2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "qemu/osdep.h"
31 #include "qemu-common.h"
33 #include "hw/boards.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/sysbus.h"
37 #include "migration/vmstate.h"
38 #include "strongarm.h"
39 #include "qemu/error-report.h"
40 #include "hw/arm/boot.h"
41 #include "chardev/char-fe.h"
42 #include "chardev/char-serial.h"
43 #include "sysemu/sysemu.h"
44 #include "hw/ssi/ssi.h"
45 #include "qemu/cutils.h"
52 - Implement cp15, c14 ?
53 - Implement cp15, c15 !!! (idle used in L)
54 - Implement idle mode handling/DIM
55 - Implement sleep mode/Wake sources
56 - Implement reset control
57 - Implement memory control regs
59 - Maybe support MBGNT/MBREQ
64 - Enhance UART with modem signals
68 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
70 # define DPRINTF(format, ...) do { } while (0)
77 { 0x80010000, SA_PIC_UART1
},
78 { 0x80030000, SA_PIC_UART2
},
79 { 0x80050000, SA_PIC_UART3
},
83 /* Interrupt Controller */
85 #define TYPE_STRONGARM_PIC "strongarm_pic"
86 #define STRONGARM_PIC(obj) \
87 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
89 typedef struct StrongARMPICState
{
90 SysBusDevice parent_obj
;
109 #define SA_PIC_SRCS 32
112 static void strongarm_pic_update(void *opaque
)
114 StrongARMPICState
*s
= opaque
;
116 /* FIXME: reflect DIM */
117 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
118 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
121 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
123 StrongARMPICState
*s
= opaque
;
126 s
->pending
|= 1 << irq
;
128 s
->pending
&= ~(1 << irq
);
131 strongarm_pic_update(s
);
134 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
137 StrongARMPICState
*s
= opaque
;
141 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
147 return s
->int_idle
== 0;
149 return s
->pending
& s
->is_fiq
& s
->enabled
;
153 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
159 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
160 uint64_t value
, unsigned size
)
162 StrongARMPICState
*s
= opaque
;
172 s
->int_idle
= (value
& 1) ? 0 : ~0;
175 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
179 strongarm_pic_update(s
);
182 static const MemoryRegionOps strongarm_pic_ops
= {
183 .read
= strongarm_pic_mem_read
,
184 .write
= strongarm_pic_mem_write
,
185 .endianness
= DEVICE_NATIVE_ENDIAN
,
188 static void strongarm_pic_initfn(Object
*obj
)
190 DeviceState
*dev
= DEVICE(obj
);
191 StrongARMPICState
*s
= STRONGARM_PIC(obj
);
192 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
194 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
195 memory_region_init_io(&s
->iomem
, obj
, &strongarm_pic_ops
, s
,
197 sysbus_init_mmio(sbd
, &s
->iomem
);
198 sysbus_init_irq(sbd
, &s
->irq
);
199 sysbus_init_irq(sbd
, &s
->fiq
);
202 static int strongarm_pic_post_load(void *opaque
, int version_id
)
204 strongarm_pic_update(opaque
);
208 static VMStateDescription vmstate_strongarm_pic_regs
= {
209 .name
= "strongarm_pic",
211 .minimum_version_id
= 0,
212 .post_load
= strongarm_pic_post_load
,
213 .fields
= (VMStateField
[]) {
214 VMSTATE_UINT32(pending
, StrongARMPICState
),
215 VMSTATE_UINT32(enabled
, StrongARMPICState
),
216 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
217 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
218 VMSTATE_END_OF_LIST(),
222 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
224 DeviceClass
*dc
= DEVICE_CLASS(klass
);
226 dc
->desc
= "StrongARM PIC";
227 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
230 static const TypeInfo strongarm_pic_info
= {
231 .name
= TYPE_STRONGARM_PIC
,
232 .parent
= TYPE_SYS_BUS_DEVICE
,
233 .instance_size
= sizeof(StrongARMPICState
),
234 .instance_init
= strongarm_pic_initfn
,
235 .class_init
= strongarm_pic_class_init
,
238 /* Real-Time Clock */
239 #define RTAR 0x00 /* RTC Alarm register */
240 #define RCNR 0x04 /* RTC Counter register */
241 #define RTTR 0x08 /* RTC Timer Trim register */
242 #define RTSR 0x10 /* RTC Status register */
244 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
245 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
246 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
247 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
249 /* 16 LSB of RTTR are clockdiv for internal trim logic,
250 * trim delete isn't emulated, so
251 * f = 32 768 / (RTTR_trim + 1) */
253 #define TYPE_STRONGARM_RTC "strongarm-rtc"
254 #define STRONGARM_RTC(obj) \
255 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
257 typedef struct StrongARMRTCState
{
258 SysBusDevice parent_obj
;
266 QEMUTimer
*rtc_alarm
;
272 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
274 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
275 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
278 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
280 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
281 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
282 (1000 * ((s
->rttr
& 0xffff) + 1));
286 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
288 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
289 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
291 timer_del(s
->rtc_hz
);
294 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
295 timer_mod(s
->rtc_alarm
, s
->last_hz
+
296 (((s
->rtar
- s
->last_rcnr
) * 1000 *
297 ((s
->rttr
& 0xffff) + 1)) >> 15));
299 timer_del(s
->rtc_alarm
);
303 static inline void strongarm_rtc_alarm_tick(void *opaque
)
305 StrongARMRTCState
*s
= opaque
;
307 strongarm_rtc_timer_update(s
);
308 strongarm_rtc_int_update(s
);
311 static inline void strongarm_rtc_hz_tick(void *opaque
)
313 StrongARMRTCState
*s
= opaque
;
315 strongarm_rtc_timer_update(s
);
316 strongarm_rtc_int_update(s
);
319 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
322 StrongARMRTCState
*s
= opaque
;
332 return s
->last_rcnr
+
333 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
334 (1000 * ((s
->rttr
& 0xffff) + 1));
336 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
341 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
342 uint64_t value
, unsigned size
)
344 StrongARMRTCState
*s
= opaque
;
349 strongarm_rtc_hzupdate(s
);
351 strongarm_rtc_timer_update(s
);
356 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
357 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
359 if (s
->rtsr
!= old_rtsr
) {
360 strongarm_rtc_timer_update(s
);
363 strongarm_rtc_int_update(s
);
368 strongarm_rtc_timer_update(s
);
372 strongarm_rtc_hzupdate(s
);
373 s
->last_rcnr
= value
;
374 strongarm_rtc_timer_update(s
);
378 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
382 static const MemoryRegionOps strongarm_rtc_ops
= {
383 .read
= strongarm_rtc_read
,
384 .write
= strongarm_rtc_write
,
385 .endianness
= DEVICE_NATIVE_ENDIAN
,
388 static void strongarm_rtc_init(Object
*obj
)
390 StrongARMRTCState
*s
= STRONGARM_RTC(obj
);
391 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
397 qemu_get_timedate(&tm
, 0);
399 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
400 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
402 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
403 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
405 sysbus_init_irq(dev
, &s
->rtc_irq
);
406 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
408 memory_region_init_io(&s
->iomem
, obj
, &strongarm_rtc_ops
, s
,
410 sysbus_init_mmio(dev
, &s
->iomem
);
413 static int strongarm_rtc_pre_save(void *opaque
)
415 StrongARMRTCState
*s
= opaque
;
417 strongarm_rtc_hzupdate(s
);
422 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
424 StrongARMRTCState
*s
= opaque
;
426 strongarm_rtc_timer_update(s
);
427 strongarm_rtc_int_update(s
);
432 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
433 .name
= "strongarm-rtc",
435 .minimum_version_id
= 0,
436 .pre_save
= strongarm_rtc_pre_save
,
437 .post_load
= strongarm_rtc_post_load
,
438 .fields
= (VMStateField
[]) {
439 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
440 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
441 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
442 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
443 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
444 VMSTATE_END_OF_LIST(),
448 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
450 DeviceClass
*dc
= DEVICE_CLASS(klass
);
452 dc
->desc
= "StrongARM RTC Controller";
453 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
456 static const TypeInfo strongarm_rtc_sysbus_info
= {
457 .name
= TYPE_STRONGARM_RTC
,
458 .parent
= TYPE_SYS_BUS_DEVICE
,
459 .instance_size
= sizeof(StrongARMRTCState
),
460 .instance_init
= strongarm_rtc_init
,
461 .class_init
= strongarm_rtc_sysbus_class_init
,
474 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
475 #define STRONGARM_GPIO(obj) \
476 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
478 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
479 struct StrongARMGPIOInfo
{
482 qemu_irq handler
[28];
498 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
501 for (i
= 0; i
< 11; i
++) {
502 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
505 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
508 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
510 StrongARMGPIOInfo
*s
= opaque
;
516 s
->status
|= s
->rising
& mask
&
517 ~s
->ilevel
& ~s
->dir
;
520 s
->status
|= s
->falling
& mask
&
525 if (s
->status
& mask
) {
526 strongarm_gpio_irq_update(s
);
530 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
532 uint32_t level
, diff
;
535 level
= s
->olevel
& s
->dir
;
537 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
539 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
542 s
->prev_level
= level
;
545 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
548 StrongARMGPIOInfo
*s
= opaque
;
551 case GPDR
: /* GPIO Pin-Direction registers */
554 case GPSR
: /* GPIO Pin-Output Set registers */
555 qemu_log_mask(LOG_GUEST_ERROR
,
556 "strongarm GPIO: read from write only register GPSR\n");
559 case GPCR
: /* GPIO Pin-Output Clear registers */
560 qemu_log_mask(LOG_GUEST_ERROR
,
561 "strongarm GPIO: read from write only register GPCR\n");
564 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
567 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
570 case GAFR
: /* GPIO Alternate Function registers */
573 case GPLR
: /* GPIO Pin-Level registers */
574 return (s
->olevel
& s
->dir
) |
575 (s
->ilevel
& ~s
->dir
);
577 case GEDR
: /* GPIO Edge Detect Status registers */
581 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
587 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
588 uint64_t value
, unsigned size
)
590 StrongARMGPIOInfo
*s
= opaque
;
593 case GPDR
: /* GPIO Pin-Direction registers */
594 s
->dir
= value
& 0x0fffffff;
595 strongarm_gpio_handler_update(s
);
598 case GPSR
: /* GPIO Pin-Output Set registers */
599 s
->olevel
|= value
& 0x0fffffff;
600 strongarm_gpio_handler_update(s
);
603 case GPCR
: /* GPIO Pin-Output Clear registers */
605 strongarm_gpio_handler_update(s
);
608 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
612 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
616 case GAFR
: /* GPIO Alternate Function registers */
620 case GEDR
: /* GPIO Edge Detect Status registers */
622 strongarm_gpio_irq_update(s
);
626 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
630 static const MemoryRegionOps strongarm_gpio_ops
= {
631 .read
= strongarm_gpio_read
,
632 .write
= strongarm_gpio_write
,
633 .endianness
= DEVICE_NATIVE_ENDIAN
,
636 static DeviceState
*strongarm_gpio_init(hwaddr base
,
642 dev
= qdev_create(NULL
, TYPE_STRONGARM_GPIO
);
643 qdev_init_nofail(dev
);
645 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
646 for (i
= 0; i
< 12; i
++)
647 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
648 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
653 static void strongarm_gpio_initfn(Object
*obj
)
655 DeviceState
*dev
= DEVICE(obj
);
656 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(obj
);
657 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
660 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
661 qdev_init_gpio_out(dev
, s
->handler
, 28);
663 memory_region_init_io(&s
->iomem
, obj
, &strongarm_gpio_ops
, s
,
666 sysbus_init_mmio(sbd
, &s
->iomem
);
667 for (i
= 0; i
< 11; i
++) {
668 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
670 sysbus_init_irq(sbd
, &s
->irqX
);
673 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
674 .name
= "strongarm-gpio",
676 .minimum_version_id
= 0,
677 .fields
= (VMStateField
[]) {
678 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
679 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
680 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
681 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
682 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
683 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
684 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
685 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
686 VMSTATE_END_OF_LIST(),
690 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
692 DeviceClass
*dc
= DEVICE_CLASS(klass
);
694 dc
->desc
= "StrongARM GPIO controller";
695 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
698 static const TypeInfo strongarm_gpio_info
= {
699 .name
= TYPE_STRONGARM_GPIO
,
700 .parent
= TYPE_SYS_BUS_DEVICE
,
701 .instance_size
= sizeof(StrongARMGPIOInfo
),
702 .instance_init
= strongarm_gpio_initfn
,
703 .class_init
= strongarm_gpio_class_init
,
706 /* Peripheral Pin Controller */
713 #define TYPE_STRONGARM_PPC "strongarm-ppc"
714 #define STRONGARM_PPC(obj) \
715 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
717 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
718 struct StrongARMPPCInfo
{
719 SysBusDevice parent_obj
;
722 qemu_irq handler
[28];
734 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
736 StrongARMPPCInfo
*s
= opaque
;
739 s
->ilevel
|= 1 << line
;
741 s
->ilevel
&= ~(1 << line
);
745 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
747 uint32_t level
, diff
;
750 level
= s
->olevel
& s
->dir
;
752 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
754 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
757 s
->prev_level
= level
;
760 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
763 StrongARMPPCInfo
*s
= opaque
;
766 case PPDR
: /* PPC Pin Direction registers */
767 return s
->dir
| ~0x3fffff;
769 case PPSR
: /* PPC Pin State registers */
770 return (s
->olevel
& s
->dir
) |
771 (s
->ilevel
& ~s
->dir
) |
775 return s
->ppar
| ~0x41000;
781 return s
->ppfr
| ~0x7f001;
784 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
790 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
791 uint64_t value
, unsigned size
)
793 StrongARMPPCInfo
*s
= opaque
;
796 case PPDR
: /* PPC Pin Direction registers */
797 s
->dir
= value
& 0x3fffff;
798 strongarm_ppc_handler_update(s
);
801 case PPSR
: /* PPC Pin State registers */
802 s
->olevel
= value
& s
->dir
& 0x3fffff;
803 strongarm_ppc_handler_update(s
);
807 s
->ppar
= value
& 0x41000;
811 s
->psdr
= value
& 0x3fffff;
815 s
->ppfr
= value
& 0x7f001;
819 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
823 static const MemoryRegionOps strongarm_ppc_ops
= {
824 .read
= strongarm_ppc_read
,
825 .write
= strongarm_ppc_write
,
826 .endianness
= DEVICE_NATIVE_ENDIAN
,
829 static void strongarm_ppc_init(Object
*obj
)
831 DeviceState
*dev
= DEVICE(obj
);
832 StrongARMPPCInfo
*s
= STRONGARM_PPC(obj
);
833 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
835 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
836 qdev_init_gpio_out(dev
, s
->handler
, 22);
838 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ppc_ops
, s
,
841 sysbus_init_mmio(sbd
, &s
->iomem
);
844 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
845 .name
= "strongarm-ppc",
847 .minimum_version_id
= 0,
848 .fields
= (VMStateField
[]) {
849 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
850 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
851 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
852 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
853 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
854 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
855 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
856 VMSTATE_END_OF_LIST(),
860 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
862 DeviceClass
*dc
= DEVICE_CLASS(klass
);
864 dc
->desc
= "StrongARM PPC controller";
865 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
868 static const TypeInfo strongarm_ppc_info
= {
869 .name
= TYPE_STRONGARM_PPC
,
870 .parent
= TYPE_SYS_BUS_DEVICE
,
871 .instance_size
= sizeof(StrongARMPPCInfo
),
872 .instance_init
= strongarm_ppc_init
,
873 .class_init
= strongarm_ppc_class_init
,
885 #define UTCR0_PE (1 << 0) /* Parity enable */
886 #define UTCR0_OES (1 << 1) /* Even parity */
887 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
888 #define UTCR0_DSS (1 << 3) /* 8-bit data */
890 #define UTCR3_RXE (1 << 0) /* Rx enable */
891 #define UTCR3_TXE (1 << 1) /* Tx enable */
892 #define UTCR3_BRK (1 << 2) /* Force Break */
893 #define UTCR3_RIE (1 << 3) /* Rx int enable */
894 #define UTCR3_TIE (1 << 4) /* Tx int enable */
895 #define UTCR3_LBM (1 << 5) /* Loopback */
897 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
898 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
899 #define UTSR0_RID (1 << 2) /* Receiver Idle */
900 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
901 #define UTSR0_REB (1 << 4) /* Receiver end break */
902 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
904 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
905 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
906 #define UTSR1_PRE (1 << 3) /* Parity error */
907 #define UTSR1_FRE (1 << 4) /* Frame error */
908 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
910 #define RX_FIFO_PRE (1 << 8)
911 #define RX_FIFO_FRE (1 << 9)
912 #define RX_FIFO_ROR (1 << 10)
914 #define TYPE_STRONGARM_UART "strongarm-uart"
915 #define STRONGARM_UART(obj) \
916 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
918 typedef struct StrongARMUARTState
{
919 SysBusDevice parent_obj
;
934 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
938 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
940 QEMUTimer
*rx_timeout_timer
;
942 } StrongARMUARTState
;
944 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
948 if (s
->tx_len
!= 8) {
952 if (s
->rx_len
!= 0) {
953 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
956 if (ent
& RX_FIFO_PRE
) {
957 s
->utsr1
|= UTSR1_PRE
;
959 if (ent
& RX_FIFO_FRE
) {
960 s
->utsr1
|= UTSR1_FRE
;
962 if (ent
& RX_FIFO_ROR
) {
963 s
->utsr1
|= UTSR1_ROR
;
970 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
972 uint16_t utsr0
= s
->utsr0
&
973 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
976 if ((s
->utcr3
& UTCR3_TXE
) &&
977 (s
->utcr3
& UTCR3_TIE
) &&
982 if ((s
->utcr3
& UTCR3_RXE
) &&
983 (s
->utcr3
& UTCR3_RIE
) &&
988 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
989 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
995 qemu_set_irq(s
->irq
, utsr0
);
998 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
1000 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
1001 QEMUSerialSetParams ssp
;
1005 if (s
->utcr0
& UTCR0_PE
) {
1008 if (s
->utcr0
& UTCR0_OES
) {
1016 if (s
->utcr0
& UTCR0_SBS
) {
1022 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1023 frame_size
+= data_bits
+ stop_bits
;
1024 speed
= 3686400 / 16 / (s
->brd
+ 1);
1026 ssp
.parity
= parity
;
1027 ssp
.data_bits
= data_bits
;
1028 ssp
.stop_bits
= stop_bits
;
1029 s
->char_transmit_time
= (NANOSECONDS_PER_SECOND
/ speed
) * frame_size
;
1030 qemu_chr_fe_ioctl(&s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1032 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1033 speed
, parity
, data_bits
, stop_bits
);
1036 static void strongarm_uart_rx_to(void *opaque
)
1038 StrongARMUARTState
*s
= opaque
;
1041 s
->utsr0
|= UTSR0_RID
;
1042 strongarm_uart_update_int_status(s
);
1046 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1048 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1053 if (s
->wait_break_end
) {
1054 s
->utsr0
|= UTSR0_REB
;
1055 s
->wait_break_end
= false;
1058 if (s
->rx_len
< 12) {
1059 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1062 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1065 static int strongarm_uart_can_receive(void *opaque
)
1067 StrongARMUARTState
*s
= opaque
;
1069 if (s
->rx_len
== 12) {
1072 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1073 if (s
->rx_len
< 8) {
1074 return 8 - s
->rx_len
;
1079 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1081 StrongARMUARTState
*s
= opaque
;
1084 for (i
= 0; i
< size
; i
++) {
1085 strongarm_uart_rx_push(s
, buf
[i
]);
1088 /* call the timeout receive callback in 3 char transmit time */
1089 timer_mod(s
->rx_timeout_timer
,
1090 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1092 strongarm_uart_update_status(s
);
1093 strongarm_uart_update_int_status(s
);
1096 static void strongarm_uart_event(void *opaque
, int event
)
1098 StrongARMUARTState
*s
= opaque
;
1099 if (event
== CHR_EVENT_BREAK
) {
1100 s
->utsr0
|= UTSR0_RBB
;
1101 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1102 s
->wait_break_end
= true;
1103 strongarm_uart_update_status(s
);
1104 strongarm_uart_update_int_status(s
);
1108 static void strongarm_uart_tx(void *opaque
)
1110 StrongARMUARTState
*s
= opaque
;
1111 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1113 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1114 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1115 } else if (qemu_chr_fe_backend_connected(&s
->chr
)) {
1116 /* XXX this blocks entire thread. Rewrite to use
1117 * qemu_chr_fe_write and background I/O callbacks */
1118 qemu_chr_fe_write_all(&s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1121 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1124 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1126 strongarm_uart_update_status(s
);
1127 strongarm_uart_update_int_status(s
);
1130 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1133 StrongARMUARTState
*s
= opaque
;
1144 return s
->brd
& 0xff;
1150 if (s
->rx_len
!= 0) {
1151 ret
= s
->rx_fifo
[s
->rx_start
];
1152 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1154 strongarm_uart_update_status(s
);
1155 strongarm_uart_update_int_status(s
);
1167 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1172 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1173 uint64_t value
, unsigned size
)
1175 StrongARMUARTState
*s
= opaque
;
1179 s
->utcr0
= value
& 0x7f;
1180 strongarm_uart_update_parameters(s
);
1184 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1185 strongarm_uart_update_parameters(s
);
1189 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1190 strongarm_uart_update_parameters(s
);
1194 s
->utcr3
= value
& 0x3f;
1195 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1198 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1201 strongarm_uart_update_status(s
);
1202 strongarm_uart_update_int_status(s
);
1206 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1207 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1209 strongarm_uart_update_status(s
);
1210 strongarm_uart_update_int_status(s
);
1211 if (s
->tx_len
== 1) {
1212 strongarm_uart_tx(s
);
1218 s
->utsr0
= s
->utsr0
& ~(value
&
1219 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1220 strongarm_uart_update_int_status(s
);
1224 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1228 static const MemoryRegionOps strongarm_uart_ops
= {
1229 .read
= strongarm_uart_read
,
1230 .write
= strongarm_uart_write
,
1231 .endianness
= DEVICE_NATIVE_ENDIAN
,
1234 static void strongarm_uart_init(Object
*obj
)
1236 StrongARMUARTState
*s
= STRONGARM_UART(obj
);
1237 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1239 memory_region_init_io(&s
->iomem
, obj
, &strongarm_uart_ops
, s
,
1241 sysbus_init_mmio(dev
, &s
->iomem
);
1242 sysbus_init_irq(dev
, &s
->irq
);
1244 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_rx_to
, s
);
1245 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1248 static void strongarm_uart_realize(DeviceState
*dev
, Error
**errp
)
1250 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1252 qemu_chr_fe_set_handlers(&s
->chr
,
1253 strongarm_uart_can_receive
,
1254 strongarm_uart_receive
,
1255 strongarm_uart_event
,
1256 NULL
, s
, NULL
, true);
1259 static void strongarm_uart_reset(DeviceState
*dev
)
1261 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1263 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1264 s
->brd
= 23; /* 9600 */
1265 /* enable send & recv - this actually violates spec */
1266 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1268 s
->rx_len
= s
->tx_len
= 0;
1270 strongarm_uart_update_parameters(s
);
1271 strongarm_uart_update_status(s
);
1272 strongarm_uart_update_int_status(s
);
1275 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1277 StrongARMUARTState
*s
= opaque
;
1279 strongarm_uart_update_parameters(s
);
1280 strongarm_uart_update_status(s
);
1281 strongarm_uart_update_int_status(s
);
1283 /* tx and restart timer */
1285 strongarm_uart_tx(s
);
1288 /* restart rx timeout timer */
1290 timer_mod(s
->rx_timeout_timer
,
1291 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1297 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1298 .name
= "strongarm-uart",
1300 .minimum_version_id
= 0,
1301 .post_load
= strongarm_uart_post_load
,
1302 .fields
= (VMStateField
[]) {
1303 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1304 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1305 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1306 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1307 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1308 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1309 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1310 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1311 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1312 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1313 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1314 VMSTATE_END_OF_LIST(),
1318 static Property strongarm_uart_properties
[] = {
1319 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1320 DEFINE_PROP_END_OF_LIST(),
1323 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1325 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1327 dc
->desc
= "StrongARM UART controller";
1328 dc
->reset
= strongarm_uart_reset
;
1329 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1330 dc
->props
= strongarm_uart_properties
;
1331 dc
->realize
= strongarm_uart_realize
;
1334 static const TypeInfo strongarm_uart_info
= {
1335 .name
= TYPE_STRONGARM_UART
,
1336 .parent
= TYPE_SYS_BUS_DEVICE
,
1337 .instance_size
= sizeof(StrongARMUARTState
),
1338 .instance_init
= strongarm_uart_init
,
1339 .class_init
= strongarm_uart_class_init
,
1342 /* Synchronous Serial Ports */
1344 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1345 #define STRONGARM_SSP(obj) \
1346 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1348 typedef struct StrongARMSSPState
{
1349 SysBusDevice parent_obj
;
1358 uint16_t rx_fifo
[8];
1361 } StrongARMSSPState
;
1363 #define SSCR0 0x60 /* SSP Control register 0 */
1364 #define SSCR1 0x64 /* SSP Control register 1 */
1365 #define SSDR 0x6c /* SSP Data register */
1366 #define SSSR 0x74 /* SSP Status register */
1368 /* Bitfields for above registers */
1369 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1370 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1371 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1372 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1373 #define SSCR0_SSE (1 << 7)
1374 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1375 #define SSCR1_RIE (1 << 0)
1376 #define SSCR1_TIE (1 << 1)
1377 #define SSCR1_LBM (1 << 2)
1378 #define SSSR_TNF (1 << 2)
1379 #define SSSR_RNE (1 << 3)
1380 #define SSSR_TFS (1 << 5)
1381 #define SSSR_RFS (1 << 6)
1382 #define SSSR_ROR (1 << 7)
1383 #define SSSR_RW 0x0080
1385 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1389 level
|= (s
->sssr
& SSSR_ROR
);
1390 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1391 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1392 qemu_set_irq(s
->irq
, level
);
1395 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1397 s
->sssr
&= ~SSSR_TFS
;
1398 s
->sssr
&= ~SSSR_TNF
;
1399 if (s
->sscr
[0] & SSCR0_SSE
) {
1400 if (s
->rx_level
>= 4) {
1401 s
->sssr
|= SSSR_RFS
;
1403 s
->sssr
&= ~SSSR_RFS
;
1406 s
->sssr
|= SSSR_RNE
;
1408 s
->sssr
&= ~SSSR_RNE
;
1410 /* TX FIFO is never filled, so it is always in underrun
1411 condition if SSP is enabled */
1412 s
->sssr
|= SSSR_TFS
;
1413 s
->sssr
|= SSSR_TNF
;
1416 strongarm_ssp_int_update(s
);
1419 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1422 StrongARMSSPState
*s
= opaque
;
1433 if (~s
->sscr
[0] & SSCR0_SSE
) {
1436 if (s
->rx_level
< 1) {
1437 printf("%s: SSP Rx Underrun\n", __func__
);
1441 retval
= s
->rx_fifo
[s
->rx_start
++];
1443 strongarm_ssp_fifo_update(s
);
1446 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1452 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1453 uint64_t value
, unsigned size
)
1455 StrongARMSSPState
*s
= opaque
;
1459 s
->sscr
[0] = value
& 0xffbf;
1460 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1461 printf("%s: Wrong data size: %i bits\n", __func__
,
1462 (int)SSCR0_DSS(value
));
1464 if (!(value
& SSCR0_SSE
)) {
1468 strongarm_ssp_fifo_update(s
);
1472 s
->sscr
[1] = value
& 0x2f;
1473 if (value
& SSCR1_LBM
) {
1474 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1476 strongarm_ssp_fifo_update(s
);
1480 s
->sssr
&= ~(value
& SSSR_RW
);
1481 strongarm_ssp_int_update(s
);
1485 if (SSCR0_UWIRE(s
->sscr
[0])) {
1488 /* Note how 32bits overflow does no harm here */
1489 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1491 /* Data goes from here to the Tx FIFO and is shifted out from
1492 * there directly to the slave, no need to buffer it.
1494 if (s
->sscr
[0] & SSCR0_SSE
) {
1496 if (s
->sscr
[1] & SSCR1_LBM
) {
1499 readval
= ssi_transfer(s
->bus
, value
);
1502 if (s
->rx_level
< 0x08) {
1503 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1505 s
->sssr
|= SSSR_ROR
;
1508 strongarm_ssp_fifo_update(s
);
1512 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1517 static const MemoryRegionOps strongarm_ssp_ops
= {
1518 .read
= strongarm_ssp_read
,
1519 .write
= strongarm_ssp_write
,
1520 .endianness
= DEVICE_NATIVE_ENDIAN
,
1523 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1525 StrongARMSSPState
*s
= opaque
;
1527 strongarm_ssp_fifo_update(s
);
1532 static void strongarm_ssp_init(Object
*obj
)
1534 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
1535 DeviceState
*dev
= DEVICE(sbd
);
1536 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1538 sysbus_init_irq(sbd
, &s
->irq
);
1540 memory_region_init_io(&s
->iomem
, obj
, &strongarm_ssp_ops
, s
,
1542 sysbus_init_mmio(sbd
, &s
->iomem
);
1544 s
->bus
= ssi_create_bus(dev
, "ssi");
1547 static void strongarm_ssp_reset(DeviceState
*dev
)
1549 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1551 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1556 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1557 .name
= "strongarm-ssp",
1559 .minimum_version_id
= 0,
1560 .post_load
= strongarm_ssp_post_load
,
1561 .fields
= (VMStateField
[]) {
1562 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1563 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1564 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1565 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1566 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1567 VMSTATE_END_OF_LIST(),
1571 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1573 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1575 dc
->desc
= "StrongARM SSP controller";
1576 dc
->reset
= strongarm_ssp_reset
;
1577 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1580 static const TypeInfo strongarm_ssp_info
= {
1581 .name
= TYPE_STRONGARM_SSP
,
1582 .parent
= TYPE_SYS_BUS_DEVICE
,
1583 .instance_size
= sizeof(StrongARMSSPState
),
1584 .instance_init
= strongarm_ssp_init
,
1585 .class_init
= strongarm_ssp_class_init
,
1588 /* Main CPU functions */
1589 StrongARMState
*sa1110_init(MemoryRegion
*sysmem
,
1590 unsigned int sdram_size
, const char *cpu_type
)
1595 s
= g_new0(StrongARMState
, 1);
1597 if (strncmp(cpu_type
, "sa1110", 6)) {
1598 error_report("Machine requires a SA1110 processor.");
1602 s
->cpu
= ARM_CPU(cpu_create(cpu_type
));
1604 memory_region_allocate_system_memory(&s
->sdram
, NULL
, "strongarm.sdram",
1606 memory_region_add_subregion(sysmem
, SA_SDCS0
, &s
->sdram
);
1608 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1609 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1610 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1613 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1614 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1615 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1616 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1617 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1620 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1621 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1623 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1625 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1627 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1628 DeviceState
*dev
= qdev_create(NULL
, TYPE_STRONGARM_UART
);
1629 qdev_prop_set_chr(dev
, "chardev", serial_hd(i
));
1630 qdev_init_nofail(dev
);
1631 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1632 sa_serial
[i
].io_base
);
1633 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1634 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1637 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1638 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1639 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1644 static void strongarm_register_types(void)
1646 type_register_static(&strongarm_pic_info
);
1647 type_register_static(&strongarm_rtc_sysbus_info
);
1648 type_register_static(&strongarm_gpio_info
);
1649 type_register_static(&strongarm_ppc_info
);
1650 type_register_static(&strongarm_uart_info
);
1651 type_register_static(&strongarm_ssp_info
);
1654 type_init(strongarm_register_types
)