hw/i386/kvm/apic.c

   1 /*
   2  * KVM in-kernel APIC support
   3  *
   4  * Copyright (c) 2011 Siemens AG
   5  *
   6  * Authors:
   7  *  Jan Kiszka          <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL version 2.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qemu/module.h"
  15 #include "cpu.h"
  16 #include "hw/i386/apic_internal.h"
  17 #include "hw/pci/msi.h"
  18 #include "sysemu/hw_accel.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/i386/kvm_i386.h"
  21
  22 static inline void kvm_apic_set_reg(struct kvm_lapic_state *kapic,
  23                                     int reg_id, uint32_t val)
  24 {
  25     *((uint32_t *)(kapic->regs + (reg_id << 4))) = val;
  26 }
  27
  28 static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic,
  29                                         int reg_id)
  30 {
  31     return *((uint32_t *)(kapic->regs + (reg_id << 4)));
  32 }
  33
  34 static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic)
  35 {
  36     int i;
  37
  38     memset(kapic, 0, sizeof(*kapic));
  39     if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) {
  40         kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id);
  41     } else {
  42         kvm_apic_set_reg(kapic, 0x2, s->id << 24);
  43     }
  44     kvm_apic_set_reg(kapic, 0x8, s->tpr);
  45     kvm_apic_set_reg(kapic, 0xd, s->log_dest << 24);
  46     kvm_apic_set_reg(kapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
  47     kvm_apic_set_reg(kapic, 0xf, s->spurious_vec);
  48     for (i = 0; i < 8; i++) {
  49         kvm_apic_set_reg(kapic, 0x10 + i, s->isr[i]);
  50         kvm_apic_set_reg(kapic, 0x18 + i, s->tmr[i]);
  51         kvm_apic_set_reg(kapic, 0x20 + i, s->irr[i]);
  52     }
  53     kvm_apic_set_reg(kapic, 0x28, s->esr);
  54     kvm_apic_set_reg(kapic, 0x30, s->icr[0]);
  55     kvm_apic_set_reg(kapic, 0x31, s->icr[1]);
  56     for (i = 0; i < APIC_LVT_NB; i++) {
  57         kvm_apic_set_reg(kapic, 0x32 + i, s->lvt[i]);
  58     }
  59     kvm_apic_set_reg(kapic, 0x38, s->initial_count);
  60     kvm_apic_set_reg(kapic, 0x3e, s->divide_conf);
  61 }
  62
  63 void kvm_get_apic_state(DeviceState *dev, struct kvm_lapic_state *kapic)
  64 {
  65     APICCommonState *s = APIC_COMMON(dev);
  66     int i, v;
  67
  68     if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) {
  69         assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id);
  70     } else {
  71         s->id = kvm_apic_get_reg(kapic, 0x2) >> 24;
  72     }
  73     s->tpr = kvm_apic_get_reg(kapic, 0x8);
  74     s->arb_id = kvm_apic_get_reg(kapic, 0x9);
  75     s->log_dest = kvm_apic_get_reg(kapic, 0xd) >> 24;
  76     s->dest_mode = kvm_apic_get_reg(kapic, 0xe) >> 28;
  77     s->spurious_vec = kvm_apic_get_reg(kapic, 0xf);
  78     for (i = 0; i < 8; i++) {
  79         s->isr[i] = kvm_apic_get_reg(kapic, 0x10 + i);
  80         s->tmr[i] = kvm_apic_get_reg(kapic, 0x18 + i);
  81         s->irr[i] = kvm_apic_get_reg(kapic, 0x20 + i);
  82     }
  83     s->esr = kvm_apic_get_reg(kapic, 0x28);
  84     s->icr[0] = kvm_apic_get_reg(kapic, 0x30);
  85     s->icr[1] = kvm_apic_get_reg(kapic, 0x31);
  86     for (i = 0; i < APIC_LVT_NB; i++) {
  87         s->lvt[i] = kvm_apic_get_reg(kapic, 0x32 + i);
  88     }
  89     s->initial_count = kvm_apic_get_reg(kapic, 0x38);
  90     s->divide_conf = kvm_apic_get_reg(kapic, 0x3e);
  91
  92     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
  93     s->count_shift = (v + 1) & 7;
  94
  95     s->initial_count_load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  96     apic_next_timer(s, s->initial_count_load_time);
  97 }
  98
  99 static void kvm_apic_set_base(APICCommonState *s, uint64_t val)
 100 {
 101     s->apicbase = val;
 102 }
 103
 104 static void kvm_apic_set_tpr(APICCommonState *s, uint8_t val)
 105 {
 106     s->tpr = (val & 0x0f) << 4;
 107 }
 108
 109 static uint8_t kvm_apic_get_tpr(APICCommonState *s)
 110 {
 111     return s->tpr >> 4;
 112 }
 113
 114 static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
 115 {
 116     struct kvm_tpr_access_ctl ctl = {
 117         .enabled = enable
 118     };
 119
 120     kvm_vcpu_ioctl(CPU(s->cpu), KVM_TPR_ACCESS_REPORTING, &ctl);
 121 }
 122
 123 static void kvm_apic_vapic_base_update(APICCommonState *s)
 124 {
 125     struct kvm_vapic_addr vapid_addr = {
 126         .vapic_addr = s->vapic_paddr,
 127     };
 128     int ret;
 129
 130     ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_VAPIC_ADDR, &vapid_addr);
 131     if (ret < 0) {
 132         fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
 133                 strerror(-ret));
 134         abort();
 135     }
 136 }
 137
 138 static void kvm_apic_put(CPUState *cs, run_on_cpu_data data)
 139 {
 140     APICCommonState *s = data.host_ptr;
 141     struct kvm_lapic_state kapic;
 142     int ret;
 143
 144     kvm_put_apicbase(s->cpu, s->apicbase);
 145     kvm_put_apic_state(s, &kapic);
 146
 147     ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic);
 148     if (ret < 0) {
 149         fprintf(stderr, "KVM_SET_LAPIC failed: %s\n", strerror(ret));
 150         abort();
 151     }
 152 }
 153
 154 static void kvm_apic_post_load(APICCommonState *s)
 155 {
 156     run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s));
 157 }
 158
 159 static void do_inject_external_nmi(CPUState *cpu, run_on_cpu_data data)
 160 {
 161     APICCommonState *s = data.host_ptr;
 162     uint32_t lvt;
 163     int ret;
 164
 165     cpu_synchronize_state(cpu);
 166
 167     lvt = s->lvt[APIC_LVT_LINT1];
 168     if (!(lvt & APIC_LVT_MASKED) && ((lvt >> 8) & 7) == APIC_DM_NMI) {
 169         ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
 170         if (ret < 0) {
 171             fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
 172                     strerror(-ret));
 173         }
 174     }
 175 }
 176
 177 static void kvm_apic_external_nmi(APICCommonState *s)
 178 {
 179     run_on_cpu(CPU(s->cpu), do_inject_external_nmi, RUN_ON_CPU_HOST_PTR(s));
 180 }
 181
 182 static void kvm_send_msi(MSIMessage *msg)
 183 {
 184     int ret;
 185
 186     ret = kvm_irqchip_send_msi(kvm_state, *msg);
 187     if (ret < 0) {
 188         fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n",
 189                 strerror(-ret));
 190     }
 191 }
 192
 193 static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr,
 194                                   unsigned size)
 195 {
 196     return ~(uint64_t)0;
 197 }
 198
 199 static void kvm_apic_mem_write(void *opaque, hwaddr addr,
 200                                uint64_t data, unsigned size)
 201 {
 202     MSIMessage msg = { .address = addr, .data = data };
 203
 204     kvm_send_msi(&msg);
 205 }
 206
 207 static const MemoryRegionOps kvm_apic_io_ops = {
 208     .read = kvm_apic_mem_read,
 209     .write = kvm_apic_mem_write,
 210     .endianness = DEVICE_NATIVE_ENDIAN,
 211 };
 212
 213 static void kvm_apic_reset(APICCommonState *s)
 214 {
 215     /* Not used by KVM, which uses the CPU mp_state instead.  */
 216     s->wait_for_sipi = 0;
 217
 218     run_on_cpu(CPU(s->cpu), kvm_apic_put, RUN_ON_CPU_HOST_PTR(s));
 219 }
 220
 221 static void kvm_apic_realize(DeviceState *dev, Error **errp)
 222 {
 223     APICCommonState *s = APIC_COMMON(dev);
 224
 225     memory_region_init_io(&s->io_memory, OBJECT(s), &kvm_apic_io_ops, s,
 226                           "kvm-apic-msi", APIC_SPACE_SIZE);
 227
 228     if (kvm_has_gsi_routing()) {
 229         msi_nonbroken = true;
 230     }
 231 }
 232
 233 static void kvm_apic_unrealize(DeviceState *dev, Error **errp)
 234 {
 235 }
 236
 237 static void kvm_apic_class_init(ObjectClass *klass, void *data)
 238 {
 239     APICCommonClass *k = APIC_COMMON_CLASS(klass);
 240
 241     k->realize = kvm_apic_realize;
 242     k->unrealize = kvm_apic_unrealize;
 243     k->reset = kvm_apic_reset;
 244     k->set_base = kvm_apic_set_base;
 245     k->set_tpr = kvm_apic_set_tpr;
 246     k->get_tpr = kvm_apic_get_tpr;
 247     k->post_load = kvm_apic_post_load;
 248     k->enable_tpr_reporting = kvm_apic_enable_tpr_reporting;
 249     k->vapic_base_update = kvm_apic_vapic_base_update;
 250     k->external_nmi = kvm_apic_external_nmi;
 251     k->send_msi = kvm_send_msi;
 252 }
 253
 254 static const TypeInfo kvm_apic_info = {
 255     .name = "kvm-apic",
 256     .parent = TYPE_APIC_COMMON,
 257     .instance_size = sizeof(APICCommonState),
 258     .class_init = kvm_apic_class_init,
 259 };
 260
 261 static void kvm_apic_register_types(void)
 262 {
 263     type_register_static(&kvm_apic_info);
 264 }
 265
 266 type_init(kvm_apic_register_types)