hw/misc/aspeed_scu.c

   1 /*
   2  * ASPEED System Control Unit
   3  *
   4  * Andrew Jeffery <andrew@aj.id.au>
   5  *
   6  * Copyright 2016 IBM Corp.
   7  *
   8  * This code is licensed under the GPL version 2 or later.  See
   9  * the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "hw/misc/aspeed_scu.h"
  14 #include "hw/qdev-properties.h"
  15 #include "migration/vmstate.h"
  16 #include "qapi/error.h"
  17 #include "qapi/visitor.h"
  18 #include "qemu/bitops.h"
  19 #include "qemu/log.h"
  20 #include "qemu/guest-random.h"
  21 #include "qemu/module.h"
  22 #include "trace.h"
  23
  24 #define TO_REG(offset) ((offset) >> 2)
  25
  26 #define PROT_KEY             TO_REG(0x00)
  27 #define SYS_RST_CTRL         TO_REG(0x04)
  28 #define CLK_SEL              TO_REG(0x08)
  29 #define CLK_STOP_CTRL        TO_REG(0x0C)
  30 #define FREQ_CNTR_CTRL       TO_REG(0x10)
  31 #define FREQ_CNTR_EVAL       TO_REG(0x14)
  32 #define IRQ_CTRL             TO_REG(0x18)
  33 #define D2PLL_PARAM          TO_REG(0x1C)
  34 #define MPLL_PARAM           TO_REG(0x20)
  35 #define HPLL_PARAM           TO_REG(0x24)
  36 #define FREQ_CNTR_RANGE      TO_REG(0x28)
  37 #define MISC_CTRL1           TO_REG(0x2C)
  38 #define PCI_CTRL1            TO_REG(0x30)
  39 #define PCI_CTRL2            TO_REG(0x34)
  40 #define PCI_CTRL3            TO_REG(0x38)
  41 #define SYS_RST_STATUS       TO_REG(0x3C)
  42 #define SOC_SCRATCH1         TO_REG(0x40)
  43 #define SOC_SCRATCH2         TO_REG(0x44)
  44 #define MAC_CLK_DELAY        TO_REG(0x48)
  45 #define MISC_CTRL2           TO_REG(0x4C)
  46 #define VGA_SCRATCH1         TO_REG(0x50)
  47 #define VGA_SCRATCH2         TO_REG(0x54)
  48 #define VGA_SCRATCH3         TO_REG(0x58)
  49 #define VGA_SCRATCH4         TO_REG(0x5C)
  50 #define VGA_SCRATCH5         TO_REG(0x60)
  51 #define VGA_SCRATCH6         TO_REG(0x64)
  52 #define VGA_SCRATCH7         TO_REG(0x68)
  53 #define VGA_SCRATCH8         TO_REG(0x6C)
  54 #define HW_STRAP1            TO_REG(0x70)
  55 #define RNG_CTRL             TO_REG(0x74)
  56 #define RNG_DATA             TO_REG(0x78)
  57 #define SILICON_REV          TO_REG(0x7C)
  58 #define PINMUX_CTRL1         TO_REG(0x80)
  59 #define PINMUX_CTRL2         TO_REG(0x84)
  60 #define PINMUX_CTRL3         TO_REG(0x88)
  61 #define PINMUX_CTRL4         TO_REG(0x8C)
  62 #define PINMUX_CTRL5         TO_REG(0x90)
  63 #define PINMUX_CTRL6         TO_REG(0x94)
  64 #define WDT_RST_CTRL         TO_REG(0x9C)
  65 #define PINMUX_CTRL7         TO_REG(0xA0)
  66 #define PINMUX_CTRL8         TO_REG(0xA4)
  67 #define PINMUX_CTRL9         TO_REG(0xA8)
  68 #define WAKEUP_EN            TO_REG(0xC0)
  69 #define WAKEUP_CTRL          TO_REG(0xC4)
  70 #define HW_STRAP2            TO_REG(0xD0)
  71 #define FREE_CNTR4           TO_REG(0xE0)
  72 #define FREE_CNTR4_EXT       TO_REG(0xE4)
  73 #define CPU2_CTRL            TO_REG(0x100)
  74 #define CPU2_BASE_SEG1       TO_REG(0x104)
  75 #define CPU2_BASE_SEG2       TO_REG(0x108)
  76 #define CPU2_BASE_SEG3       TO_REG(0x10C)
  77 #define CPU2_BASE_SEG4       TO_REG(0x110)
  78 #define CPU2_BASE_SEG5       TO_REG(0x114)
  79 #define CPU2_CACHE_CTRL      TO_REG(0x118)
  80 #define UART_HPLL_CLK        TO_REG(0x160)
  81 #define PCIE_CTRL            TO_REG(0x180)
  82 #define BMC_MMIO_CTRL        TO_REG(0x184)
  83 #define RELOC_DECODE_BASE1   TO_REG(0x188)
  84 #define RELOC_DECODE_BASE2   TO_REG(0x18C)
  85 #define MAILBOX_DECODE_BASE  TO_REG(0x190)
  86 #define SRAM_DECODE_BASE1    TO_REG(0x194)
  87 #define SRAM_DECODE_BASE2    TO_REG(0x198)
  88 #define BMC_REV              TO_REG(0x19C)
  89 #define BMC_DEV_ID           TO_REG(0x1A4)
  90
  91 #define SCU_IO_REGION_SIZE 0x1000
  92
  93 static const uint32_t ast2400_a0_resets[ASPEED_SCU_NR_REGS] = {
  94      [SYS_RST_CTRL]    = 0xFFCFFEDCU,
  95      [CLK_SEL]         = 0xF3F40000U,
  96      [CLK_STOP_CTRL]   = 0x19FC3E8BU,
  97      [D2PLL_PARAM]     = 0x00026108U,
  98      [MPLL_PARAM]      = 0x00030291U,
  99      [HPLL_PARAM]      = 0x00000291U,
 100      [MISC_CTRL1]      = 0x00000010U,
 101      [PCI_CTRL1]       = 0x20001A03U,
 102      [PCI_CTRL2]       = 0x20001A03U,
 103      [PCI_CTRL3]       = 0x04000030U,
 104      [SYS_RST_STATUS]  = 0x00000001U,
 105      [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
 106      [MISC_CTRL2]      = 0x00000023U,
 107      [RNG_CTRL]        = 0x0000000EU,
 108      [PINMUX_CTRL2]    = 0x0000F000U,
 109      [PINMUX_CTRL3]    = 0x01000000U,
 110      [PINMUX_CTRL4]    = 0x000000FFU,
 111      [PINMUX_CTRL5]    = 0x0000A000U,
 112      [WDT_RST_CTRL]    = 0x003FFFF3U,
 113      [PINMUX_CTRL8]    = 0xFFFF0000U,
 114      [PINMUX_CTRL9]    = 0x000FFFFFU,
 115      [FREE_CNTR4]      = 0x000000FFU,
 116      [FREE_CNTR4_EXT]  = 0x000000FFU,
 117      [CPU2_BASE_SEG1]  = 0x80000000U,
 118      [CPU2_BASE_SEG4]  = 0x1E600000U,
 119      [CPU2_BASE_SEG5]  = 0xC0000000U,
 120      [UART_HPLL_CLK]   = 0x00001903U,
 121      [PCIE_CTRL]       = 0x0000007BU,
 122      [BMC_DEV_ID]      = 0x00002402U
 123 };
 124
 125 /* SCU70 bit 23: 0 24Mhz. bit 11:9: 0b001 AXI:ABH ratio 2:1 */
 126 /* AST2500 revision A1 */
 127
 128 static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_REGS] = {
 129      [SYS_RST_CTRL]    = 0xFFCFFEDCU,
 130      [CLK_SEL]         = 0xF3F40000U,
 131      [CLK_STOP_CTRL]   = 0x19FC3E8BU,
 132      [D2PLL_PARAM]     = 0x00026108U,
 133      [MPLL_PARAM]      = 0x00030291U,
 134      [HPLL_PARAM]      = 0x93000400U,
 135      [MISC_CTRL1]      = 0x00000010U,
 136      [PCI_CTRL1]       = 0x20001A03U,
 137      [PCI_CTRL2]       = 0x20001A03U,
 138      [PCI_CTRL3]       = 0x04000030U,
 139      [SYS_RST_STATUS]  = 0x00000001U,
 140      [SOC_SCRATCH1]    = 0x000000C0U, /* SoC completed DRAM init */
 141      [MISC_CTRL2]      = 0x00000023U,
 142      [RNG_CTRL]        = 0x0000000EU,
 143      [PINMUX_CTRL2]    = 0x0000F000U,
 144      [PINMUX_CTRL3]    = 0x03000000U,
 145      [PINMUX_CTRL4]    = 0x00000000U,
 146      [PINMUX_CTRL5]    = 0x0000A000U,
 147      [WDT_RST_CTRL]    = 0x023FFFF3U,
 148      [PINMUX_CTRL8]    = 0xFFFF0000U,
 149      [PINMUX_CTRL9]    = 0x000FFFFFU,
 150      [FREE_CNTR4]      = 0x000000FFU,
 151      [FREE_CNTR4_EXT]  = 0x000000FFU,
 152      [CPU2_BASE_SEG1]  = 0x80000000U,
 153      [CPU2_BASE_SEG4]  = 0x1E600000U,
 154      [CPU2_BASE_SEG5]  = 0xC0000000U,
 155      [UART_HPLL_CLK]   = 0x00001903U,
 156      [PCIE_CTRL]       = 0x0000007BU,
 157      [BMC_DEV_ID]      = 0x00002402U
 158 };
 159
 160 static uint32_t aspeed_scu_get_random(void)
 161 {
 162     uint32_t num;
 163     qemu_guest_getrandom_nofail(&num, sizeof(num));
 164     return num;
 165 }
 166
 167 static void aspeed_scu_set_apb_freq(AspeedSCUState *s)
 168 {
 169     uint32_t apb_divider;
 170
 171     switch (s->silicon_rev) {
 172     case AST2400_A0_SILICON_REV:
 173     case AST2400_A1_SILICON_REV:
 174         apb_divider = 2;
 175         break;
 176     case AST2500_A0_SILICON_REV:
 177     case AST2500_A1_SILICON_REV:
 178         apb_divider = 4;
 179         break;
 180     default:
 181         g_assert_not_reached();
 182     }
 183
 184     s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1)
 185         / apb_divider;
 186 }
 187
 188 static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size)
 189 {
 190     AspeedSCUState *s = ASPEED_SCU(opaque);
 191     int reg = TO_REG(offset);
 192
 193     if (reg >= ARRAY_SIZE(s->regs)) {
 194         qemu_log_mask(LOG_GUEST_ERROR,
 195                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
 196                       __func__, offset);
 197         return 0;
 198     }
 199
 200     switch (reg) {
 201     case RNG_DATA:
 202         /* On hardware, RNG_DATA works regardless of
 203          * the state of the enable bit in RNG_CTRL
 204          */
 205         s->regs[RNG_DATA] = aspeed_scu_get_random();
 206         break;
 207     case WAKEUP_EN:
 208         qemu_log_mask(LOG_GUEST_ERROR,
 209                       "%s: Read of write-only offset 0x%" HWADDR_PRIx "\n",
 210                       __func__, offset);
 211         break;
 212     }
 213
 214     return s->regs[reg];
 215 }
 216
 217 static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data,
 218                              unsigned size)
 219 {
 220     AspeedSCUState *s = ASPEED_SCU(opaque);
 221     int reg = TO_REG(offset);
 222
 223     if (reg >= ARRAY_SIZE(s->regs)) {
 224         qemu_log_mask(LOG_GUEST_ERROR,
 225                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 226                       __func__, offset);
 227         return;
 228     }
 229
 230     if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 &&
 231             !s->regs[PROT_KEY]) {
 232         qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__);
 233         return;
 234     }
 235
 236     trace_aspeed_scu_write(offset, size, data);
 237
 238     switch (reg) {
 239     case PROT_KEY:
 240         s->regs[reg] = (data == ASPEED_SCU_PROT_KEY) ? 1 : 0;
 241         return;
 242     case CLK_SEL:
 243         s->regs[reg] = data;
 244         aspeed_scu_set_apb_freq(s);
 245         break;
 246     case HW_STRAP1:
 247         if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
 248             s->regs[HW_STRAP1] |= data;
 249             return;
 250         }
 251         /* Jump to assignment below */
 252         break;
 253     case SILICON_REV:
 254         if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) {
 255             s->regs[HW_STRAP1] &= ~data;
 256         } else {
 257             qemu_log_mask(LOG_GUEST_ERROR,
 258                           "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
 259                           __func__, offset);
 260         }
 261         /* Avoid assignment below, we've handled everything */
 262         return;
 263     case FREQ_CNTR_EVAL:
 264     case VGA_SCRATCH1 ... VGA_SCRATCH8:
 265     case RNG_DATA:
 266     case FREE_CNTR4:
 267     case FREE_CNTR4_EXT:
 268         qemu_log_mask(LOG_GUEST_ERROR,
 269                       "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n",
 270                       __func__, offset);
 271         return;
 272     }
 273
 274     s->regs[reg] = data;
 275 }
 276
 277 static const MemoryRegionOps aspeed_scu_ops = {
 278     .read = aspeed_scu_read,
 279     .write = aspeed_scu_write,
 280     .endianness = DEVICE_LITTLE_ENDIAN,
 281     .valid.min_access_size = 4,
 282     .valid.max_access_size = 4,
 283     .valid.unaligned = false,
 284 };
 285
 286 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s)
 287 {
 288     if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) {
 289         return 25000000;
 290     } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) {
 291         return 48000000;
 292     } else {
 293         return 24000000;
 294     }
 295 }
 296
 297 /*
 298  * Strapped frequencies for the AST2400 in MHz. They depend on the
 299  * clkin frequency.
 300  */
 301 static const uint32_t hpll_ast2400_freqs[][4] = {
 302     { 384, 360, 336, 408 }, /* 24MHz or 48MHz */
 303     { 400, 375, 350, 425 }, /* 25MHz */
 304 };
 305
 306 static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s)
 307 {
 308     uint32_t hpll_reg = s->regs[HPLL_PARAM];
 309     uint8_t freq_select;
 310     bool clk_25m_in;
 311
 312     if (hpll_reg & SCU_AST2400_H_PLL_OFF) {
 313         return 0;
 314     }
 315
 316     if (hpll_reg & SCU_AST2400_H_PLL_PROGRAMMED) {
 317         uint32_t multiplier = 1;
 318
 319         if (!(hpll_reg & SCU_AST2400_H_PLL_BYPASS_EN)) {
 320             uint32_t n  = (hpll_reg >> 5) & 0x3f;
 321             uint32_t od = (hpll_reg >> 4) & 0x1;
 322             uint32_t d  = hpll_reg & 0xf;
 323
 324             multiplier = (2 - od) * ((n + 2) / (d + 1));
 325         }
 326
 327         return s->clkin * multiplier;
 328     }
 329
 330     /* HW strapping */
 331     clk_25m_in = !!(s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN);
 332     freq_select = SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(s->hw_strap1);
 333
 334     return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000;
 335 }
 336
 337 static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s)
 338 {
 339     uint32_t hpll_reg   = s->regs[HPLL_PARAM];
 340     uint32_t multiplier = 1;
 341
 342     if (hpll_reg & SCU_H_PLL_OFF) {
 343         return 0;
 344     }
 345
 346     if (!(hpll_reg & SCU_H_PLL_BYPASS_EN)) {
 347         uint32_t p = (hpll_reg >> 13) & 0x3f;
 348         uint32_t m = (hpll_reg >> 5) & 0xff;
 349         uint32_t n = hpll_reg & 0x1f;
 350
 351         multiplier = ((m + 1) / (n + 1)) / (p + 1);
 352     }
 353
 354     return s->clkin * multiplier;
 355 }
 356
 357 static void aspeed_scu_reset(DeviceState *dev)
 358 {
 359     AspeedSCUState *s = ASPEED_SCU(dev);
 360     const uint32_t *reset;
 361     uint32_t (*calc_hpll)(AspeedSCUState *s);
 362
 363     switch (s->silicon_rev) {
 364     case AST2400_A0_SILICON_REV:
 365     case AST2400_A1_SILICON_REV:
 366         reset = ast2400_a0_resets;
 367         calc_hpll = aspeed_scu_calc_hpll_ast2400;
 368         break;
 369     case AST2500_A0_SILICON_REV:
 370     case AST2500_A1_SILICON_REV:
 371         reset = ast2500_a1_resets;
 372         calc_hpll = aspeed_scu_calc_hpll_ast2500;
 373         break;
 374     default:
 375         g_assert_not_reached();
 376     }
 377
 378     memcpy(s->regs, reset, sizeof(s->regs));
 379     s->regs[SILICON_REV] = s->silicon_rev;
 380     s->regs[HW_STRAP1] = s->hw_strap1;
 381     s->regs[HW_STRAP2] = s->hw_strap2;
 382     s->regs[PROT_KEY] = s->hw_prot_key;
 383
 384     /*
 385      * All registers are set. Now compute the frequencies of the main clocks
 386      */
 387     s->clkin = aspeed_scu_get_clkin(s);
 388     s->hpll = calc_hpll(s);
 389     aspeed_scu_set_apb_freq(s);
 390 }
 391
 392 static uint32_t aspeed_silicon_revs[] = {
 393     AST2400_A0_SILICON_REV,
 394     AST2400_A1_SILICON_REV,
 395     AST2500_A0_SILICON_REV,
 396     AST2500_A1_SILICON_REV,
 397 };
 398
 399 bool is_supported_silicon_rev(uint32_t silicon_rev)
 400 {
 401     int i;
 402
 403     for (i = 0; i < ARRAY_SIZE(aspeed_silicon_revs); i++) {
 404         if (silicon_rev == aspeed_silicon_revs[i]) {
 405             return true;
 406         }
 407     }
 408
 409     return false;
 410 }
 411
 412 static void aspeed_scu_realize(DeviceState *dev, Error **errp)
 413 {
 414     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 415     AspeedSCUState *s = ASPEED_SCU(dev);
 416
 417     if (!is_supported_silicon_rev(s->silicon_rev)) {
 418         error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
 419                 s->silicon_rev);
 420         return;
 421     }
 422
 423     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_scu_ops, s,
 424                           TYPE_ASPEED_SCU, SCU_IO_REGION_SIZE);
 425
 426     sysbus_init_mmio(sbd, &s->iomem);
 427 }
 428
 429 static const VMStateDescription vmstate_aspeed_scu = {
 430     .name = "aspeed.scu",
 431     .version_id = 1,
 432     .minimum_version_id = 1,
 433     .fields = (VMStateField[]) {
 434         VMSTATE_UINT32_ARRAY(regs, AspeedSCUState, ASPEED_SCU_NR_REGS),
 435         VMSTATE_END_OF_LIST()
 436     }
 437 };
 438
 439 static Property aspeed_scu_properties[] = {
 440     DEFINE_PROP_UINT32("silicon-rev", AspeedSCUState, silicon_rev, 0),
 441     DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0),
 442     DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0),
 443     DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0),
 444     DEFINE_PROP_END_OF_LIST(),
 445 };
 446
 447 static void aspeed_scu_class_init(ObjectClass *klass, void *data)
 448 {
 449     DeviceClass *dc = DEVICE_CLASS(klass);
 450     dc->realize = aspeed_scu_realize;
 451     dc->reset = aspeed_scu_reset;
 452     dc->desc = "ASPEED System Control Unit";
 453     dc->vmsd = &vmstate_aspeed_scu;
 454     dc->props = aspeed_scu_properties;
 455 }
 456
 457 static const TypeInfo aspeed_scu_info = {
 458     .name = TYPE_ASPEED_SCU,
 459     .parent = TYPE_SYS_BUS_DEVICE,
 460     .instance_size = sizeof(AspeedSCUState),
 461     .class_init = aspeed_scu_class_init,
 462 };
 463
 464 static void aspeed_scu_register_types(void)
 465 {
 466     type_register_static(&aspeed_scu_info);
 467 }
 468
 469 type_init(aspeed_scu_register_types);