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monitor/qmp: Update comment for commit 4eaca8de268
[qemu/armbru.git] / hw / net / dp8393x.c
bloba5678e11faf9e20e972df205b2bff0e7c2ac89d4
1 /*
2 * QEMU NS SONIC DP8393x netcard
3 *
4 * Copyright (c) 2008-2009 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "net/net.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include <zlib.h>
30
31 //#define DEBUG_SONIC
32
33 #define SONIC_PROM_SIZE 0x1000
34
35 #ifdef DEBUG_SONIC
36 #define DPRINTF(fmt, ...) \
37 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
38 static const char* reg_names[] = {
39 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
40 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
41 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
42 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
43 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
44 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
45 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
46 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
47 #else
48 #define DPRINTF(fmt, ...) do {} while (0)
49 #endif
50
51 #define SONIC_ERROR(fmt, ...) \
52 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
53
54 #define SONIC_CR 0x00
55 #define SONIC_DCR 0x01
56 #define SONIC_RCR 0x02
57 #define SONIC_TCR 0x03
58 #define SONIC_IMR 0x04
59 #define SONIC_ISR 0x05
60 #define SONIC_UTDA 0x06
61 #define SONIC_CTDA 0x07
62 #define SONIC_TPS 0x08
63 #define SONIC_TFC 0x09
64 #define SONIC_TSA0 0x0a
65 #define SONIC_TSA1 0x0b
66 #define SONIC_TFS 0x0c
67 #define SONIC_URDA 0x0d
68 #define SONIC_CRDA 0x0e
69 #define SONIC_CRBA0 0x0f
70 #define SONIC_CRBA1 0x10
71 #define SONIC_RBWC0 0x11
72 #define SONIC_RBWC1 0x12
73 #define SONIC_EOBC 0x13
74 #define SONIC_URRA 0x14
75 #define SONIC_RSA 0x15
76 #define SONIC_REA 0x16
77 #define SONIC_RRP 0x17
78 #define SONIC_RWP 0x18
79 #define SONIC_TRBA0 0x19
80 #define SONIC_TRBA1 0x1a
81 #define SONIC_LLFA 0x1f
82 #define SONIC_TTDA 0x20
83 #define SONIC_CEP 0x21
84 #define SONIC_CAP2 0x22
85 #define SONIC_CAP1 0x23
86 #define SONIC_CAP0 0x24
87 #define SONIC_CE 0x25
88 #define SONIC_CDP 0x26
89 #define SONIC_CDC 0x27
90 #define SONIC_SR 0x28
91 #define SONIC_WT0 0x29
92 #define SONIC_WT1 0x2a
93 #define SONIC_RSC 0x2b
94 #define SONIC_CRCT 0x2c
95 #define SONIC_FAET 0x2d
96 #define SONIC_MPT 0x2e
97 #define SONIC_MDT 0x2f
98 #define SONIC_DCR2 0x3f
99
100 #define SONIC_CR_HTX 0x0001
101 #define SONIC_CR_TXP 0x0002
102 #define SONIC_CR_RXDIS 0x0004
103 #define SONIC_CR_RXEN 0x0008
104 #define SONIC_CR_STP 0x0010
105 #define SONIC_CR_ST 0x0020
106 #define SONIC_CR_RST 0x0080
107 #define SONIC_CR_RRRA 0x0100
108 #define SONIC_CR_LCAM 0x0200
109 #define SONIC_CR_MASK 0x03bf
110
111 #define SONIC_DCR_DW 0x0020
112 #define SONIC_DCR_LBR 0x2000
113 #define SONIC_DCR_EXBUS 0x8000
114
115 #define SONIC_RCR_PRX 0x0001
116 #define SONIC_RCR_LBK 0x0002
117 #define SONIC_RCR_FAER 0x0004
118 #define SONIC_RCR_CRCR 0x0008
119 #define SONIC_RCR_CRS 0x0020
120 #define SONIC_RCR_LPKT 0x0040
121 #define SONIC_RCR_BC 0x0080
122 #define SONIC_RCR_MC 0x0100
123 #define SONIC_RCR_LB0 0x0200
124 #define SONIC_RCR_LB1 0x0400
125 #define SONIC_RCR_AMC 0x0800
126 #define SONIC_RCR_PRO 0x1000
127 #define SONIC_RCR_BRD 0x2000
128 #define SONIC_RCR_RNT 0x4000
129
130 #define SONIC_TCR_PTX 0x0001
131 #define SONIC_TCR_BCM 0x0002
132 #define SONIC_TCR_FU 0x0004
133 #define SONIC_TCR_EXC 0x0040
134 #define SONIC_TCR_CRSL 0x0080
135 #define SONIC_TCR_NCRS 0x0100
136 #define SONIC_TCR_EXD 0x0400
137 #define SONIC_TCR_CRCI 0x2000
138 #define SONIC_TCR_PINT 0x8000
139
140 #define SONIC_ISR_RBE 0x0020
141 #define SONIC_ISR_RDE 0x0040
142 #define SONIC_ISR_TC 0x0080
143 #define SONIC_ISR_TXDN 0x0200
144 #define SONIC_ISR_PKTRX 0x0400
145 #define SONIC_ISR_PINT 0x0800
146 #define SONIC_ISR_LCD 0x1000
147
148 #define TYPE_DP8393X "dp8393x"
149 #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X)
150
151 typedef struct dp8393xState {
152 SysBusDevice parent_obj;
153
154 /* Hardware */
155 uint8_t it_shift;
156 qemu_irq irq;
157 #ifdef DEBUG_SONIC
158 int irq_level;
159 #endif
160 QEMUTimer *watchdog;
161 int64_t wt_last_update;
162 NICConf conf;
163 NICState *nic;
164 MemoryRegion mmio;
165 MemoryRegion prom;
166
167 /* Registers */
168 uint8_t cam[16][6];
169 uint16_t regs[0x40];
170
171 /* Temporaries */
172 uint8_t tx_buffer[0x10000];
173 int loopback_packet;
174
175 /* Memory access */
176 void *dma_mr;
177 AddressSpace as;
178 } dp8393xState;
179
180 /* Accessor functions for values which are formed by
181 * concatenating two 16 bit device registers. By putting these
182 * in their own functions with a uint32_t return type we avoid the
183 * pitfall of implicit sign extension where ((x << 16) | y) is a
184 * signed 32 bit integer that might get sign-extended to a 64 bit integer.
185 */
186 static uint32_t dp8393x_cdp(dp8393xState *s)
187 {
188 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
189 }
190
191 static uint32_t dp8393x_crba(dp8393xState *s)
192 {
193 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
194 }
195
196 static uint32_t dp8393x_crda(dp8393xState *s)
197 {
198 return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA];
199 }
200
201 static uint32_t dp8393x_rbwc(dp8393xState *s)
202 {
203 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
204 }
205
206 static uint32_t dp8393x_rrp(dp8393xState *s)
207 {
208 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
209 }
210
211 static uint32_t dp8393x_tsa(dp8393xState *s)
212 {
213 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
214 }
215
216 static uint32_t dp8393x_ttda(dp8393xState *s)
217 {
218 return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA];
219 }
220
221 static uint32_t dp8393x_wt(dp8393xState *s)
222 {
223 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
224 }
225
226 static void dp8393x_update_irq(dp8393xState *s)
227 {
228 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
229
230 #ifdef DEBUG_SONIC
231 if (level != s->irq_level) {
232 s->irq_level = level;
233 if (level) {
234 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
235 } else {
236 DPRINTF("lower irq\n");
237 }
238 }
239 #endif
240
241 qemu_set_irq(s->irq, level);
242 }
243
244 static void dp8393x_do_load_cam(dp8393xState *s)
245 {
246 uint16_t data[8];
247 int width, size;
248 uint16_t index = 0;
249
250 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
251 size = sizeof(uint16_t) * 4 * width;
252
253 while (s->regs[SONIC_CDC] & 0x1f) {
254 /* Fill current entry */
255 address_space_rw(&s->as, dp8393x_cdp(s),
256 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
257 s->cam[index][0] = data[1 * width] & 0xff;
258 s->cam[index][1] = data[1 * width] >> 8;
259 s->cam[index][2] = data[2 * width] & 0xff;
260 s->cam[index][3] = data[2 * width] >> 8;
261 s->cam[index][4] = data[3 * width] & 0xff;
262 s->cam[index][5] = data[3 * width] >> 8;
263 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
264 s->cam[index][0], s->cam[index][1], s->cam[index][2],
265 s->cam[index][3], s->cam[index][4], s->cam[index][5]);
266 /* Move to next entry */
267 s->regs[SONIC_CDC]--;
268 s->regs[SONIC_CDP] += size;
269 index++;
270 }
271
272 /* Read CAM enable */
273 address_space_rw(&s->as, dp8393x_cdp(s),
274 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
275 s->regs[SONIC_CE] = data[0 * width];
276 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
277
278 /* Done */
279 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
280 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
281 dp8393x_update_irq(s);
282 }
283
284 static void dp8393x_do_read_rra(dp8393xState *s)
285 {
286 uint16_t data[8];
287 int width, size;
288
289 /* Read memory */
290 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
291 size = sizeof(uint16_t) * 4 * width;
292 address_space_rw(&s->as, dp8393x_rrp(s),
293 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
294
295 /* Update SONIC registers */
296 s->regs[SONIC_CRBA0] = data[0 * width];
297 s->regs[SONIC_CRBA1] = data[1 * width];
298 s->regs[SONIC_RBWC0] = data[2 * width];
299 s->regs[SONIC_RBWC1] = data[3 * width];
300 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
301 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
302 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
303
304 /* Go to next entry */
305 s->regs[SONIC_RRP] += size;
306
307 /* Handle wrap */
308 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
309 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
310 }
311
312 /* Check resource exhaustion */
313 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
314 {
315 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
316 dp8393x_update_irq(s);
317 }
318
319 /* Done */
320 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
321 }
322
323 static void dp8393x_do_software_reset(dp8393xState *s)
324 {
325 timer_del(s->watchdog);
326
327 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
328 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
329 }
330
331 static void dp8393x_set_next_tick(dp8393xState *s)
332 {
333 uint32_t ticks;
334 int64_t delay;
335
336 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
337 timer_del(s->watchdog);
338 return;
339 }
340
341 ticks = dp8393x_wt(s);
342 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
343 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
344 timer_mod(s->watchdog, s->wt_last_update + delay);
345 }
346
347 static void dp8393x_update_wt_regs(dp8393xState *s)
348 {
349 int64_t elapsed;
350 uint32_t val;
351
352 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
353 timer_del(s->watchdog);
354 return;
355 }
356
357 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
358 val = dp8393x_wt(s);
359 val -= elapsed / 5000000;
360 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
361 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
362 dp8393x_set_next_tick(s);
363
364 }
365
366 static void dp8393x_do_start_timer(dp8393xState *s)
367 {
368 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
369 dp8393x_set_next_tick(s);
370 }
371
372 static void dp8393x_do_stop_timer(dp8393xState *s)
373 {
374 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
375 dp8393x_update_wt_regs(s);
376 }
377
378 static int dp8393x_can_receive(NetClientState *nc);
379
380 static void dp8393x_do_receiver_enable(dp8393xState *s)
381 {
382 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
383 if (dp8393x_can_receive(s->nic->ncs)) {
384 qemu_flush_queued_packets(qemu_get_queue(s->nic));
385 }
386 }
387
388 static void dp8393x_do_receiver_disable(dp8393xState *s)
389 {
390 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
391 }
392
393 static void dp8393x_do_transmit_packets(dp8393xState *s)
394 {
395 NetClientState *nc = qemu_get_queue(s->nic);
396 uint16_t data[12];
397 int width, size;
398 int tx_len, len;
399 uint16_t i;
400
401 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
402
403 while (1) {
404 /* Read memory */
405 size = sizeof(uint16_t) * 6 * width;
406 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
407 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
408 address_space_rw(&s->as,
409 dp8393x_ttda(s) + sizeof(uint16_t) * width,
410 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
411 tx_len = 0;
412
413 /* Update registers */
414 s->regs[SONIC_TCR] = data[0 * width] & 0xf000;
415 s->regs[SONIC_TPS] = data[1 * width];
416 s->regs[SONIC_TFC] = data[2 * width];
417 s->regs[SONIC_TSA0] = data[3 * width];
418 s->regs[SONIC_TSA1] = data[4 * width];
419 s->regs[SONIC_TFS] = data[5 * width];
420
421 /* Handle programmable interrupt */
422 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
423 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
424 } else {
425 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
426 }
427
428 for (i = 0; i < s->regs[SONIC_TFC]; ) {
429 /* Append fragment */
430 len = s->regs[SONIC_TFS];
431 if (tx_len + len > sizeof(s->tx_buffer)) {
432 len = sizeof(s->tx_buffer) - tx_len;
433 }
434 address_space_rw(&s->as, dp8393x_tsa(s),
435 MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0);
436 tx_len += len;
437
438 i++;
439 if (i != s->regs[SONIC_TFC]) {
440 /* Read next fragment details */
441 size = sizeof(uint16_t) * 3 * width;
442 address_space_rw(&s->as,
443 dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width,
444 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
445 s->regs[SONIC_TSA0] = data[0 * width];
446 s->regs[SONIC_TSA1] = data[1 * width];
447 s->regs[SONIC_TFS] = data[2 * width];
448 }
449 }
450
451 /* Handle Ethernet checksum */
452 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
453 /* Don't append FCS there, to look like slirp packets
454 * which don't have one */
455 } else {
456 /* Remove existing FCS */
457 tx_len -= 4;
458 }
459
460 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
461 /* Loopback */
462 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
463 if (nc->info->can_receive(nc)) {
464 s->loopback_packet = 1;
465 nc->info->receive(nc, s->tx_buffer, tx_len);
466 }
467 } else {
468 /* Transmit packet */
469 qemu_send_packet(nc, s->tx_buffer, tx_len);
470 }
471 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
472
473 /* Write status */
474 data[0 * width] = s->regs[SONIC_TCR] & 0x0fff; /* status */
475 size = sizeof(uint16_t) * width;
476 address_space_rw(&s->as,
477 dp8393x_ttda(s),
478 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
479
480 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
481 /* Read footer of packet */
482 size = sizeof(uint16_t) * width;
483 address_space_rw(&s->as,
484 dp8393x_ttda(s) +
485 sizeof(uint16_t) *
486 (4 + 3 * s->regs[SONIC_TFC]) * width,
487 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
488 s->regs[SONIC_CTDA] = data[0 * width] & ~0x1;
489 if (data[0 * width] & 0x1) {
490 /* EOL detected */
491 break;
492 }
493 }
494 }
495
496 /* Done */
497 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
498 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
499 dp8393x_update_irq(s);
500 }
501
502 static void dp8393x_do_halt_transmission(dp8393xState *s)
503 {
504 /* Nothing to do */
505 }
506
507 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
508 {
509 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
510 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
511 return;
512 }
513
514 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
515
516 if (command & SONIC_CR_HTX)
517 dp8393x_do_halt_transmission(s);
518 if (command & SONIC_CR_TXP)
519 dp8393x_do_transmit_packets(s);
520 if (command & SONIC_CR_RXDIS)
521 dp8393x_do_receiver_disable(s);
522 if (command & SONIC_CR_RXEN)
523 dp8393x_do_receiver_enable(s);
524 if (command & SONIC_CR_STP)
525 dp8393x_do_stop_timer(s);
526 if (command & SONIC_CR_ST)
527 dp8393x_do_start_timer(s);
528 if (command & SONIC_CR_RST)
529 dp8393x_do_software_reset(s);
530 if (command & SONIC_CR_RRRA)
531 dp8393x_do_read_rra(s);
532 if (command & SONIC_CR_LCAM)
533 dp8393x_do_load_cam(s);
534 }
535
536 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
537 {
538 dp8393xState *s = opaque;
539 int reg = addr >> s->it_shift;
540 uint16_t val = 0;
541
542 switch (reg) {
543 /* Update data before reading it */
544 case SONIC_WT0:
545 case SONIC_WT1:
546 dp8393x_update_wt_regs(s);
547 val = s->regs[reg];
548 break;
549 /* Accept read to some registers only when in reset mode */
550 case SONIC_CAP2:
551 case SONIC_CAP1:
552 case SONIC_CAP0:
553 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
554 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
555 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
556 }
557 break;
558 /* All other registers have no special contrainst */
559 default:
560 val = s->regs[reg];
561 }
562
563 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
564
565 return val;
566 }
567
568 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
569 unsigned int size)
570 {
571 dp8393xState *s = opaque;
572 int reg = addr >> s->it_shift;
573
574 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]);
575
576 switch (reg) {
577 /* Command register */
578 case SONIC_CR:
579 dp8393x_do_command(s, data);
580 break;
581 /* Prevent write to read-only registers */
582 case SONIC_CAP2:
583 case SONIC_CAP1:
584 case SONIC_CAP0:
585 case SONIC_SR:
586 case SONIC_MDT:
587 DPRINTF("writing to reg %d invalid\n", reg);
588 break;
589 /* Accept write to some registers only when in reset mode */
590 case SONIC_DCR:
591 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
592 s->regs[reg] = data & 0xbfff;
593 } else {
594 DPRINTF("writing to DCR invalid\n");
595 }
596 break;
597 case SONIC_DCR2:
598 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
599 s->regs[reg] = data & 0xf017;
600 } else {
601 DPRINTF("writing to DCR2 invalid\n");
602 }
603 break;
604 /* 12 lower bytes are Read Only */
605 case SONIC_TCR:
606 s->regs[reg] = data & 0xf000;
607 break;
608 /* 9 lower bytes are Read Only */
609 case SONIC_RCR:
610 s->regs[reg] = data & 0xffe0;
611 break;
612 /* Ignore most significant bit */
613 case SONIC_IMR:
614 s->regs[reg] = data & 0x7fff;
615 dp8393x_update_irq(s);
616 break;
617 /* Clear bits by writing 1 to them */
618 case SONIC_ISR:
619 data &= s->regs[reg];
620 s->regs[reg] &= ~data;
621 if (data & SONIC_ISR_RBE) {
622 dp8393x_do_read_rra(s);
623 }
624 dp8393x_update_irq(s);
625 if (dp8393x_can_receive(s->nic->ncs)) {
626 qemu_flush_queued_packets(qemu_get_queue(s->nic));
627 }
628 break;
629 /* Ignore least significant bit */
630 case SONIC_RSA:
631 case SONIC_REA:
632 case SONIC_RRP:
633 case SONIC_RWP:
634 s->regs[reg] = data & 0xfffe;
635 break;
636 /* Invert written value for some registers */
637 case SONIC_CRCT:
638 case SONIC_FAET:
639 case SONIC_MPT:
640 s->regs[reg] = data ^ 0xffff;
641 break;
642 /* All other registers have no special contrainst */
643 default:
644 s->regs[reg] = data;
645 }
646
647 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
648 dp8393x_set_next_tick(s);
649 }
650 }
651
652 static const MemoryRegionOps dp8393x_ops = {
653 .read = dp8393x_read,
654 .write = dp8393x_write,
655 .impl.min_access_size = 2,
656 .impl.max_access_size = 2,
657 .endianness = DEVICE_NATIVE_ENDIAN,
658 };
659
660 static void dp8393x_watchdog(void *opaque)
661 {
662 dp8393xState *s = opaque;
663
664 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
665 return;
666 }
667
668 s->regs[SONIC_WT1] = 0xffff;
669 s->regs[SONIC_WT0] = 0xffff;
670 dp8393x_set_next_tick(s);
671
672 /* Signal underflow */
673 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
674 dp8393x_update_irq(s);
675 }
676
677 static int dp8393x_can_receive(NetClientState *nc)
678 {
679 dp8393xState *s = qemu_get_nic_opaque(nc);
680
681 if (!(s->regs[SONIC_CR] & SONIC_CR_RXEN))
682 return 0;
683 if (s->regs[SONIC_ISR] & SONIC_ISR_RBE)
684 return 0;
685 return 1;
686 }
687
688 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
689 int size)
690 {
691 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
692 int i;
693
694 /* Check promiscuous mode */
695 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
696 return 0;
697 }
698
699 /* Check multicast packets */
700 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
701 return SONIC_RCR_MC;
702 }
703
704 /* Check broadcast */
705 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
706 return SONIC_RCR_BC;
707 }
708
709 /* Check CAM */
710 for (i = 0; i < 16; i++) {
711 if (s->regs[SONIC_CE] & (1 << i)) {
712 /* Entry enabled */
713 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
714 return 0;
715 }
716 }
717 }
718
719 return -1;
720 }
721
722 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
723 size_t size)
724 {
725 dp8393xState *s = qemu_get_nic_opaque(nc);
726 uint16_t data[10];
727 int packet_type;
728 uint32_t available, address;
729 int width, rx_len = size;
730 uint32_t checksum;
731
732 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
733
734 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
735 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
736
737 packet_type = dp8393x_receive_filter(s, buf, size);
738 if (packet_type < 0) {
739 DPRINTF("packet not for netcard\n");
740 return -1;
741 }
742
743 /* XXX: Check byte ordering */
744
745 /* Check for EOL */
746 if (s->regs[SONIC_LLFA] & 0x1) {
747 /* Are we still in resource exhaustion? */
748 size = sizeof(uint16_t) * 1 * width;
749 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
750 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
751 (uint8_t *)data, size, 0);
752 if (data[0 * width] & 0x1) {
753 /* Still EOL ; stop reception */
754 return -1;
755 } else {
756 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
757 }
758 }
759
760 /* Save current position */
761 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
762 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
763
764 /* Calculate the ethernet checksum */
765 checksum = cpu_to_le32(crc32(0, buf, rx_len));
766
767 /* Put packet into RBA */
768 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
769 address = dp8393x_crba(s);
770 address_space_rw(&s->as, address,
771 MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1);
772 address += rx_len;
773 address_space_rw(&s->as, address,
774 MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1);
775 rx_len += 4;
776 s->regs[SONIC_CRBA1] = address >> 16;
777 s->regs[SONIC_CRBA0] = address & 0xffff;
778 available = dp8393x_rbwc(s);
779 available -= rx_len / 2;
780 s->regs[SONIC_RBWC1] = available >> 16;
781 s->regs[SONIC_RBWC0] = available & 0xffff;
782
783 /* Update status */
784 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
785 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
786 }
787 s->regs[SONIC_RCR] |= packet_type;
788 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
789 if (s->loopback_packet) {
790 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
791 s->loopback_packet = 0;
792 }
793
794 /* Write status to memory */
795 DPRINTF("Write status at %08x\n", dp8393x_crda(s));
796 data[0 * width] = s->regs[SONIC_RCR]; /* status */
797 data[1 * width] = rx_len; /* byte count */
798 data[2 * width] = s->regs[SONIC_TRBA0]; /* pkt_ptr0 */
799 data[3 * width] = s->regs[SONIC_TRBA1]; /* pkt_ptr1 */
800 data[4 * width] = s->regs[SONIC_RSC]; /* seq_no */
801 size = sizeof(uint16_t) * 5 * width;
802 address_space_rw(&s->as, dp8393x_crda(s),
803 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 1);
804
805 /* Move to next descriptor */
806 size = sizeof(uint16_t) * width;
807 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
808 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, size, 0);
809 s->regs[SONIC_LLFA] = data[0 * width];
810 if (s->regs[SONIC_LLFA] & 0x1) {
811 /* EOL detected */
812 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
813 } else {
814 data[0 * width] = 0; /* in_use */
815 address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 6 * width,
816 MEMTXATTRS_UNSPECIFIED, (uint8_t *)data, sizeof(uint16_t), 1);
817 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
818 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
819 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff);
820
821 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
822 /* Read next RRA */
823 dp8393x_do_read_rra(s);
824 }
825 }
826
827 /* Done */
828 dp8393x_update_irq(s);
829
830 return size;
831 }
832
833 static void dp8393x_reset(DeviceState *dev)
834 {
835 dp8393xState *s = DP8393X(dev);
836 timer_del(s->watchdog);
837
838 memset(s->regs, 0, sizeof(s->regs));
839 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
840 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
841 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
842 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
843 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
844 s->regs[SONIC_IMR] = 0;
845 s->regs[SONIC_ISR] = 0;
846 s->regs[SONIC_DCR2] = 0;
847 s->regs[SONIC_EOBC] = 0x02F8;
848 s->regs[SONIC_RSC] = 0;
849 s->regs[SONIC_CE] = 0;
850 s->regs[SONIC_RSC] = 0;
851
852 /* Network cable is connected */
853 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
854
855 dp8393x_update_irq(s);
856 }
857
858 static NetClientInfo net_dp83932_info = {
859 .type = NET_CLIENT_DRIVER_NIC,
860 .size = sizeof(NICState),
861 .can_receive = dp8393x_can_receive,
862 .receive = dp8393x_receive,
863 };
864
865 static void dp8393x_instance_init(Object *obj)
866 {
867 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
868 dp8393xState *s = DP8393X(obj);
869
870 sysbus_init_mmio(sbd, &s->mmio);
871 sysbus_init_mmio(sbd, &s->prom);
872 sysbus_init_irq(sbd, &s->irq);
873 }
874
875 static void dp8393x_realize(DeviceState *dev, Error **errp)
876 {
877 dp8393xState *s = DP8393X(dev);
878 int i, checksum;
879 uint8_t *prom;
880 Error *local_err = NULL;
881
882 address_space_init(&s->as, s->dma_mr, "dp8393x");
883 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
884 "dp8393x-regs", 0x40 << s->it_shift);
885
886 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
887 object_get_typename(OBJECT(dev)), dev->id, s);
888 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
889
890 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
891 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
892
893 memory_region_init_ram(&s->prom, OBJECT(dev),
894 "dp8393x-prom", SONIC_PROM_SIZE, &local_err);
895 if (local_err) {
896 error_propagate(errp, local_err);
897 return;
898 }
899 memory_region_set_readonly(&s->prom, true);
900 prom = memory_region_get_ram_ptr(&s->prom);
901 checksum = 0;
902 for (i = 0; i < 6; i++) {
903 prom[i] = s->conf.macaddr.a[i];
904 checksum += prom[i];
905 if (checksum > 0xff) {
906 checksum = (checksum + 1) & 0xff;
907 }
908 }
909 prom[7] = 0xff - checksum;
910 }
911
912 static const VMStateDescription vmstate_dp8393x = {
913 .name = "dp8393x",
914 .version_id = 0,
915 .minimum_version_id = 0,
916 .fields = (VMStateField []) {
917 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
918 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
919 VMSTATE_END_OF_LIST()
920 }
921 };
922
923 static Property dp8393x_properties[] = {
924 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
925 DEFINE_PROP_PTR("dma_mr", dp8393xState, dma_mr),
926 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
927 DEFINE_PROP_END_OF_LIST(),
928 };
929
930 static void dp8393x_class_init(ObjectClass *klass, void *data)
931 {
932 DeviceClass *dc = DEVICE_CLASS(klass);
933
934 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
935 dc->realize = dp8393x_realize;
936 dc->reset = dp8393x_reset;
937 dc->vmsd = &vmstate_dp8393x;
938 dc->props = dp8393x_properties;
939 /* Reason: dma_mr property can't be set */
940 dc->user_creatable = false;
941 }
942
943 static const TypeInfo dp8393x_info = {
944 .name = TYPE_DP8393X,
945 .parent = TYPE_SYS_BUS_DEVICE,
946 .instance_size = sizeof(dp8393xState),
947 .instance_init = dp8393x_instance_init,
948 .class_init = dp8393x_class_init,
949 };
950
951 static void dp8393x_register_types(void)
952 {
953 type_register_static(&dp8393x_info);
954 }
955
956 type_init(dp8393x_register_types)
armbru's QEMU hackery