2 * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
5 * Copyright (c) 2013 Hervé Poussineau
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
27 #include "hw/isa/isa.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/timer/m48t59.h"
30 #include "m48t59-internal.h"
31 #include "qemu/module.h"
33 #define TYPE_M48TXX_ISA "isa-m48txx"
34 #define M48TXX_ISA_GET_CLASS(obj) \
35 OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
36 #define M48TXX_ISA_CLASS(klass) \
37 OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
38 #define M48TXX_ISA(obj) \
39 OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
41 typedef struct M48txxISAState
{
48 typedef struct M48txxISADeviceClass
{
49 ISADeviceClass parent_class
;
51 } M48txxISADeviceClass
;
53 static M48txxInfo m48txx_isa_info
[] = {
55 .bus_name
= "isa-m48t59",
61 Nvram
*m48t59_init_isa(ISABus
*bus
, uint32_t io_base
, uint16_t size
,
62 int base_year
, int model
)
67 for (i
= 0; i
< ARRAY_SIZE(m48txx_isa_info
); i
++) {
68 if (m48txx_isa_info
[i
].size
!= size
||
69 m48txx_isa_info
[i
].model
!= model
) {
73 dev
= DEVICE(isa_create(bus
, m48txx_isa_info
[i
].bus_name
));
74 qdev_prop_set_uint32(dev
, "iobase", io_base
);
75 qdev_prop_set_int32(dev
, "base-year", base_year
);
76 qdev_init_nofail(dev
);
84 static uint32_t m48txx_isa_read(Nvram
*obj
, uint32_t addr
)
86 M48txxISAState
*d
= M48TXX_ISA(obj
);
87 return m48t59_read(&d
->state
, addr
);
90 static void m48txx_isa_write(Nvram
*obj
, uint32_t addr
, uint32_t val
)
92 M48txxISAState
*d
= M48TXX_ISA(obj
);
93 m48t59_write(&d
->state
, addr
, val
);
96 static void m48txx_isa_toggle_lock(Nvram
*obj
, int lock
)
98 M48txxISAState
*d
= M48TXX_ISA(obj
);
99 m48t59_toggle_lock(&d
->state
, lock
);
102 static Property m48t59_isa_properties
[] = {
103 DEFINE_PROP_INT32("base-year", M48txxISAState
, state
.base_year
, 0),
104 DEFINE_PROP_UINT32("iobase", M48txxISAState
, io_base
, 0x74),
105 DEFINE_PROP_END_OF_LIST(),
108 static void m48t59_reset_isa(DeviceState
*d
)
110 M48txxISAState
*isa
= M48TXX_ISA(d
);
111 M48t59State
*NVRAM
= &isa
->state
;
113 m48t59_reset_common(NVRAM
);
116 static void m48t59_isa_realize(DeviceState
*dev
, Error
**errp
)
118 M48txxISADeviceClass
*u
= M48TXX_ISA_GET_CLASS(dev
);
119 ISADevice
*isadev
= ISA_DEVICE(dev
);
120 M48txxISAState
*d
= M48TXX_ISA(dev
);
121 M48t59State
*s
= &d
->state
;
123 s
->model
= u
->info
.model
;
124 s
->size
= u
->info
.size
;
125 isa_init_irq(isadev
, &s
->IRQ
, 8);
126 m48t59_realize_common(s
, errp
);
127 memory_region_init_io(&d
->io
, OBJECT(dev
), &m48t59_io_ops
, s
, "m48t59", 4);
128 if (d
->io_base
!= 0) {
129 isa_register_ioport(isadev
, &d
->io
, d
->io_base
);
133 static void m48txx_isa_class_init(ObjectClass
*klass
, void *data
)
135 DeviceClass
*dc
= DEVICE_CLASS(klass
);
136 NvramClass
*nc
= NVRAM_CLASS(klass
);
138 dc
->realize
= m48t59_isa_realize
;
139 dc
->reset
= m48t59_reset_isa
;
140 dc
->props
= m48t59_isa_properties
;
141 nc
->read
= m48txx_isa_read
;
142 nc
->write
= m48txx_isa_write
;
143 nc
->toggle_lock
= m48txx_isa_toggle_lock
;
146 static void m48txx_isa_concrete_class_init(ObjectClass
*klass
, void *data
)
148 M48txxISADeviceClass
*u
= M48TXX_ISA_CLASS(klass
);
149 M48txxInfo
*info
= data
;
154 static const TypeInfo m48txx_isa_type_info
= {
155 .name
= TYPE_M48TXX_ISA
,
156 .parent
= TYPE_ISA_DEVICE
,
157 .instance_size
= sizeof(M48txxISAState
),
159 .class_init
= m48txx_isa_class_init
,
160 .interfaces
= (InterfaceInfo
[]) {
166 static void m48t59_isa_register_types(void)
168 TypeInfo isa_type_info
= {
169 .parent
= TYPE_M48TXX_ISA
,
170 .class_size
= sizeof(M48txxISADeviceClass
),
171 .class_init
= m48txx_isa_concrete_class_init
,
175 type_register_static(&m48txx_isa_type_info
);
177 for (i
= 0; i
< ARRAY_SIZE(m48txx_isa_info
); i
++) {
178 isa_type_info
.name
= m48txx_isa_info
[i
].bus_name
;
179 isa_type_info
.class_data
= &m48txx_isa_info
[i
];
180 type_register(&isa_type_info
);
184 type_init(m48t59_isa_register_types
)