hw/timer/xlnx-zynqmp-rtc.c

   1 /*
   2  * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
   3  *
   4  * Copyright (c) 2017 Xilinx Inc.
   5  *
   6  * Written-by: Alistair Francis <alistair.francis@xilinx.com>
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu-common.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/register.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/log.h"
  33 #include "qemu/module.h"
  34 #include "hw/irq.h"
  35 #include "hw/ptimer.h"
  36 #include "qemu/cutils.h"
  37 #include "sysemu/sysemu.h"
  38 #include "trace.h"
  39 #include "hw/timer/xlnx-zynqmp-rtc.h"
  40 #include "migration/vmstate.h"
  41
  42 #ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
  43 #define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
  44 #endif
  45
  46 static void rtc_int_update_irq(XlnxZynqMPRTC *s)
  47 {
  48     bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
  49     qemu_set_irq(s->irq_rtc_int, pending);
  50 }
  51
  52 static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
  53 {
  54     bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
  55     qemu_set_irq(s->irq_addr_error_int, pending);
  56 }
  57
  58 static uint32_t rtc_get_count(XlnxZynqMPRTC *s)
  59 {
  60     int64_t now = qemu_clock_get_ns(rtc_clock);
  61     return s->tick_offset + now / NANOSECONDS_PER_SECOND;
  62 }
  63
  64 static uint64_t current_time_postr(RegisterInfo *reg, uint64_t val64)
  65 {
  66     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  67
  68     return rtc_get_count(s);
  69 }
  70
  71 static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
  72 {
  73     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  74     rtc_int_update_irq(s);
  75 }
  76
  77 static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
  78 {
  79     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  80
  81     s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
  82     rtc_int_update_irq(s);
  83     return 0;
  84 }
  85
  86 static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
  87 {
  88     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  89
  90     s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
  91     rtc_int_update_irq(s);
  92     return 0;
  93 }
  94
  95 static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
  96 {
  97     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
  98     addr_error_int_update_irq(s);
  99 }
 100
 101 static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
 102 {
 103     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 104
 105     s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
 106     addr_error_int_update_irq(s);
 107     return 0;
 108 }
 109
 110 static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
 111 {
 112     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
 113
 114     s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
 115     addr_error_int_update_irq(s);
 116     return 0;
 117 }
 118
 119 static const RegisterAccessInfo rtc_regs_info[] = {
 120     {   .name = "SET_TIME_WRITE",  .addr = A_SET_TIME_WRITE,
 121         .unimp = MAKE_64BIT_MASK(0, 32),
 122     },{ .name = "SET_TIME_READ",  .addr = A_SET_TIME_READ,
 123         .ro = 0xffffffff,
 124         .post_read = current_time_postr,
 125     },{ .name = "CALIB_WRITE",  .addr = A_CALIB_WRITE,
 126         .unimp = MAKE_64BIT_MASK(0, 32),
 127     },{ .name = "CALIB_READ",  .addr = A_CALIB_READ,
 128         .ro = 0x1fffff,
 129     },{ .name = "CURRENT_TIME",  .addr = A_CURRENT_TIME,
 130         .ro = 0xffffffff,
 131         .post_read = current_time_postr,
 132     },{ .name = "CURRENT_TICK",  .addr = A_CURRENT_TICK,
 133         .ro = 0xffff,
 134     },{ .name = "ALARM",  .addr = A_ALARM,
 135     },{ .name = "RTC_INT_STATUS",  .addr = A_RTC_INT_STATUS,
 136         .w1c = 0x3,
 137         .post_write = rtc_int_status_postw,
 138     },{ .name = "RTC_INT_MASK",  .addr = A_RTC_INT_MASK,
 139         .reset = 0x3,
 140         .ro = 0x3,
 141     },{ .name = "RTC_INT_EN",  .addr = A_RTC_INT_EN,
 142         .pre_write = rtc_int_en_prew,
 143     },{ .name = "RTC_INT_DIS",  .addr = A_RTC_INT_DIS,
 144         .pre_write = rtc_int_dis_prew,
 145     },{ .name = "ADDR_ERROR",  .addr = A_ADDR_ERROR,
 146         .w1c = 0x1,
 147         .post_write = addr_error_postw,
 148     },{ .name = "ADDR_ERROR_INT_MASK",  .addr = A_ADDR_ERROR_INT_MASK,
 149         .reset = 0x1,
 150         .ro = 0x1,
 151     },{ .name = "ADDR_ERROR_INT_EN",  .addr = A_ADDR_ERROR_INT_EN,
 152         .pre_write = addr_error_int_en_prew,
 153     },{ .name = "ADDR_ERROR_INT_DIS",  .addr = A_ADDR_ERROR_INT_DIS,
 154         .pre_write = addr_error_int_dis_prew,
 155     },{ .name = "CONTROL",  .addr = A_CONTROL,
 156         .reset = 0x1000000,
 157         .rsvd = 0x70fffffe,
 158     },{ .name = "SAFETY_CHK",  .addr = A_SAFETY_CHK,
 159     }
 160 };
 161
 162 static void rtc_reset(DeviceState *dev)
 163 {
 164     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
 165     unsigned int i;
 166
 167     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
 168         register_reset(&s->regs_info[i]);
 169     }
 170
 171     rtc_int_update_irq(s);
 172     addr_error_int_update_irq(s);
 173 }
 174
 175 static const MemoryRegionOps rtc_ops = {
 176     .read = register_read_memory,
 177     .write = register_write_memory,
 178     .endianness = DEVICE_LITTLE_ENDIAN,
 179     .valid = {
 180         .min_access_size = 4,
 181         .max_access_size = 4,
 182     },
 183 };
 184
 185 static void rtc_init(Object *obj)
 186 {
 187     XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
 188     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 189     RegisterInfoArray *reg_array;
 190     struct tm current_tm;
 191
 192     memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
 193                        XLNX_ZYNQMP_RTC_R_MAX * 4);
 194     reg_array =
 195         register_init_block32(DEVICE(obj), rtc_regs_info,
 196                               ARRAY_SIZE(rtc_regs_info),
 197                               s->regs_info, s->regs,
 198                               &rtc_ops,
 199                               XLNX_ZYNQMP_RTC_ERR_DEBUG,
 200                               XLNX_ZYNQMP_RTC_R_MAX * 4);
 201     memory_region_add_subregion(&s->iomem,
 202                                 0x0,
 203                                 &reg_array->mem);
 204     sysbus_init_mmio(sbd, &s->iomem);
 205     sysbus_init_irq(sbd, &s->irq_rtc_int);
 206     sysbus_init_irq(sbd, &s->irq_addr_error_int);
 207
 208     qemu_get_timedate(&current_tm, 0);
 209     s->tick_offset = mktimegm(&current_tm) -
 210         qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 211
 212     trace_xlnx_zynqmp_rtc_gettime(current_tm.tm_year, current_tm.tm_mon,
 213                                   current_tm.tm_mday, current_tm.tm_hour,
 214                                   current_tm.tm_min, current_tm.tm_sec);
 215 }
 216
 217 static int rtc_pre_save(void *opaque)
 218 {
 219     XlnxZynqMPRTC *s = opaque;
 220     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 221
 222     /* Add the time at migration */
 223     s->tick_offset = s->tick_offset + now;
 224
 225     return 0;
 226 }
 227
 228 static int rtc_post_load(void *opaque, int version_id)
 229 {
 230     XlnxZynqMPRTC *s = opaque;
 231     int64_t now = qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
 232
 233     /* Subtract the time after migration. This combined with the pre_save
 234      * action results in us having subtracted the time that the guest was
 235      * stopped to the offset.
 236      */
 237     s->tick_offset = s->tick_offset - now;
 238
 239     return 0;
 240 }
 241
 242 static const VMStateDescription vmstate_rtc = {
 243     .name = TYPE_XLNX_ZYNQMP_RTC,
 244     .version_id = 1,
 245     .minimum_version_id = 1,
 246     .pre_save = rtc_pre_save,
 247     .post_load = rtc_post_load,
 248     .fields = (VMStateField[]) {
 249         VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
 250         VMSTATE_UINT32(tick_offset, XlnxZynqMPRTC),
 251         VMSTATE_END_OF_LIST(),
 252     }
 253 };
 254
 255 static void rtc_class_init(ObjectClass *klass, void *data)
 256 {
 257     DeviceClass *dc = DEVICE_CLASS(klass);
 258
 259     dc->reset = rtc_reset;
 260     dc->vmsd = &vmstate_rtc;
 261 }
 262
 263 static const TypeInfo rtc_info = {
 264     .name          = TYPE_XLNX_ZYNQMP_RTC,
 265     .parent        = TYPE_SYS_BUS_DEVICE,
 266     .instance_size = sizeof(XlnxZynqMPRTC),
 267     .class_init    = rtc_class_init,
 268     .instance_init = rtc_init,
 269 };
 270
 271 static void rtc_register_types(void)
 272 {
 273     type_register_static(&rtc_info);
 274 }
 275
 276 type_init(rtc_register_types)