monitor/qmp: Update comment for commit 4eaca8de268
[qemu/armbru.git] / target / arm / kvm32.c
blob2451a2d4bbefe104cdb28c24841c7fcc02420e7b
1 /*
2 * ARM implementation of KVM hooks, 32 bit specific code.
4 * Copyright Christoffer Dall 2009-2010
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
9 */
11 #include "qemu/osdep.h"
12 #include <sys/ioctl.h>
14 #include <linux/kvm.h>
16 #include "qemu-common.h"
17 #include "cpu.h"
18 #include "qemu/timer.h"
19 #include "sysemu/kvm.h"
20 #include "kvm_arm.h"
21 #include "internals.h"
22 #include "qemu/log.h"
24 static inline void set_feature(uint64_t *features, int feature)
26 *features |= 1ULL << feature;
29 static int read_sys_reg32(int fd, uint32_t *pret, uint64_t id)
31 struct kvm_one_reg idreg = { .id = id, .addr = (uintptr_t)pret };
33 assert((id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32);
34 return ioctl(fd, KVM_GET_ONE_REG, &idreg);
37 bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
39 /* Identify the feature bits corresponding to the host CPU, and
40 * fill out the ARMHostCPUClass fields accordingly. To do this
41 * we have to create a scratch VM, create a single CPU inside it,
42 * and then query that CPU for the relevant ID registers.
44 int err = 0, fdarray[3];
45 uint32_t midr, id_pfr0;
46 uint64_t features = 0;
48 /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
49 * we know these will only support creating one kind of guest CPU,
50 * which is its preferred CPU type.
52 static const uint32_t cpus_to_try[] = {
53 QEMU_KVM_ARM_TARGET_CORTEX_A15,
54 QEMU_KVM_ARM_TARGET_NONE
56 struct kvm_vcpu_init init;
58 if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
59 return false;
62 ahcf->target = init.target;
64 /* This is not strictly blessed by the device tree binding docs yet,
65 * but in practice the kernel does not care about this string so
66 * there is no point maintaining an KVM_ARM_TARGET_* -> string table.
68 ahcf->dtb_compatible = "arm,arm-v7";
70 err |= read_sys_reg32(fdarray[2], &midr, ARM_CP15_REG32(0, 0, 0, 0));
71 err |= read_sys_reg32(fdarray[2], &id_pfr0, ARM_CP15_REG32(0, 0, 1, 0));
73 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
74 ARM_CP15_REG32(0, 0, 2, 0));
75 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
76 ARM_CP15_REG32(0, 0, 2, 1));
77 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
78 ARM_CP15_REG32(0, 0, 2, 2));
79 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
80 ARM_CP15_REG32(0, 0, 2, 3));
81 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
82 ARM_CP15_REG32(0, 0, 2, 4));
83 err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
84 ARM_CP15_REG32(0, 0, 2, 5));
85 if (read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
86 ARM_CP15_REG32(0, 0, 2, 7))) {
88 * Older kernels don't support reading ID_ISAR6. This register was
89 * only introduced in ARMv8, so we can assume that it is zero on a
90 * CPU that a kernel this old is running on.
92 ahcf->isar.id_isar6 = 0;
95 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
96 KVM_REG_ARM | KVM_REG_SIZE_U32 |
97 KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0);
98 err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr1,
99 KVM_REG_ARM | KVM_REG_SIZE_U32 |
100 KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR1);
102 * FIXME: There is not yet a way to read MVFR2.
103 * Fortunately there is not yet anything in there that affects migration.
106 kvm_arm_destroy_scratch_host_vcpu(fdarray);
108 if (err < 0) {
109 return false;
112 /* Now we've retrieved all the register information we can
113 * set the feature bits based on the ID register fields.
114 * We can assume any KVM supporting CPU is at least a v7
115 * with VFPv3, virtualization extensions, and the generic
116 * timers; this in turn implies most of the other feature
117 * bits, but a few must be tested.
119 set_feature(&features, ARM_FEATURE_V7VE);
120 set_feature(&features, ARM_FEATURE_VFP3);
121 set_feature(&features, ARM_FEATURE_GENERIC_TIMER);
123 if (extract32(id_pfr0, 12, 4) == 1) {
124 set_feature(&features, ARM_FEATURE_THUMB2EE);
126 if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
127 set_feature(&features, ARM_FEATURE_NEON);
129 if (extract32(ahcf->isar.mvfr1, 28, 4) == 1) {
130 /* FMAC support implies VFPv4 */
131 set_feature(&features, ARM_FEATURE_VFP4);
134 ahcf->features = features;
136 return true;
139 bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
141 /* Return true if the regidx is a register we should synchronize
142 * via the cpreg_tuples array (ie is not a core reg we sync by
143 * hand in kvm_arch_get/put_registers())
145 switch (regidx & KVM_REG_ARM_COPROC_MASK) {
146 case KVM_REG_ARM_CORE:
147 case KVM_REG_ARM_VFP:
148 return false;
149 default:
150 return true;
154 typedef struct CPRegStateLevel {
155 uint64_t regidx;
156 int level;
157 } CPRegStateLevel;
159 /* All coprocessor registers not listed in the following table are assumed to
160 * be of the level KVM_PUT_RUNTIME_STATE. If a register should be written less
161 * often, you must add it to this table with a state of either
162 * KVM_PUT_RESET_STATE or KVM_PUT_FULL_STATE.
164 static const CPRegStateLevel non_runtime_cpregs[] = {
165 { KVM_REG_ARM_TIMER_CNT, KVM_PUT_FULL_STATE },
168 int kvm_arm_cpreg_level(uint64_t regidx)
170 int i;
172 for (i = 0; i < ARRAY_SIZE(non_runtime_cpregs); i++) {
173 const CPRegStateLevel *l = &non_runtime_cpregs[i];
174 if (l->regidx == regidx) {
175 return l->level;
179 return KVM_PUT_RUNTIME_STATE;
182 #define ARM_CPU_ID_MPIDR 0, 0, 0, 5
184 int kvm_arch_init_vcpu(CPUState *cs)
186 int ret;
187 uint64_t v;
188 uint32_t mpidr;
189 struct kvm_one_reg r;
190 ARMCPU *cpu = ARM_CPU(cs);
192 if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE) {
193 fprintf(stderr, "KVM is not supported for this guest CPU type\n");
194 return -EINVAL;
197 /* Determine init features for this CPU */
198 memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
199 if (cpu->start_powered_off) {
200 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
202 if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
203 cpu->psci_version = 2;
204 cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
207 /* Do KVM_ARM_VCPU_INIT ioctl */
208 ret = kvm_arm_vcpu_init(cs);
209 if (ret) {
210 return ret;
213 /* Query the kernel to make sure it supports 32 VFP
214 * registers: QEMU's "cortex-a15" CPU is always a
215 * VFP-D32 core. The simplest way to do this is just
216 * to attempt to read register d31.
218 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31;
219 r.addr = (uintptr_t)(&v);
220 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
221 if (ret == -ENOENT) {
222 return -EINVAL;
226 * When KVM is in use, PSCI is emulated in-kernel and not by qemu.
227 * Currently KVM has its own idea about MPIDR assignment, so we
228 * override our defaults with what we get from KVM.
230 ret = kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr);
231 if (ret) {
232 return ret;
234 cpu->mp_affinity = mpidr & ARM32_AFFINITY_MASK;
236 /* Check whether userspace can specify guest syndrome value */
237 kvm_arm_init_serror_injection(cs);
239 return kvm_arm_init_cpreg_list(cpu);
242 int kvm_arch_destroy_vcpu(CPUState *cs)
244 return 0;
247 typedef struct Reg {
248 uint64_t id;
249 int offset;
250 } Reg;
252 #define COREREG(KERNELNAME, QEMUFIELD) \
254 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
255 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
256 offsetof(CPUARMState, QEMUFIELD) \
259 #define VFPSYSREG(R) \
261 KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \
262 KVM_REG_ARM_VFP_##R, \
263 offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \
266 /* Like COREREG, but handle fields which are in a uint64_t in CPUARMState. */
267 #define COREREG64(KERNELNAME, QEMUFIELD) \
269 KVM_REG_ARM | KVM_REG_SIZE_U32 | \
270 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \
271 offsetoflow32(CPUARMState, QEMUFIELD) \
274 static const Reg regs[] = {
275 /* R0_usr .. R14_usr */
276 COREREG(usr_regs.uregs[0], regs[0]),
277 COREREG(usr_regs.uregs[1], regs[1]),
278 COREREG(usr_regs.uregs[2], regs[2]),
279 COREREG(usr_regs.uregs[3], regs[3]),
280 COREREG(usr_regs.uregs[4], regs[4]),
281 COREREG(usr_regs.uregs[5], regs[5]),
282 COREREG(usr_regs.uregs[6], regs[6]),
283 COREREG(usr_regs.uregs[7], regs[7]),
284 COREREG(usr_regs.uregs[8], usr_regs[0]),
285 COREREG(usr_regs.uregs[9], usr_regs[1]),
286 COREREG(usr_regs.uregs[10], usr_regs[2]),
287 COREREG(usr_regs.uregs[11], usr_regs[3]),
288 COREREG(usr_regs.uregs[12], usr_regs[4]),
289 COREREG(usr_regs.uregs[13], banked_r13[BANK_USRSYS]),
290 COREREG(usr_regs.uregs[14], banked_r14[BANK_USRSYS]),
291 /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */
292 COREREG(svc_regs[0], banked_r13[BANK_SVC]),
293 COREREG(svc_regs[1], banked_r14[BANK_SVC]),
294 COREREG64(svc_regs[2], banked_spsr[BANK_SVC]),
295 COREREG(abt_regs[0], banked_r13[BANK_ABT]),
296 COREREG(abt_regs[1], banked_r14[BANK_ABT]),
297 COREREG64(abt_regs[2], banked_spsr[BANK_ABT]),
298 COREREG(und_regs[0], banked_r13[BANK_UND]),
299 COREREG(und_regs[1], banked_r14[BANK_UND]),
300 COREREG64(und_regs[2], banked_spsr[BANK_UND]),
301 COREREG(irq_regs[0], banked_r13[BANK_IRQ]),
302 COREREG(irq_regs[1], banked_r14[BANK_IRQ]),
303 COREREG64(irq_regs[2], banked_spsr[BANK_IRQ]),
304 /* R8_fiq .. R14_fiq and SPSR_fiq */
305 COREREG(fiq_regs[0], fiq_regs[0]),
306 COREREG(fiq_regs[1], fiq_regs[1]),
307 COREREG(fiq_regs[2], fiq_regs[2]),
308 COREREG(fiq_regs[3], fiq_regs[3]),
309 COREREG(fiq_regs[4], fiq_regs[4]),
310 COREREG(fiq_regs[5], banked_r13[BANK_FIQ]),
311 COREREG(fiq_regs[6], banked_r14[BANK_FIQ]),
312 COREREG64(fiq_regs[7], banked_spsr[BANK_FIQ]),
313 /* R15 */
314 COREREG(usr_regs.uregs[15], regs[15]),
315 /* VFP system registers */
316 VFPSYSREG(FPSID),
317 VFPSYSREG(MVFR1),
318 VFPSYSREG(MVFR0),
319 VFPSYSREG(FPEXC),
320 VFPSYSREG(FPINST),
321 VFPSYSREG(FPINST2),
324 int kvm_arch_put_registers(CPUState *cs, int level)
326 ARMCPU *cpu = ARM_CPU(cs);
327 CPUARMState *env = &cpu->env;
328 struct kvm_one_reg r;
329 int mode, bn;
330 int ret, i;
331 uint32_t cpsr, fpscr;
333 /* Make sure the banked regs are properly set */
334 mode = env->uncached_cpsr & CPSR_M;
335 bn = bank_number(mode);
336 if (mode == ARM_CPU_MODE_FIQ) {
337 memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
338 } else {
339 memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
341 env->banked_r13[bn] = env->regs[13];
342 env->banked_spsr[bn] = env->spsr;
343 env->banked_r14[r14_bank_number(mode)] = env->regs[14];
345 /* Now we can safely copy stuff down to the kernel */
346 for (i = 0; i < ARRAY_SIZE(regs); i++) {
347 r.id = regs[i].id;
348 r.addr = (uintptr_t)(env) + regs[i].offset;
349 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
350 if (ret) {
351 return ret;
355 /* Special cases which aren't a single CPUARMState field */
356 cpsr = cpsr_read(env);
357 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
358 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
359 r.addr = (uintptr_t)(&cpsr);
360 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
361 if (ret) {
362 return ret;
365 /* VFP registers */
366 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
367 for (i = 0; i < 32; i++) {
368 r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
369 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
370 if (ret) {
371 return ret;
373 r.id++;
376 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
377 KVM_REG_ARM_VFP_FPSCR;
378 fpscr = vfp_get_fpscr(env);
379 r.addr = (uintptr_t)&fpscr;
380 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r);
381 if (ret) {
382 return ret;
385 ret = kvm_put_vcpu_events(cpu);
386 if (ret) {
387 return ret;
390 write_cpustate_to_list(cpu, true);
392 if (!write_list_to_kvmstate(cpu, level)) {
393 return EINVAL;
396 kvm_arm_sync_mpstate_to_kvm(cpu);
398 return ret;
401 int kvm_arch_get_registers(CPUState *cs)
403 ARMCPU *cpu = ARM_CPU(cs);
404 CPUARMState *env = &cpu->env;
405 struct kvm_one_reg r;
406 int mode, bn;
407 int ret, i;
408 uint32_t cpsr, fpscr;
410 for (i = 0; i < ARRAY_SIZE(regs); i++) {
411 r.id = regs[i].id;
412 r.addr = (uintptr_t)(env) + regs[i].offset;
413 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
414 if (ret) {
415 return ret;
419 /* Special cases which aren't a single CPUARMState field */
420 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 |
421 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr);
422 r.addr = (uintptr_t)(&cpsr);
423 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
424 if (ret) {
425 return ret;
427 cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw);
429 /* Make sure the current mode regs are properly set */
430 mode = env->uncached_cpsr & CPSR_M;
431 bn = bank_number(mode);
432 if (mode == ARM_CPU_MODE_FIQ) {
433 memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
434 } else {
435 memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
437 env->regs[13] = env->banked_r13[bn];
438 env->spsr = env->banked_spsr[bn];
439 env->regs[14] = env->banked_r14[r14_bank_number(mode)];
441 /* VFP registers */
442 r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
443 for (i = 0; i < 32; i++) {
444 r.addr = (uintptr_t)aa32_vfp_dreg(env, i);
445 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
446 if (ret) {
447 return ret;
449 r.id++;
452 r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP |
453 KVM_REG_ARM_VFP_FPSCR;
454 r.addr = (uintptr_t)&fpscr;
455 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
456 if (ret) {
457 return ret;
459 vfp_set_fpscr(env, fpscr);
461 ret = kvm_get_vcpu_events(cpu);
462 if (ret) {
463 return ret;
466 if (!write_kvmstate_to_list(cpu)) {
467 return EINVAL;
469 /* Note that it's OK to have registers which aren't in CPUState,
470 * so we can ignore a failure return here.
472 write_list_to_cpustate(cpu);
474 kvm_arm_sync_mpstate_to_qemu(cpu);
476 return 0;
479 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
481 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
482 return -EINVAL;
485 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
487 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
488 return -EINVAL;
491 bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
493 qemu_log_mask(LOG_UNIMP, "%s: guest debug not yet implemented\n", __func__);
494 return false;
497 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
498 target_ulong len, int type)
500 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
501 return -EINVAL;
504 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
505 target_ulong len, int type)
507 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
508 return -EINVAL;
511 void kvm_arch_remove_all_hw_breakpoints(void)
513 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
516 void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr)
518 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
521 bool kvm_arm_hw_debug_active(CPUState *cs)
523 return false;
526 void kvm_arm_pmu_set_irq(CPUState *cs, int irq)
528 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
531 void kvm_arm_pmu_init(CPUState *cs)
533 qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);