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monitor/qmp: Update comment for commit 4eaca8de268
[qemu/armbru.git] / target / ppc / kvm.c
blob6162a903fa199c99bc5a7900c255da0d8702b94f
1 /*
2 * PowerPC implementation of KVM hooks
3 *
4 * Copyright IBM Corp. 2007
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * Authors:
8 * Jerone Young <jyoung5@us.ibm.com>
9 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
10 * Hollis Blanchard <hollisb@us.ibm.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2 or later.
13 * See the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "qemu/osdep.h"
18 #include <dirent.h>
19 #include <sys/ioctl.h>
20 #include <sys/vfs.h>
21
22 #include <linux/kvm.h>
23
24 #include "qemu-common.h"
25 #include "qapi/error.h"
26 #include "qemu/error-report.h"
27 #include "cpu.h"
28 #include "cpu-models.h"
29 #include "qemu/timer.h"
30 #include "sysemu/hw_accel.h"
31 #include "kvm_ppc.h"
32 #include "sysemu/cpus.h"
33 #include "sysemu/device_tree.h"
34 #include "mmu-hash64.h"
35
36 #include "hw/sysbus.h"
37 #include "hw/ppc/spapr.h"
38 #include "hw/ppc/spapr_cpu_core.h"
39 #include "hw/hw.h"
40 #include "hw/ppc/ppc.h"
41 #include "migration/qemu-file-types.h"
42 #include "sysemu/watchdog.h"
43 #include "trace.h"
44 #include "exec/gdbstub.h"
45 #include "exec/memattrs.h"
46 #include "exec/ram_addr.h"
47 #include "sysemu/hostmem.h"
48 #include "qemu/cutils.h"
49 #include "qemu/main-loop.h"
50 #include "qemu/mmap-alloc.h"
51 #include "elf.h"
52 #include "sysemu/kvm_int.h"
53
54 #define PROC_DEVTREE_CPU "/proc/device-tree/cpus/"
55
56 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
57 KVM_CAP_LAST_INFO
58 };
59
60 static int cap_interrupt_unset;
61 static int cap_interrupt_level;
62 static int cap_segstate;
63 static int cap_booke_sregs;
64 static int cap_ppc_smt;
65 static int cap_ppc_smt_possible;
66 static int cap_spapr_tce;
67 static int cap_spapr_tce_64;
68 static int cap_spapr_multitce;
69 static int cap_spapr_vfio;
70 static int cap_hior;
71 static int cap_one_reg;
72 static int cap_epr;
73 static int cap_ppc_watchdog;
74 static int cap_papr;
75 static int cap_htab_fd;
76 static int cap_fixup_hcalls;
77 static int cap_htm; /* Hardware transactional memory support */
78 static int cap_mmu_radix;
79 static int cap_mmu_hash_v3;
80 static int cap_xive;
81 static int cap_resize_hpt;
82 static int cap_ppc_pvr_compat;
83 static int cap_ppc_safe_cache;
84 static int cap_ppc_safe_bounds_check;
85 static int cap_ppc_safe_indirect_branch;
86 static int cap_ppc_count_cache_flush_assist;
87 static int cap_ppc_nested_kvm_hv;
88 static int cap_large_decr;
89
90 static uint32_t debug_inst_opcode;
91
92 /*
93 * XXX We have a race condition where we actually have a level triggered
94 * interrupt, but the infrastructure can't expose that yet, so the guest
95 * takes but ignores it, goes to sleep and never gets notified that there's
96 * still an interrupt pending.
97 *
98 * As a quick workaround, let's just wake up again 20 ms after we injected
99 * an interrupt. That way we can assure that we're always reinjecting
100 * interrupts in case the guest swallowed them.
101 */
102 static QEMUTimer *idle_timer;
103
104 static void kvm_kick_cpu(void *opaque)
105 {
106 PowerPCCPU *cpu = opaque;
107
108 qemu_cpu_kick(CPU(cpu));
109 }
110
111 /*
112 * Check whether we are running with KVM-PR (instead of KVM-HV). This
113 * should only be used for fallback tests - generally we should use
114 * explicit capabilities for the features we want, rather than
115 * assuming what is/isn't available depending on the KVM variant.
116 */
117 static bool kvmppc_is_pr(KVMState *ks)
118 {
119 /* Assume KVM-PR if the GET_PVINFO capability is available */
120 return kvm_vm_check_extension(ks, KVM_CAP_PPC_GET_PVINFO) != 0;
121 }
122
123 static int kvm_ppc_register_host_cpu_type(MachineState *ms);
124 static void kvmppc_get_cpu_characteristics(KVMState *s);
125 static int kvmppc_get_dec_bits(void);
126
127 int kvm_arch_init(MachineState *ms, KVMState *s)
128 {
129 cap_interrupt_unset = kvm_check_extension(s, KVM_CAP_PPC_UNSET_IRQ);
130 cap_interrupt_level = kvm_check_extension(s, KVM_CAP_PPC_IRQ_LEVEL);
131 cap_segstate = kvm_check_extension(s, KVM_CAP_PPC_SEGSTATE);
132 cap_booke_sregs = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_SREGS);
133 cap_ppc_smt_possible = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT_POSSIBLE);
134 cap_spapr_tce = kvm_check_extension(s, KVM_CAP_SPAPR_TCE);
135 cap_spapr_tce_64 = kvm_check_extension(s, KVM_CAP_SPAPR_TCE_64);
136 cap_spapr_multitce = kvm_check_extension(s, KVM_CAP_SPAPR_MULTITCE);
137 cap_spapr_vfio = kvm_vm_check_extension(s, KVM_CAP_SPAPR_TCE_VFIO);
138 cap_one_reg = kvm_check_extension(s, KVM_CAP_ONE_REG);
139 cap_hior = kvm_check_extension(s, KVM_CAP_PPC_HIOR);
140 cap_epr = kvm_check_extension(s, KVM_CAP_PPC_EPR);
141 cap_ppc_watchdog = kvm_check_extension(s, KVM_CAP_PPC_BOOKE_WATCHDOG);
142 /*
143 * Note: we don't set cap_papr here, because this capability is
144 * only activated after this by kvmppc_set_papr()
145 */
146 cap_htab_fd = kvm_vm_check_extension(s, KVM_CAP_PPC_HTAB_FD);
147 cap_fixup_hcalls = kvm_check_extension(s, KVM_CAP_PPC_FIXUP_HCALL);
148 cap_ppc_smt = kvm_vm_check_extension(s, KVM_CAP_PPC_SMT);
149 cap_htm = kvm_vm_check_extension(s, KVM_CAP_PPC_HTM);
150 cap_mmu_radix = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_RADIX);
151 cap_mmu_hash_v3 = kvm_vm_check_extension(s, KVM_CAP_PPC_MMU_HASH_V3);
152 cap_xive = kvm_vm_check_extension(s, KVM_CAP_PPC_IRQ_XIVE);
153 cap_resize_hpt = kvm_vm_check_extension(s, KVM_CAP_SPAPR_RESIZE_HPT);
154 kvmppc_get_cpu_characteristics(s);
155 cap_ppc_nested_kvm_hv = kvm_vm_check_extension(s, KVM_CAP_PPC_NESTED_HV);
156 cap_large_decr = kvmppc_get_dec_bits();
157 /*
158 * Note: setting it to false because there is not such capability
159 * in KVM at this moment.
160 *
161 * TODO: call kvm_vm_check_extension() with the right capability
162 * after the kernel starts implementing it.
163 */
164 cap_ppc_pvr_compat = false;
165
166 if (!cap_interrupt_level) {
167 fprintf(stderr, "KVM: Couldn't find level irq capability. Expect the "
168 "VM to stall at times!\n");
169 }
170
171 kvm_ppc_register_host_cpu_type(ms);
172
173 return 0;
174 }
175
176 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
177 {
178 return 0;
179 }
180
181 static int kvm_arch_sync_sregs(PowerPCCPU *cpu)
182 {
183 CPUPPCState *cenv = &cpu->env;
184 CPUState *cs = CPU(cpu);
185 struct kvm_sregs sregs;
186 int ret;
187
188 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
189 /*
190 * What we're really trying to say is "if we're on BookE, we
191 * use the native PVR for now". This is the only sane way to
192 * check it though, so we potentially confuse users that they
193 * can run BookE guests on BookS. Let's hope nobody dares
194 * enough :)
195 */
196 return 0;
197 } else {
198 if (!cap_segstate) {
199 fprintf(stderr, "kvm error: missing PVR setting capability\n");
200 return -ENOSYS;
201 }
202 }
203
204 ret = kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs);
205 if (ret) {
206 return ret;
207 }
208
209 sregs.pvr = cenv->spr[SPR_PVR];
210 return kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs);
211 }
212
213 /* Set up a shared TLB array with KVM */
214 static int kvm_booke206_tlb_init(PowerPCCPU *cpu)
215 {
216 CPUPPCState *env = &cpu->env;
217 CPUState *cs = CPU(cpu);
218 struct kvm_book3e_206_tlb_params params = {};
219 struct kvm_config_tlb cfg = {};
220 unsigned int entries = 0;
221 int ret, i;
222
223 if (!kvm_enabled() ||
224 !kvm_check_extension(cs->kvm_state, KVM_CAP_SW_TLB)) {
225 return 0;
226 }
227
228 assert(ARRAY_SIZE(params.tlb_sizes) == BOOKE206_MAX_TLBN);
229
230 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
231 params.tlb_sizes[i] = booke206_tlb_size(env, i);
232 params.tlb_ways[i] = booke206_tlb_ways(env, i);
233 entries += params.tlb_sizes[i];
234 }
235
236 assert(entries == env->nb_tlb);
237 assert(sizeof(struct kvm_book3e_206_tlb_entry) == sizeof(ppcmas_tlb_t));
238
239 env->tlb_dirty = true;
240
241 cfg.array = (uintptr_t)env->tlb.tlbm;
242 cfg.array_len = sizeof(ppcmas_tlb_t) * entries;
243 cfg.params = (uintptr_t)&params;
244 cfg.mmu_type = KVM_MMU_FSL_BOOKE_NOHV;
245
246 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_SW_TLB, 0, (uintptr_t)&cfg);
247 if (ret < 0) {
248 fprintf(stderr, "%s: couldn't enable KVM_CAP_SW_TLB: %s\n",
249 __func__, strerror(-ret));
250 return ret;
251 }
252
253 env->kvm_sw_tlb = true;
254 return 0;
255 }
256
257
258 #if defined(TARGET_PPC64)
259 static void kvm_get_smmu_info(struct kvm_ppc_smmu_info *info, Error **errp)
260 {
261 int ret;
262
263 assert(kvm_state != NULL);
264
265 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_GET_SMMU_INFO)) {
266 error_setg(errp, "KVM doesn't expose the MMU features it supports");
267 error_append_hint(errp, "Consider switching to a newer KVM\n");
268 return;
269 }
270
271 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_SMMU_INFO, info);
272 if (ret == 0) {
273 return;
274 }
275
276 error_setg_errno(errp, -ret,
277 "KVM failed to provide the MMU features it supports");
278 }
279
280 struct ppc_radix_page_info *kvm_get_radix_page_info(void)
281 {
282 KVMState *s = KVM_STATE(current_machine->accelerator);
283 struct ppc_radix_page_info *radix_page_info;
284 struct kvm_ppc_rmmu_info rmmu_info;
285 int i;
286
287 if (!kvm_check_extension(s, KVM_CAP_PPC_MMU_RADIX)) {
288 return NULL;
289 }
290 if (kvm_vm_ioctl(s, KVM_PPC_GET_RMMU_INFO, &rmmu_info)) {
291 return NULL;
292 }
293 radix_page_info = g_malloc0(sizeof(*radix_page_info));
294 radix_page_info->count = 0;
295 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
296 if (rmmu_info.ap_encodings[i]) {
297 radix_page_info->entries[i] = rmmu_info.ap_encodings[i];
298 radix_page_info->count++;
299 }
300 }
301 return radix_page_info;
302 }
303
304 target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu,
305 bool radix, bool gtse,
306 uint64_t proc_tbl)
307 {
308 CPUState *cs = CPU(cpu);
309 int ret;
310 uint64_t flags = 0;
311 struct kvm_ppc_mmuv3_cfg cfg = {
312 .process_table = proc_tbl,
313 };
314
315 if (radix) {
316 flags |= KVM_PPC_MMUV3_RADIX;
317 }
318 if (gtse) {
319 flags |= KVM_PPC_MMUV3_GTSE;
320 }
321 cfg.flags = flags;
322 ret = kvm_vm_ioctl(cs->kvm_state, KVM_PPC_CONFIGURE_V3_MMU, &cfg);
323 switch (ret) {
324 case 0:
325 return H_SUCCESS;
326 case -EINVAL:
327 return H_PARAMETER;
328 case -ENODEV:
329 return H_NOT_AVAILABLE;
330 default:
331 return H_HARDWARE;
332 }
333 }
334
335 bool kvmppc_hpt_needs_host_contiguous_pages(void)
336 {
337 static struct kvm_ppc_smmu_info smmu_info;
338
339 if (!kvm_enabled()) {
340 return false;
341 }
342
343 kvm_get_smmu_info(&smmu_info, &error_fatal);
344 return !!(smmu_info.flags & KVM_PPC_PAGE_SIZES_REAL);
345 }
346
347 void kvm_check_mmu(PowerPCCPU *cpu, Error **errp)
348 {
349 struct kvm_ppc_smmu_info smmu_info;
350 int iq, ik, jq, jk;
351 Error *local_err = NULL;
352
353 /* For now, we only have anything to check on hash64 MMUs */
354 if (!cpu->hash64_opts || !kvm_enabled()) {
355 return;
356 }
357
358 kvm_get_smmu_info(&smmu_info, &local_err);
359 if (local_err) {
360 error_propagate(errp, local_err);
361 return;
362 }
363
364 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)
365 && !(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) {
366 error_setg(errp,
367 "KVM does not support 1TiB segments which guest expects");
368 return;
369 }
370
371 if (smmu_info.slb_size < cpu->hash64_opts->slb_size) {
372 error_setg(errp, "KVM only supports %u SLB entries, but guest needs %u",
373 smmu_info.slb_size, cpu->hash64_opts->slb_size);
374 return;
375 }
376
377 /*
378 * Verify that every pagesize supported by the cpu model is
379 * supported by KVM with the same encodings
380 */
381 for (iq = 0; iq < ARRAY_SIZE(cpu->hash64_opts->sps); iq++) {
382 PPCHash64SegmentPageSizes *qsps = &cpu->hash64_opts->sps[iq];
383 struct kvm_ppc_one_seg_page_size *ksps;
384
385 for (ik = 0; ik < ARRAY_SIZE(smmu_info.sps); ik++) {
386 if (qsps->page_shift == smmu_info.sps[ik].page_shift) {
387 break;
388 }
389 }
390 if (ik >= ARRAY_SIZE(smmu_info.sps)) {
391 error_setg(errp, "KVM doesn't support for base page shift %u",
392 qsps->page_shift);
393 return;
394 }
395
396 ksps = &smmu_info.sps[ik];
397 if (ksps->slb_enc != qsps->slb_enc) {
398 error_setg(errp,
399 "KVM uses SLB encoding 0x%x for page shift %u, but guest expects 0x%x",
400 ksps->slb_enc, ksps->page_shift, qsps->slb_enc);
401 return;
402 }
403
404 for (jq = 0; jq < ARRAY_SIZE(qsps->enc); jq++) {
405 for (jk = 0; jk < ARRAY_SIZE(ksps->enc); jk++) {
406 if (qsps->enc[jq].page_shift == ksps->enc[jk].page_shift) {
407 break;
408 }
409 }
410
411 if (jk >= ARRAY_SIZE(ksps->enc)) {
412 error_setg(errp, "KVM doesn't support page shift %u/%u",
413 qsps->enc[jq].page_shift, qsps->page_shift);
414 return;
415 }
416 if (qsps->enc[jq].pte_enc != ksps->enc[jk].pte_enc) {
417 error_setg(errp,
418 "KVM uses PTE encoding 0x%x for page shift %u/%u, but guest expects 0x%x",
419 ksps->enc[jk].pte_enc, qsps->enc[jq].page_shift,
420 qsps->page_shift, qsps->enc[jq].pte_enc);
421 return;
422 }
423 }
424 }
425
426 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
427 /*
428 * Mostly what guest pagesizes we can use are related to the
429 * host pages used to map guest RAM, which is handled in the
430 * platform code. Cache-Inhibited largepages (64k) however are
431 * used for I/O, so if they're mapped to the host at all it
432 * will be a normal mapping, not a special hugepage one used
433 * for RAM.
434 */
435 if (getpagesize() < 0x10000) {
436 error_setg(errp,
437 "KVM can't supply 64kiB CI pages, which guest expects");
438 }
439 }
440 }
441 #endif /* !defined (TARGET_PPC64) */
442
443 unsigned long kvm_arch_vcpu_id(CPUState *cpu)
444 {
445 return POWERPC_CPU(cpu)->vcpu_id;
446 }
447
448 /*
449 * e500 supports 2 h/w breakpoint and 2 watchpoint. book3s supports
450 * only 1 watchpoint, so array size of 4 is sufficient for now.
451 */
452 #define MAX_HW_BKPTS 4
453
454 static struct HWBreakpoint {
455 target_ulong addr;
456 int type;
457 } hw_debug_points[MAX_HW_BKPTS];
458
459 static CPUWatchpoint hw_watchpoint;
460
461 /* Default there is no breakpoint and watchpoint supported */
462 static int max_hw_breakpoint;
463 static int max_hw_watchpoint;
464 static int nb_hw_breakpoint;
465 static int nb_hw_watchpoint;
466
467 static void kvmppc_hw_debug_points_init(CPUPPCState *cenv)
468 {
469 if (cenv->excp_model == POWERPC_EXCP_BOOKE) {
470 max_hw_breakpoint = 2;
471 max_hw_watchpoint = 2;
472 }
473
474 if ((max_hw_breakpoint + max_hw_watchpoint) > MAX_HW_BKPTS) {
475 fprintf(stderr, "Error initializing h/w breakpoints\n");
476 return;
477 }
478 }
479
480 int kvm_arch_init_vcpu(CPUState *cs)
481 {
482 PowerPCCPU *cpu = POWERPC_CPU(cs);
483 CPUPPCState *cenv = &cpu->env;
484 int ret;
485
486 /* Synchronize sregs with kvm */
487 ret = kvm_arch_sync_sregs(cpu);
488 if (ret) {
489 if (ret == -EINVAL) {
490 error_report("Register sync failed... If you're using kvm-hv.ko,"
491 " only \"-cpu host\" is possible");
492 }
493 return ret;
494 }
495
496 idle_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, kvm_kick_cpu, cpu);
497
498 switch (cenv->mmu_model) {
499 case POWERPC_MMU_BOOKE206:
500 /* This target supports access to KVM's guest TLB */
501 ret = kvm_booke206_tlb_init(cpu);
502 break;
503 case POWERPC_MMU_2_07:
504 if (!cap_htm && !kvmppc_is_pr(cs->kvm_state)) {
505 /*
506 * KVM-HV has transactional memory on POWER8 also without
507 * the KVM_CAP_PPC_HTM extension, so enable it here
508 * instead as long as it's availble to userspace on the
509 * host.
510 */
511 if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) {
512 cap_htm = true;
513 }
514 }
515 break;
516 default:
517 break;
518 }
519
520 kvm_get_one_reg(cs, KVM_REG_PPC_DEBUG_INST, &debug_inst_opcode);
521 kvmppc_hw_debug_points_init(cenv);
522
523 return ret;
524 }
525
526 int kvm_arch_destroy_vcpu(CPUState *cs)
527 {
528 return 0;
529 }
530
531 static void kvm_sw_tlb_put(PowerPCCPU *cpu)
532 {
533 CPUPPCState *env = &cpu->env;
534 CPUState *cs = CPU(cpu);
535 struct kvm_dirty_tlb dirty_tlb;
536 unsigned char *bitmap;
537 int ret;
538
539 if (!env->kvm_sw_tlb) {
540 return;
541 }
542
543 bitmap = g_malloc((env->nb_tlb + 7) / 8);
544 memset(bitmap, 0xFF, (env->nb_tlb + 7) / 8);
545
546 dirty_tlb.bitmap = (uintptr_t)bitmap;
547 dirty_tlb.num_dirty = env->nb_tlb;
548
549 ret = kvm_vcpu_ioctl(cs, KVM_DIRTY_TLB, &dirty_tlb);
550 if (ret) {
551 fprintf(stderr, "%s: KVM_DIRTY_TLB: %s\n",
552 __func__, strerror(-ret));
553 }
554
555 g_free(bitmap);
556 }
557
558 static void kvm_get_one_spr(CPUState *cs, uint64_t id, int spr)
559 {
560 PowerPCCPU *cpu = POWERPC_CPU(cs);
561 CPUPPCState *env = &cpu->env;
562 union {
563 uint32_t u32;
564 uint64_t u64;
565 } val;
566 struct kvm_one_reg reg = {
567 .id = id,
568 .addr = (uintptr_t) &val,
569 };
570 int ret;
571
572 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
573 if (ret != 0) {
574 trace_kvm_failed_spr_get(spr, strerror(errno));
575 } else {
576 switch (id & KVM_REG_SIZE_MASK) {
577 case KVM_REG_SIZE_U32:
578 env->spr[spr] = val.u32;
579 break;
580
581 case KVM_REG_SIZE_U64:
582 env->spr[spr] = val.u64;
583 break;
584
585 default:
586 /* Don't handle this size yet */
587 abort();
588 }
589 }
590 }
591
592 static void kvm_put_one_spr(CPUState *cs, uint64_t id, int spr)
593 {
594 PowerPCCPU *cpu = POWERPC_CPU(cs);
595 CPUPPCState *env = &cpu->env;
596 union {
597 uint32_t u32;
598 uint64_t u64;
599 } val;
600 struct kvm_one_reg reg = {
601 .id = id,
602 .addr = (uintptr_t) &val,
603 };
604 int ret;
605
606 switch (id & KVM_REG_SIZE_MASK) {
607 case KVM_REG_SIZE_U32:
608 val.u32 = env->spr[spr];
609 break;
610
611 case KVM_REG_SIZE_U64:
612 val.u64 = env->spr[spr];
613 break;
614
615 default:
616 /* Don't handle this size yet */
617 abort();
618 }
619
620 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
621 if (ret != 0) {
622 trace_kvm_failed_spr_set(spr, strerror(errno));
623 }
624 }
625
626 static int kvm_put_fp(CPUState *cs)
627 {
628 PowerPCCPU *cpu = POWERPC_CPU(cs);
629 CPUPPCState *env = &cpu->env;
630 struct kvm_one_reg reg;
631 int i;
632 int ret;
633
634 if (env->insns_flags & PPC_FLOAT) {
635 uint64_t fpscr = env->fpscr;
636 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
637
638 reg.id = KVM_REG_PPC_FPSCR;
639 reg.addr = (uintptr_t)&fpscr;
640 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
641 if (ret < 0) {
642 trace_kvm_failed_fpscr_set(strerror(errno));
643 return ret;
644 }
645
646 for (i = 0; i < 32; i++) {
647 uint64_t vsr[2];
648 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
649 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
650
651 #ifdef HOST_WORDS_BIGENDIAN
652 vsr[0] = float64_val(*fpr);
653 vsr[1] = *vsrl;
654 #else
655 vsr[0] = *vsrl;
656 vsr[1] = float64_val(*fpr);
657 #endif
658 reg.addr = (uintptr_t) &vsr;
659 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
660
661 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
662 if (ret < 0) {
663 trace_kvm_failed_fp_set(vsx ? "VSR" : "FPR", i,
664 strerror(errno));
665 return ret;
666 }
667 }
668 }
669
670 if (env->insns_flags & PPC_ALTIVEC) {
671 reg.id = KVM_REG_PPC_VSCR;
672 reg.addr = (uintptr_t)&env->vscr;
673 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
674 if (ret < 0) {
675 trace_kvm_failed_vscr_set(strerror(errno));
676 return ret;
677 }
678
679 for (i = 0; i < 32; i++) {
680 reg.id = KVM_REG_PPC_VR(i);
681 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
682 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
683 if (ret < 0) {
684 trace_kvm_failed_vr_set(i, strerror(errno));
685 return ret;
686 }
687 }
688 }
689
690 return 0;
691 }
692
693 static int kvm_get_fp(CPUState *cs)
694 {
695 PowerPCCPU *cpu = POWERPC_CPU(cs);
696 CPUPPCState *env = &cpu->env;
697 struct kvm_one_reg reg;
698 int i;
699 int ret;
700
701 if (env->insns_flags & PPC_FLOAT) {
702 uint64_t fpscr;
703 bool vsx = !!(env->insns_flags2 & PPC2_VSX);
704
705 reg.id = KVM_REG_PPC_FPSCR;
706 reg.addr = (uintptr_t)&fpscr;
707 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
708 if (ret < 0) {
709 trace_kvm_failed_fpscr_get(strerror(errno));
710 return ret;
711 } else {
712 env->fpscr = fpscr;
713 }
714
715 for (i = 0; i < 32; i++) {
716 uint64_t vsr[2];
717 uint64_t *fpr = cpu_fpr_ptr(&cpu->env, i);
718 uint64_t *vsrl = cpu_vsrl_ptr(&cpu->env, i);
719
720 reg.addr = (uintptr_t) &vsr;
721 reg.id = vsx ? KVM_REG_PPC_VSR(i) : KVM_REG_PPC_FPR(i);
722
723 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
724 if (ret < 0) {
725 trace_kvm_failed_fp_get(vsx ? "VSR" : "FPR", i,
726 strerror(errno));
727 return ret;
728 } else {
729 #ifdef HOST_WORDS_BIGENDIAN
730 *fpr = vsr[0];
731 if (vsx) {
732 *vsrl = vsr[1];
733 }
734 #else
735 *fpr = vsr[1];
736 if (vsx) {
737 *vsrl = vsr[0];
738 }
739 #endif
740 }
741 }
742 }
743
744 if (env->insns_flags & PPC_ALTIVEC) {
745 reg.id = KVM_REG_PPC_VSCR;
746 reg.addr = (uintptr_t)&env->vscr;
747 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
748 if (ret < 0) {
749 trace_kvm_failed_vscr_get(strerror(errno));
750 return ret;
751 }
752
753 for (i = 0; i < 32; i++) {
754 reg.id = KVM_REG_PPC_VR(i);
755 reg.addr = (uintptr_t)cpu_avr_ptr(env, i);
756 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
757 if (ret < 0) {
758 trace_kvm_failed_vr_get(i, strerror(errno));
759 return ret;
760 }
761 }
762 }
763
764 return 0;
765 }
766
767 #if defined(TARGET_PPC64)
768 static int kvm_get_vpa(CPUState *cs)
769 {
770 PowerPCCPU *cpu = POWERPC_CPU(cs);
771 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
772 struct kvm_one_reg reg;
773 int ret;
774
775 reg.id = KVM_REG_PPC_VPA_ADDR;
776 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
777 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
778 if (ret < 0) {
779 trace_kvm_failed_vpa_addr_get(strerror(errno));
780 return ret;
781 }
782
783 assert((uintptr_t)&spapr_cpu->slb_shadow_size
784 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
785 reg.id = KVM_REG_PPC_VPA_SLB;
786 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
787 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
788 if (ret < 0) {
789 trace_kvm_failed_slb_get(strerror(errno));
790 return ret;
791 }
792
793 assert((uintptr_t)&spapr_cpu->dtl_size
794 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
795 reg.id = KVM_REG_PPC_VPA_DTL;
796 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
797 ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
798 if (ret < 0) {
799 trace_kvm_failed_dtl_get(strerror(errno));
800 return ret;
801 }
802
803 return 0;
804 }
805
806 static int kvm_put_vpa(CPUState *cs)
807 {
808 PowerPCCPU *cpu = POWERPC_CPU(cs);
809 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
810 struct kvm_one_reg reg;
811 int ret;
812
813 /*
814 * SLB shadow or DTL can't be registered unless a master VPA is
815 * registered. That means when restoring state, if a VPA *is*
816 * registered, we need to set that up first. If not, we need to
817 * deregister the others before deregistering the master VPA
818 */
819 assert(spapr_cpu->vpa_addr
820 || !(spapr_cpu->slb_shadow_addr || spapr_cpu->dtl_addr));
821
822 if (spapr_cpu->vpa_addr) {
823 reg.id = KVM_REG_PPC_VPA_ADDR;
824 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
825 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
826 if (ret < 0) {
827 trace_kvm_failed_vpa_addr_set(strerror(errno));
828 return ret;
829 }
830 }
831
832 assert((uintptr_t)&spapr_cpu->slb_shadow_size
833 == ((uintptr_t)&spapr_cpu->slb_shadow_addr + 8));
834 reg.id = KVM_REG_PPC_VPA_SLB;
835 reg.addr = (uintptr_t)&spapr_cpu->slb_shadow_addr;
836 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
837 if (ret < 0) {
838 trace_kvm_failed_slb_set(strerror(errno));
839 return ret;
840 }
841
842 assert((uintptr_t)&spapr_cpu->dtl_size
843 == ((uintptr_t)&spapr_cpu->dtl_addr + 8));
844 reg.id = KVM_REG_PPC_VPA_DTL;
845 reg.addr = (uintptr_t)&spapr_cpu->dtl_addr;
846 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
847 if (ret < 0) {
848 trace_kvm_failed_dtl_set(strerror(errno));
849 return ret;
850 }
851
852 if (!spapr_cpu->vpa_addr) {
853 reg.id = KVM_REG_PPC_VPA_ADDR;
854 reg.addr = (uintptr_t)&spapr_cpu->vpa_addr;
855 ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
856 if (ret < 0) {
857 trace_kvm_failed_null_vpa_addr_set(strerror(errno));
858 return ret;
859 }
860 }
861
862 return 0;
863 }
864 #endif /* TARGET_PPC64 */
865
866 int kvmppc_put_books_sregs(PowerPCCPU *cpu)
867 {
868 CPUPPCState *env = &cpu->env;
869 struct kvm_sregs sregs;
870 int i;
871
872 sregs.pvr = env->spr[SPR_PVR];
873
874 if (cpu->vhyp) {
875 PPCVirtualHypervisorClass *vhc =
876 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
877 sregs.u.s.sdr1 = vhc->encode_hpt_for_kvm_pr(cpu->vhyp);
878 } else {
879 sregs.u.s.sdr1 = env->spr[SPR_SDR1];
880 }
881
882 /* Sync SLB */
883 #ifdef TARGET_PPC64
884 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
885 sregs.u.s.ppc64.slb[i].slbe = env->slb[i].esid;
886 if (env->slb[i].esid & SLB_ESID_V) {
887 sregs.u.s.ppc64.slb[i].slbe |= i;
888 }
889 sregs.u.s.ppc64.slb[i].slbv = env->slb[i].vsid;
890 }
891 #endif
892
893 /* Sync SRs */
894 for (i = 0; i < 16; i++) {
895 sregs.u.s.ppc32.sr[i] = env->sr[i];
896 }
897
898 /* Sync BATs */
899 for (i = 0; i < 8; i++) {
900 /* Beware. We have to swap upper and lower bits here */
901 sregs.u.s.ppc32.dbat[i] = ((uint64_t)env->DBAT[0][i] << 32)
902 | env->DBAT[1][i];
903 sregs.u.s.ppc32.ibat[i] = ((uint64_t)env->IBAT[0][i] << 32)
904 | env->IBAT[1][i];
905 }
906
907 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
908 }
909
910 int kvm_arch_put_registers(CPUState *cs, int level)
911 {
912 PowerPCCPU *cpu = POWERPC_CPU(cs);
913 CPUPPCState *env = &cpu->env;
914 struct kvm_regs regs;
915 int ret;
916 int i;
917
918 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
919 if (ret < 0) {
920 return ret;
921 }
922
923 regs.ctr = env->ctr;
924 regs.lr = env->lr;
925 regs.xer = cpu_read_xer(env);
926 regs.msr = env->msr;
927 regs.pc = env->nip;
928
929 regs.srr0 = env->spr[SPR_SRR0];
930 regs.srr1 = env->spr[SPR_SRR1];
931
932 regs.sprg0 = env->spr[SPR_SPRG0];
933 regs.sprg1 = env->spr[SPR_SPRG1];
934 regs.sprg2 = env->spr[SPR_SPRG2];
935 regs.sprg3 = env->spr[SPR_SPRG3];
936 regs.sprg4 = env->spr[SPR_SPRG4];
937 regs.sprg5 = env->spr[SPR_SPRG5];
938 regs.sprg6 = env->spr[SPR_SPRG6];
939 regs.sprg7 = env->spr[SPR_SPRG7];
940
941 regs.pid = env->spr[SPR_BOOKE_PID];
942
943 for (i = 0; i < 32; i++) {
944 regs.gpr[i] = env->gpr[i];
945 }
946
947 regs.cr = 0;
948 for (i = 0; i < 8; i++) {
949 regs.cr |= (env->crf[i] & 15) << (4 * (7 - i));
950 }
951
952 ret = kvm_vcpu_ioctl(cs, KVM_SET_REGS, &regs);
953 if (ret < 0) {
954 return ret;
955 }
956
957 kvm_put_fp(cs);
958
959 if (env->tlb_dirty) {
960 kvm_sw_tlb_put(cpu);
961 env->tlb_dirty = false;
962 }
963
964 if (cap_segstate && (level >= KVM_PUT_RESET_STATE)) {
965 ret = kvmppc_put_books_sregs(cpu);
966 if (ret < 0) {
967 return ret;
968 }
969 }
970
971 if (cap_hior && (level >= KVM_PUT_RESET_STATE)) {
972 kvm_put_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
973 }
974
975 if (cap_one_reg) {
976 int i;
977
978 /*
979 * We deliberately ignore errors here, for kernels which have
980 * the ONE_REG calls, but don't support the specific
981 * registers, there's a reasonable chance things will still
982 * work, at least until we try to migrate.
983 */
984 for (i = 0; i < 1024; i++) {
985 uint64_t id = env->spr_cb[i].one_reg_id;
986
987 if (id != 0) {
988 kvm_put_one_spr(cs, id, i);
989 }
990 }
991
992 #ifdef TARGET_PPC64
993 if (msr_ts) {
994 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
995 kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
996 }
997 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
998 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
999 }
1000 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1001 kvm_set_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1002 kvm_set_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1003 kvm_set_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1004 kvm_set_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1005 kvm_set_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1006 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1007 kvm_set_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1008 kvm_set_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1009 kvm_set_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1010 }
1011
1012 if (cap_papr) {
1013 if (kvm_put_vpa(cs) < 0) {
1014 trace_kvm_failed_put_vpa();
1015 }
1016 }
1017
1018 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1019 #endif /* TARGET_PPC64 */
1020 }
1021
1022 return ret;
1023 }
1024
1025 static void kvm_sync_excp(CPUPPCState *env, int vector, int ivor)
1026 {
1027 env->excp_vectors[vector] = env->spr[ivor] + env->spr[SPR_BOOKE_IVPR];
1028 }
1029
1030 static int kvmppc_get_booke_sregs(PowerPCCPU *cpu)
1031 {
1032 CPUPPCState *env = &cpu->env;
1033 struct kvm_sregs sregs;
1034 int ret;
1035
1036 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1037 if (ret < 0) {
1038 return ret;
1039 }
1040
1041 if (sregs.u.e.features & KVM_SREGS_E_BASE) {
1042 env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;
1043 env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;
1044 env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;
1045 env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;
1046 env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;
1047 env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;
1048 env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;
1049 env->spr[SPR_DECR] = sregs.u.e.dec;
1050 env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;
1051 env->spr[SPR_TBU] = sregs.u.e.tb >> 32;
1052 env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;
1053 }
1054
1055 if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {
1056 env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;
1057 env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;
1058 env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;
1059 env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;
1060 env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;
1061 }
1062
1063 if (sregs.u.e.features & KVM_SREGS_E_64) {
1064 env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;
1065 }
1066
1067 if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {
1068 env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;
1069 }
1070
1071 if (sregs.u.e.features & KVM_SREGS_E_IVOR) {
1072 env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];
1073 kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0);
1074 env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];
1075 kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1);
1076 env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];
1077 kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2);
1078 env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];
1079 kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3);
1080 env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];
1081 kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4);
1082 env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];
1083 kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5);
1084 env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];
1085 kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6);
1086 env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];
1087 kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7);
1088 env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];
1089 kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8);
1090 env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];
1091 kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9);
1092 env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];
1093 kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10);
1094 env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];
1095 kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11);
1096 env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];
1097 kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12);
1098 env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];
1099 kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13);
1100 env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];
1101 kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14);
1102 env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];
1103 kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15);
1104
1105 if (sregs.u.e.features & KVM_SREGS_E_SPE) {
1106 env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];
1107 kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32);
1108 env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];
1109 kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33);
1110 env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];
1111 kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34);
1112 }
1113
1114 if (sregs.u.e.features & KVM_SREGS_E_PM) {
1115 env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];
1116 kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35);
1117 }
1118
1119 if (sregs.u.e.features & KVM_SREGS_E_PC) {
1120 env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];
1121 kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36);
1122 env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];
1123 kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37);
1124 }
1125 }
1126
1127 if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {
1128 env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;
1129 env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;
1130 env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;
1131 env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;
1132 env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;
1133 env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;
1134 env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;
1135 env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;
1136 env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];
1137 env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];
1138 }
1139
1140 if (sregs.u.e.features & KVM_SREGS_EXP) {
1141 env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;
1142 }
1143
1144 if (sregs.u.e.features & KVM_SREGS_E_PD) {
1145 env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;
1146 env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;
1147 }
1148
1149 if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {
1150 env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;
1151 env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;
1152 env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;
1153
1154 if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {
1155 env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;
1156 env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;
1157 }
1158 }
1159
1160 return 0;
1161 }
1162
1163 static int kvmppc_get_books_sregs(PowerPCCPU *cpu)
1164 {
1165 CPUPPCState *env = &cpu->env;
1166 struct kvm_sregs sregs;
1167 int ret;
1168 int i;
1169
1170 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1171 if (ret < 0) {
1172 return ret;
1173 }
1174
1175 if (!cpu->vhyp) {
1176 ppc_store_sdr1(env, sregs.u.s.sdr1);
1177 }
1178
1179 /* Sync SLB */
1180 #ifdef TARGET_PPC64
1181 /*
1182 * The packed SLB array we get from KVM_GET_SREGS only contains
1183 * information about valid entries. So we flush our internal copy
1184 * to get rid of stale ones, then put all valid SLB entries back
1185 * in.
1186 */
1187 memset(env->slb, 0, sizeof(env->slb));
1188 for (i = 0; i < ARRAY_SIZE(env->slb); i++) {
1189 target_ulong rb = sregs.u.s.ppc64.slb[i].slbe;
1190 target_ulong rs = sregs.u.s.ppc64.slb[i].slbv;
1191 /*
1192 * Only restore valid entries
1193 */
1194 if (rb & SLB_ESID_V) {
1195 ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs);
1196 }
1197 }
1198 #endif
1199
1200 /* Sync SRs */
1201 for (i = 0; i < 16; i++) {
1202 env->sr[i] = sregs.u.s.ppc32.sr[i];
1203 }
1204
1205 /* Sync BATs */
1206 for (i = 0; i < 8; i++) {
1207 env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
1208 env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
1209 env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
1210 env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
1211 }
1212
1213 return 0;
1214 }
1215
1216 int kvm_arch_get_registers(CPUState *cs)
1217 {
1218 PowerPCCPU *cpu = POWERPC_CPU(cs);
1219 CPUPPCState *env = &cpu->env;
1220 struct kvm_regs regs;
1221 uint32_t cr;
1222 int i, ret;
1223
1224 ret = kvm_vcpu_ioctl(cs, KVM_GET_REGS, &regs);
1225 if (ret < 0) {
1226 return ret;
1227 }
1228
1229 cr = regs.cr;
1230 for (i = 7; i >= 0; i--) {
1231 env->crf[i] = cr & 15;
1232 cr >>= 4;
1233 }
1234
1235 env->ctr = regs.ctr;
1236 env->lr = regs.lr;
1237 cpu_write_xer(env, regs.xer);
1238 env->msr = regs.msr;
1239 env->nip = regs.pc;
1240
1241 env->spr[SPR_SRR0] = regs.srr0;
1242 env->spr[SPR_SRR1] = regs.srr1;
1243
1244 env->spr[SPR_SPRG0] = regs.sprg0;
1245 env->spr[SPR_SPRG1] = regs.sprg1;
1246 env->spr[SPR_SPRG2] = regs.sprg2;
1247 env->spr[SPR_SPRG3] = regs.sprg3;
1248 env->spr[SPR_SPRG4] = regs.sprg4;
1249 env->spr[SPR_SPRG5] = regs.sprg5;
1250 env->spr[SPR_SPRG6] = regs.sprg6;
1251 env->spr[SPR_SPRG7] = regs.sprg7;
1252
1253 env->spr[SPR_BOOKE_PID] = regs.pid;
1254
1255 for (i = 0; i < 32; i++) {
1256 env->gpr[i] = regs.gpr[i];
1257 }
1258
1259 kvm_get_fp(cs);
1260
1261 if (cap_booke_sregs) {
1262 ret = kvmppc_get_booke_sregs(cpu);
1263 if (ret < 0) {
1264 return ret;
1265 }
1266 }
1267
1268 if (cap_segstate) {
1269 ret = kvmppc_get_books_sregs(cpu);
1270 if (ret < 0) {
1271 return ret;
1272 }
1273 }
1274
1275 if (cap_hior) {
1276 kvm_get_one_spr(cs, KVM_REG_PPC_HIOR, SPR_HIOR);
1277 }
1278
1279 if (cap_one_reg) {
1280 int i;
1281
1282 /*
1283 * We deliberately ignore errors here, for kernels which have
1284 * the ONE_REG calls, but don't support the specific
1285 * registers, there's a reasonable chance things will still
1286 * work, at least until we try to migrate.
1287 */
1288 for (i = 0; i < 1024; i++) {
1289 uint64_t id = env->spr_cb[i].one_reg_id;
1290
1291 if (id != 0) {
1292 kvm_get_one_spr(cs, id, i);
1293 }
1294 }
1295
1296 #ifdef TARGET_PPC64
1297 if (msr_ts) {
1298 for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
1299 kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
1300 }
1301 for (i = 0; i < ARRAY_SIZE(env->tm_vsr); i++) {
1302 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSR(i), &env->tm_vsr[i]);
1303 }
1304 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CR, &env->tm_cr);
1305 kvm_get_one_reg(cs, KVM_REG_PPC_TM_LR, &env->tm_lr);
1306 kvm_get_one_reg(cs, KVM_REG_PPC_TM_CTR, &env->tm_ctr);
1307 kvm_get_one_reg(cs, KVM_REG_PPC_TM_FPSCR, &env->tm_fpscr);
1308 kvm_get_one_reg(cs, KVM_REG_PPC_TM_AMR, &env->tm_amr);
1309 kvm_get_one_reg(cs, KVM_REG_PPC_TM_PPR, &env->tm_ppr);
1310 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VRSAVE, &env->tm_vrsave);
1311 kvm_get_one_reg(cs, KVM_REG_PPC_TM_VSCR, &env->tm_vscr);
1312 kvm_get_one_reg(cs, KVM_REG_PPC_TM_DSCR, &env->tm_dscr);
1313 kvm_get_one_reg(cs, KVM_REG_PPC_TM_TAR, &env->tm_tar);
1314 }
1315
1316 if (cap_papr) {
1317 if (kvm_get_vpa(cs) < 0) {
1318 trace_kvm_failed_get_vpa();
1319 }
1320 }
1321
1322 kvm_get_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &env->tb_env->tb_offset);
1323 #endif
1324 }
1325
1326 return 0;
1327 }
1328
1329 int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level)
1330 {
1331 unsigned virq = level ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
1332
1333 if (irq != PPC_INTERRUPT_EXT) {
1334 return 0;
1335 }
1336
1337 if (!kvm_enabled() || !cap_interrupt_unset || !cap_interrupt_level) {
1338 return 0;
1339 }
1340
1341 kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
1342
1343 return 0;
1344 }
1345
1346 #if defined(TARGET_PPC64)
1347 #define PPC_INPUT_INT PPC970_INPUT_INT
1348 #else
1349 #define PPC_INPUT_INT PPC6xx_INPUT_INT
1350 #endif
1351
1352 void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
1353 {
1354 PowerPCCPU *cpu = POWERPC_CPU(cs);
1355 CPUPPCState *env = &cpu->env;
1356 int r;
1357 unsigned irq;
1358
1359 qemu_mutex_lock_iothread();
1360
1361 /*
1362 * PowerPC QEMU tracks the various core input pins (interrupt,
1363 * critical interrupt, reset, etc) in PPC-specific
1364 * env->irq_input_state.
1365 */
1366 if (!cap_interrupt_level &&
1367 run->ready_for_interrupt_injection &&
1368 (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
1369 (env->irq_input_state & (1 << PPC_INPUT_INT)))
1370 {
1371 /*
1372 * For now KVM disregards the 'irq' argument. However, in the
1373 * future KVM could cache it in-kernel to avoid a heavyweight
1374 * exit when reading the UIC.
1375 */
1376 irq = KVM_INTERRUPT_SET;
1377
1378 trace_kvm_injected_interrupt(irq);
1379 r = kvm_vcpu_ioctl(cs, KVM_INTERRUPT, &irq);
1380 if (r < 0) {
1381 printf("cpu %d fail inject %x\n", cs->cpu_index, irq);
1382 }
1383
1384 /* Always wake up soon in case the interrupt was level based */
1385 timer_mod(idle_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1386 (NANOSECONDS_PER_SECOND / 50));
1387 }
1388
1389 /*
1390 * We don't know if there are more interrupts pending after
1391 * this. However, the guest will return to userspace in the course
1392 * of handling this one anyways, so we will get a chance to
1393 * deliver the rest.
1394 */
1395
1396 qemu_mutex_unlock_iothread();
1397 }
1398
1399 MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
1400 {
1401 return MEMTXATTRS_UNSPECIFIED;
1402 }
1403
1404 int kvm_arch_process_async_events(CPUState *cs)
1405 {
1406 return cs->halted;
1407 }
1408
1409 static int kvmppc_handle_halt(PowerPCCPU *cpu)
1410 {
1411 CPUState *cs = CPU(cpu);
1412 CPUPPCState *env = &cpu->env;
1413
1414 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
1415 cs->halted = 1;
1416 cs->exception_index = EXCP_HLT;
1417 }
1418
1419 return 0;
1420 }
1421
1422 /* map dcr access to existing qemu dcr emulation */
1423 static int kvmppc_handle_dcr_read(CPUPPCState *env,
1424 uint32_t dcrn, uint32_t *data)
1425 {
1426 if (ppc_dcr_read(env->dcr_env, dcrn, data) < 0) {
1427 fprintf(stderr, "Read to unhandled DCR (0x%x)\n", dcrn);
1428 }
1429
1430 return 0;
1431 }
1432
1433 static int kvmppc_handle_dcr_write(CPUPPCState *env,
1434 uint32_t dcrn, uint32_t data)
1435 {
1436 if (ppc_dcr_write(env->dcr_env, dcrn, data) < 0) {
1437 fprintf(stderr, "Write to unhandled DCR (0x%x)\n", dcrn);
1438 }
1439
1440 return 0;
1441 }
1442
1443 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1444 {
1445 /* Mixed endian case is not handled */
1446 uint32_t sc = debug_inst_opcode;
1447
1448 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1449 sizeof(sc), 0) ||
1450 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 1)) {
1451 return -EINVAL;
1452 }
1453
1454 return 0;
1455 }
1456
1457 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
1458 {
1459 uint32_t sc;
1460
1461 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&sc, sizeof(sc), 0) ||
1462 sc != debug_inst_opcode ||
1463 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
1464 sizeof(sc), 1)) {
1465 return -EINVAL;
1466 }
1467
1468 return 0;
1469 }
1470
1471 static int find_hw_breakpoint(target_ulong addr, int type)
1472 {
1473 int n;
1474
1475 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1476 <= ARRAY_SIZE(hw_debug_points));
1477
1478 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1479 if (hw_debug_points[n].addr == addr &&
1480 hw_debug_points[n].type == type) {
1481 return n;
1482 }
1483 }
1484
1485 return -1;
1486 }
1487
1488 static int find_hw_watchpoint(target_ulong addr, int *flag)
1489 {
1490 int n;
1491
1492 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_ACCESS);
1493 if (n >= 0) {
1494 *flag = BP_MEM_ACCESS;
1495 return n;
1496 }
1497
1498 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_WRITE);
1499 if (n >= 0) {
1500 *flag = BP_MEM_WRITE;
1501 return n;
1502 }
1503
1504 n = find_hw_breakpoint(addr, GDB_WATCHPOINT_READ);
1505 if (n >= 0) {
1506 *flag = BP_MEM_READ;
1507 return n;
1508 }
1509
1510 return -1;
1511 }
1512
1513 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1514 target_ulong len, int type)
1515 {
1516 if ((nb_hw_breakpoint + nb_hw_watchpoint) >= ARRAY_SIZE(hw_debug_points)) {
1517 return -ENOBUFS;
1518 }
1519
1520 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].addr = addr;
1521 hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint].type = type;
1522
1523 switch (type) {
1524 case GDB_BREAKPOINT_HW:
1525 if (nb_hw_breakpoint >= max_hw_breakpoint) {
1526 return -ENOBUFS;
1527 }
1528
1529 if (find_hw_breakpoint(addr, type) >= 0) {
1530 return -EEXIST;
1531 }
1532
1533 nb_hw_breakpoint++;
1534 break;
1535
1536 case GDB_WATCHPOINT_WRITE:
1537 case GDB_WATCHPOINT_READ:
1538 case GDB_WATCHPOINT_ACCESS:
1539 if (nb_hw_watchpoint >= max_hw_watchpoint) {
1540 return -ENOBUFS;
1541 }
1542
1543 if (find_hw_breakpoint(addr, type) >= 0) {
1544 return -EEXIST;
1545 }
1546
1547 nb_hw_watchpoint++;
1548 break;
1549
1550 default:
1551 return -ENOSYS;
1552 }
1553
1554 return 0;
1555 }
1556
1557 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1558 target_ulong len, int type)
1559 {
1560 int n;
1561
1562 n = find_hw_breakpoint(addr, type);
1563 if (n < 0) {
1564 return -ENOENT;
1565 }
1566
1567 switch (type) {
1568 case GDB_BREAKPOINT_HW:
1569 nb_hw_breakpoint--;
1570 break;
1571
1572 case GDB_WATCHPOINT_WRITE:
1573 case GDB_WATCHPOINT_READ:
1574 case GDB_WATCHPOINT_ACCESS:
1575 nb_hw_watchpoint--;
1576 break;
1577
1578 default:
1579 return -ENOSYS;
1580 }
1581 hw_debug_points[n] = hw_debug_points[nb_hw_breakpoint + nb_hw_watchpoint];
1582
1583 return 0;
1584 }
1585
1586 void kvm_arch_remove_all_hw_breakpoints(void)
1587 {
1588 nb_hw_breakpoint = nb_hw_watchpoint = 0;
1589 }
1590
1591 void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
1592 {
1593 int n;
1594
1595 /* Software Breakpoint updates */
1596 if (kvm_sw_breakpoints_active(cs)) {
1597 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1598 }
1599
1600 assert((nb_hw_breakpoint + nb_hw_watchpoint)
1601 <= ARRAY_SIZE(hw_debug_points));
1602 assert((nb_hw_breakpoint + nb_hw_watchpoint) <= ARRAY_SIZE(dbg->arch.bp));
1603
1604 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1605 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1606 memset(dbg->arch.bp, 0, sizeof(dbg->arch.bp));
1607 for (n = 0; n < nb_hw_breakpoint + nb_hw_watchpoint; n++) {
1608 switch (hw_debug_points[n].type) {
1609 case GDB_BREAKPOINT_HW:
1610 dbg->arch.bp[n].type = KVMPPC_DEBUG_BREAKPOINT;
1611 break;
1612 case GDB_WATCHPOINT_WRITE:
1613 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE;
1614 break;
1615 case GDB_WATCHPOINT_READ:
1616 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_READ;
1617 break;
1618 case GDB_WATCHPOINT_ACCESS:
1619 dbg->arch.bp[n].type = KVMPPC_DEBUG_WATCH_WRITE |
1620 KVMPPC_DEBUG_WATCH_READ;
1621 break;
1622 default:
1623 cpu_abort(cs, "Unsupported breakpoint type\n");
1624 }
1625 dbg->arch.bp[n].addr = hw_debug_points[n].addr;
1626 }
1627 }
1628 }
1629
1630 static int kvm_handle_hw_breakpoint(CPUState *cs,
1631 struct kvm_debug_exit_arch *arch_info)
1632 {
1633 int handle = 0;
1634 int n;
1635 int flag = 0;
1636
1637 if (nb_hw_breakpoint + nb_hw_watchpoint > 0) {
1638 if (arch_info->status & KVMPPC_DEBUG_BREAKPOINT) {
1639 n = find_hw_breakpoint(arch_info->address, GDB_BREAKPOINT_HW);
1640 if (n >= 0) {
1641 handle = 1;
1642 }
1643 } else if (arch_info->status & (KVMPPC_DEBUG_WATCH_READ |
1644 KVMPPC_DEBUG_WATCH_WRITE)) {
1645 n = find_hw_watchpoint(arch_info->address, &flag);
1646 if (n >= 0) {
1647 handle = 1;
1648 cs->watchpoint_hit = &hw_watchpoint;
1649 hw_watchpoint.vaddr = hw_debug_points[n].addr;
1650 hw_watchpoint.flags = flag;
1651 }
1652 }
1653 }
1654 return handle;
1655 }
1656
1657 static int kvm_handle_singlestep(void)
1658 {
1659 return 1;
1660 }
1661
1662 static int kvm_handle_sw_breakpoint(void)
1663 {
1664 return 1;
1665 }
1666
1667 static int kvm_handle_debug(PowerPCCPU *cpu, struct kvm_run *run)
1668 {
1669 CPUState *cs = CPU(cpu);
1670 CPUPPCState *env = &cpu->env;
1671 struct kvm_debug_exit_arch *arch_info = &run->debug.arch;
1672
1673 if (cs->singlestep_enabled) {
1674 return kvm_handle_singlestep();
1675 }
1676
1677 if (arch_info->status) {
1678 return kvm_handle_hw_breakpoint(cs, arch_info);
1679 }
1680
1681 if (kvm_find_sw_breakpoint(cs, arch_info->address)) {
1682 return kvm_handle_sw_breakpoint();
1683 }
1684
1685 /*
1686 * QEMU is not able to handle debug exception, so inject
1687 * program exception to guest;
1688 * Yes program exception NOT debug exception !!
1689 * When QEMU is using debug resources then debug exception must
1690 * be always set. To achieve this we set MSR_DE and also set
1691 * MSRP_DEP so guest cannot change MSR_DE.
1692 * When emulating debug resource for guest we want guest
1693 * to control MSR_DE (enable/disable debug interrupt on need).
1694 * Supporting both configurations are NOT possible.
1695 * So the result is that we cannot share debug resources
1696 * between QEMU and Guest on BOOKE architecture.
1697 * In the current design QEMU gets the priority over guest,
1698 * this means that if QEMU is using debug resources then guest
1699 * cannot use them;
1700 * For software breakpoint QEMU uses a privileged instruction;
1701 * So there cannot be any reason that we are here for guest
1702 * set debug exception, only possibility is guest executed a
1703 * privileged / illegal instruction and that's why we are
1704 * injecting a program interrupt.
1705 */
1706 cpu_synchronize_state(cs);
1707 /*
1708 * env->nip is PC, so increment this by 4 to use
1709 * ppc_cpu_do_interrupt(), which set srr0 = env->nip - 4.
1710 */
1711 env->nip += 4;
1712 cs->exception_index = POWERPC_EXCP_PROGRAM;
1713 env->error_code = POWERPC_EXCP_INVAL;
1714 ppc_cpu_do_interrupt(cs);
1715
1716 return 0;
1717 }
1718
1719 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
1720 {
1721 PowerPCCPU *cpu = POWERPC_CPU(cs);
1722 CPUPPCState *env = &cpu->env;
1723 int ret;
1724
1725 qemu_mutex_lock_iothread();
1726
1727 switch (run->exit_reason) {
1728 case KVM_EXIT_DCR:
1729 if (run->dcr.is_write) {
1730 trace_kvm_handle_dcr_write();
1731 ret = kvmppc_handle_dcr_write(env, run->dcr.dcrn, run->dcr.data);
1732 } else {
1733 trace_kvm_handle_dcr_read();
1734 ret = kvmppc_handle_dcr_read(env, run->dcr.dcrn, &run->dcr.data);
1735 }
1736 break;
1737 case KVM_EXIT_HLT:
1738 trace_kvm_handle_halt();
1739 ret = kvmppc_handle_halt(cpu);
1740 break;
1741 #if defined(TARGET_PPC64)
1742 case KVM_EXIT_PAPR_HCALL:
1743 trace_kvm_handle_papr_hcall();
1744 run->papr_hcall.ret = spapr_hypercall(cpu,
1745 run->papr_hcall.nr,
1746 run->papr_hcall.args);
1747 ret = 0;
1748 break;
1749 #endif
1750 case KVM_EXIT_EPR:
1751 trace_kvm_handle_epr();
1752 run->epr.epr = ldl_phys(cs->as, env->mpic_iack);
1753 ret = 0;
1754 break;
1755 case KVM_EXIT_WATCHDOG:
1756 trace_kvm_handle_watchdog_expiry();
1757 watchdog_perform_action();
1758 ret = 0;
1759 break;
1760
1761 case KVM_EXIT_DEBUG:
1762 trace_kvm_handle_debug_exception();
1763 if (kvm_handle_debug(cpu, run)) {
1764 ret = EXCP_DEBUG;
1765 break;
1766 }
1767 /* re-enter, this exception was guest-internal */
1768 ret = 0;
1769 break;
1770
1771 default:
1772 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1773 ret = -1;
1774 break;
1775 }
1776
1777 qemu_mutex_unlock_iothread();
1778 return ret;
1779 }
1780
1781 int kvmppc_or_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1782 {
1783 CPUState *cs = CPU(cpu);
1784 uint32_t bits = tsr_bits;
1785 struct kvm_one_reg reg = {
1786 .id = KVM_REG_PPC_OR_TSR,
1787 .addr = (uintptr_t) &bits,
1788 };
1789
1790 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1791 }
1792
1793 int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits)
1794 {
1795
1796 CPUState *cs = CPU(cpu);
1797 uint32_t bits = tsr_bits;
1798 struct kvm_one_reg reg = {
1799 .id = KVM_REG_PPC_CLEAR_TSR,
1800 .addr = (uintptr_t) &bits,
1801 };
1802
1803 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1804 }
1805
1806 int kvmppc_set_tcr(PowerPCCPU *cpu)
1807 {
1808 CPUState *cs = CPU(cpu);
1809 CPUPPCState *env = &cpu->env;
1810 uint32_t tcr = env->spr[SPR_BOOKE_TCR];
1811
1812 struct kvm_one_reg reg = {
1813 .id = KVM_REG_PPC_TCR,
1814 .addr = (uintptr_t) &tcr,
1815 };
1816
1817 return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
1818 }
1819
1820 int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu)
1821 {
1822 CPUState *cs = CPU(cpu);
1823 int ret;
1824
1825 if (!kvm_enabled()) {
1826 return -1;
1827 }
1828
1829 if (!cap_ppc_watchdog) {
1830 printf("warning: KVM does not support watchdog");
1831 return -1;
1832 }
1833
1834 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_BOOKE_WATCHDOG, 0);
1835 if (ret < 0) {
1836 fprintf(stderr, "%s: couldn't enable KVM_CAP_PPC_BOOKE_WATCHDOG: %s\n",
1837 __func__, strerror(-ret));
1838 return ret;
1839 }
1840
1841 return ret;
1842 }
1843
1844 static int read_cpuinfo(const char *field, char *value, int len)
1845 {
1846 FILE *f;
1847 int ret = -1;
1848 int field_len = strlen(field);
1849 char line[512];
1850
1851 f = fopen("/proc/cpuinfo", "r");
1852 if (!f) {
1853 return -1;
1854 }
1855
1856 do {
1857 if (!fgets(line, sizeof(line), f)) {
1858 break;
1859 }
1860 if (!strncmp(line, field, field_len)) {
1861 pstrcpy(value, len, line);
1862 ret = 0;
1863 break;
1864 }
1865 } while (*line);
1866
1867 fclose(f);
1868
1869 return ret;
1870 }
1871
1872 uint32_t kvmppc_get_tbfreq(void)
1873 {
1874 char line[512];
1875 char *ns;
1876 uint32_t retval = NANOSECONDS_PER_SECOND;
1877
1878 if (read_cpuinfo("timebase", line, sizeof(line))) {
1879 return retval;
1880 }
1881
1882 ns = strchr(line, ':');
1883 if (!ns) {
1884 return retval;
1885 }
1886
1887 ns++;
1888
1889 return atoi(ns);
1890 }
1891
1892 bool kvmppc_get_host_serial(char **value)
1893 {
1894 return g_file_get_contents("/proc/device-tree/system-id", value, NULL,
1895 NULL);
1896 }
1897
1898 bool kvmppc_get_host_model(char **value)
1899 {
1900 return g_file_get_contents("/proc/device-tree/model", value, NULL, NULL);
1901 }
1902
1903 /* Try to find a device tree node for a CPU with clock-frequency property */
1904 static int kvmppc_find_cpu_dt(char *buf, int buf_len)
1905 {
1906 struct dirent *dirp;
1907 DIR *dp;
1908
1909 dp = opendir(PROC_DEVTREE_CPU);
1910 if (!dp) {
1911 printf("Can't open directory " PROC_DEVTREE_CPU "\n");
1912 return -1;
1913 }
1914
1915 buf[0] = '\0';
1916 while ((dirp = readdir(dp)) != NULL) {
1917 FILE *f;
1918 snprintf(buf, buf_len, "%s%s/clock-frequency", PROC_DEVTREE_CPU,
1919 dirp->d_name);
1920 f = fopen(buf, "r");
1921 if (f) {
1922 snprintf(buf, buf_len, "%s%s", PROC_DEVTREE_CPU, dirp->d_name);
1923 fclose(f);
1924 break;
1925 }
1926 buf[0] = '\0';
1927 }
1928 closedir(dp);
1929 if (buf[0] == '\0') {
1930 printf("Unknown host!\n");
1931 return -1;
1932 }
1933
1934 return 0;
1935 }
1936
1937 static uint64_t kvmppc_read_int_dt(const char *filename)
1938 {
1939 union {
1940 uint32_t v32;
1941 uint64_t v64;
1942 } u;
1943 FILE *f;
1944 int len;
1945
1946 f = fopen(filename, "rb");
1947 if (!f) {
1948 return -1;
1949 }
1950
1951 len = fread(&u, 1, sizeof(u), f);
1952 fclose(f);
1953 switch (len) {
1954 case 4:
1955 /* property is a 32-bit quantity */
1956 return be32_to_cpu(u.v32);
1957 case 8:
1958 return be64_to_cpu(u.v64);
1959 }
1960
1961 return 0;
1962 }
1963
1964 /*
1965 * Read a CPU node property from the host device tree that's a single
1966 * integer (32-bit or 64-bit). Returns 0 if anything goes wrong
1967 * (can't find or open the property, or doesn't understand the format)
1968 */
1969 static uint64_t kvmppc_read_int_cpu_dt(const char *propname)
1970 {
1971 char buf[PATH_MAX], *tmp;
1972 uint64_t val;
1973
1974 if (kvmppc_find_cpu_dt(buf, sizeof(buf))) {
1975 return -1;
1976 }
1977
1978 tmp = g_strdup_printf("%s/%s", buf, propname);
1979 val = kvmppc_read_int_dt(tmp);
1980 g_free(tmp);
1981
1982 return val;
1983 }
1984
1985 uint64_t kvmppc_get_clockfreq(void)
1986 {
1987 return kvmppc_read_int_cpu_dt("clock-frequency");
1988 }
1989
1990 static int kvmppc_get_dec_bits(void)
1991 {
1992 int nr_bits = kvmppc_read_int_cpu_dt("ibm,dec-bits");
1993
1994 if (nr_bits > 0) {
1995 return nr_bits;
1996 }
1997 return 0;
1998 }
1999
2000 static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
2001 {
2002 CPUState *cs = env_cpu(env);
2003
2004 if (kvm_vm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
2005 !kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
2006 return 0;
2007 }
2008
2009 return 1;
2010 }
2011
2012 int kvmppc_get_hasidle(CPUPPCState *env)
2013 {
2014 struct kvm_ppc_pvinfo pvinfo;
2015
2016 if (!kvmppc_get_pvinfo(env, &pvinfo) &&
2017 (pvinfo.flags & KVM_PPC_PVINFO_FLAGS_EV_IDLE)) {
2018 return 1;
2019 }
2020
2021 return 0;
2022 }
2023
2024 int kvmppc_get_hypercall(CPUPPCState *env, uint8_t *buf, int buf_len)
2025 {
2026 uint32_t *hc = (uint32_t *)buf;
2027 struct kvm_ppc_pvinfo pvinfo;
2028
2029 if (!kvmppc_get_pvinfo(env, &pvinfo)) {
2030 memcpy(buf, pvinfo.hcall, buf_len);
2031 return 0;
2032 }
2033
2034 /*
2035 * Fallback to always fail hypercalls regardless of endianness:
2036 *
2037 * tdi 0,r0,72 (becomes b .+8 in wrong endian, nop in good endian)
2038 * li r3, -1
2039 * b .+8 (becomes nop in wrong endian)
2040 * bswap32(li r3, -1)
2041 */
2042
2043 hc[0] = cpu_to_be32(0x08000048);
2044 hc[1] = cpu_to_be32(0x3860ffff);
2045 hc[2] = cpu_to_be32(0x48000008);
2046 hc[3] = cpu_to_be32(bswap32(0x3860ffff));
2047
2048 return 1;
2049 }
2050
2051 static inline int kvmppc_enable_hcall(KVMState *s, target_ulong hcall)
2052 {
2053 return kvm_vm_enable_cap(s, KVM_CAP_PPC_ENABLE_HCALL, 0, hcall, 1);
2054 }
2055
2056 void kvmppc_enable_logical_ci_hcalls(void)
2057 {
2058 /*
2059 * FIXME: it would be nice if we could detect the cases where
2060 * we're using a device which requires the in kernel
2061 * implementation of these hcalls, but the kernel lacks them and
2062 * produce a warning.
2063 */
2064 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_LOAD);
2065 kvmppc_enable_hcall(kvm_state, H_LOGICAL_CI_STORE);
2066 }
2067
2068 void kvmppc_enable_set_mode_hcall(void)
2069 {
2070 kvmppc_enable_hcall(kvm_state, H_SET_MODE);
2071 }
2072
2073 void kvmppc_enable_clear_ref_mod_hcalls(void)
2074 {
2075 kvmppc_enable_hcall(kvm_state, H_CLEAR_REF);
2076 kvmppc_enable_hcall(kvm_state, H_CLEAR_MOD);
2077 }
2078
2079 void kvmppc_enable_h_page_init(void)
2080 {
2081 kvmppc_enable_hcall(kvm_state, H_PAGE_INIT);
2082 }
2083
2084 void kvmppc_set_papr(PowerPCCPU *cpu)
2085 {
2086 CPUState *cs = CPU(cpu);
2087 int ret;
2088
2089 if (!kvm_enabled()) {
2090 return;
2091 }
2092
2093 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_PAPR, 0);
2094 if (ret) {
2095 error_report("This vCPU type or KVM version does not support PAPR");
2096 exit(1);
2097 }
2098
2099 /*
2100 * Update the capability flag so we sync the right information
2101 * with kvm
2102 */
2103 cap_papr = 1;
2104 }
2105
2106 int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
2107 {
2108 return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
2109 }
2110
2111 void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
2112 {
2113 CPUState *cs = CPU(cpu);
2114 int ret;
2115
2116 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_PPC_EPR, 0, mpic_proxy);
2117 if (ret && mpic_proxy) {
2118 error_report("This KVM version does not support EPR");
2119 exit(1);
2120 }
2121 }
2122
2123 int kvmppc_smt_threads(void)
2124 {
2125 return cap_ppc_smt ? cap_ppc_smt : 1;
2126 }
2127
2128 int kvmppc_set_smt_threads(int smt)
2129 {
2130 int ret;
2131
2132 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_SMT, 0, smt, 0);
2133 if (!ret) {
2134 cap_ppc_smt = smt;
2135 }
2136 return ret;
2137 }
2138
2139 void kvmppc_hint_smt_possible(Error **errp)
2140 {
2141 int i;
2142 GString *g;
2143 char *s;
2144
2145 assert(kvm_enabled());
2146 if (cap_ppc_smt_possible) {
2147 g = g_string_new("Available VSMT modes:");
2148 for (i = 63; i >= 0; i--) {
2149 if ((1UL << i) & cap_ppc_smt_possible) {
2150 g_string_append_printf(g, " %lu", (1UL << i));
2151 }
2152 }
2153 s = g_string_free(g, false);
2154 error_append_hint(errp, "%s.\n", s);
2155 g_free(s);
2156 } else {
2157 error_append_hint(errp,
2158 "This KVM seems to be too old to support VSMT.\n");
2159 }
2160 }
2161
2162
2163 #ifdef TARGET_PPC64
2164 uint64_t kvmppc_rma_size(uint64_t current_size, unsigned int hash_shift)
2165 {
2166 struct kvm_ppc_smmu_info info;
2167 long rampagesize, best_page_shift;
2168 int i;
2169
2170 /*
2171 * Find the largest hardware supported page size that's less than
2172 * or equal to the (logical) backing page size of guest RAM
2173 */
2174 kvm_get_smmu_info(&info, &error_fatal);
2175 rampagesize = qemu_minrampagesize();
2176 best_page_shift = 0;
2177
2178 for (i = 0; i < KVM_PPC_PAGE_SIZES_MAX_SZ; i++) {
2179 struct kvm_ppc_one_seg_page_size *sps = &info.sps[i];
2180
2181 if (!sps->page_shift) {
2182 continue;
2183 }
2184
2185 if ((sps->page_shift > best_page_shift)
2186 && ((1UL << sps->page_shift) <= rampagesize)) {
2187 best_page_shift = sps->page_shift;
2188 }
2189 }
2190
2191 return MIN(current_size,
2192 1ULL << (best_page_shift + hash_shift - 7));
2193 }
2194 #endif
2195
2196 bool kvmppc_spapr_use_multitce(void)
2197 {
2198 return cap_spapr_multitce;
2199 }
2200
2201 int kvmppc_spapr_enable_inkernel_multitce(void)
2202 {
2203 int ret;
2204
2205 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2206 H_PUT_TCE_INDIRECT, 1);
2207 if (!ret) {
2208 ret = kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_ENABLE_HCALL, 0,
2209 H_STUFF_TCE, 1);
2210 }
2211
2212 return ret;
2213 }
2214
2215 void *kvmppc_create_spapr_tce(uint32_t liobn, uint32_t page_shift,
2216 uint64_t bus_offset, uint32_t nb_table,
2217 int *pfd, bool need_vfio)
2218 {
2219 long len;
2220 int fd;
2221 void *table;
2222
2223 /*
2224 * Must set fd to -1 so we don't try to munmap when called for
2225 * destroying the table, which the upper layers -will- do
2226 */
2227 *pfd = -1;
2228 if (!cap_spapr_tce || (need_vfio && !cap_spapr_vfio)) {
2229 return NULL;
2230 }
2231
2232 if (cap_spapr_tce_64) {
2233 struct kvm_create_spapr_tce_64 args = {
2234 .liobn = liobn,
2235 .page_shift = page_shift,
2236 .offset = bus_offset >> page_shift,
2237 .size = nb_table,
2238 .flags = 0
2239 };
2240 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE_64, &args);
2241 if (fd < 0) {
2242 fprintf(stderr,
2243 "KVM: Failed to create TCE64 table for liobn 0x%x\n",
2244 liobn);
2245 return NULL;
2246 }
2247 } else if (cap_spapr_tce) {
2248 uint64_t window_size = (uint64_t) nb_table << page_shift;
2249 struct kvm_create_spapr_tce args = {
2250 .liobn = liobn,
2251 .window_size = window_size,
2252 };
2253 if ((window_size != args.window_size) || bus_offset) {
2254 return NULL;
2255 }
2256 fd = kvm_vm_ioctl(kvm_state, KVM_CREATE_SPAPR_TCE, &args);
2257 if (fd < 0) {
2258 fprintf(stderr, "KVM: Failed to create TCE table for liobn 0x%x\n",
2259 liobn);
2260 return NULL;
2261 }
2262 } else {
2263 return NULL;
2264 }
2265
2266 len = nb_table * sizeof(uint64_t);
2267 /* FIXME: round this up to page size */
2268
2269 table = mmap(NULL, len, PROT_READ | PROT_WRITE, MAP_SHARED, fd, 0);
2270 if (table == MAP_FAILED) {
2271 fprintf(stderr, "KVM: Failed to map TCE table for liobn 0x%x\n",
2272 liobn);
2273 close(fd);
2274 return NULL;
2275 }
2276
2277 *pfd = fd;
2278 return table;
2279 }
2280
2281 int kvmppc_remove_spapr_tce(void *table, int fd, uint32_t nb_table)
2282 {
2283 long len;
2284
2285 if (fd < 0) {
2286 return -1;
2287 }
2288
2289 len = nb_table * sizeof(uint64_t);
2290 if ((munmap(table, len) < 0) ||
2291 (close(fd) < 0)) {
2292 fprintf(stderr, "KVM: Unexpected error removing TCE table: %s",
2293 strerror(errno));
2294 /* Leak the table */
2295 }
2296
2297 return 0;
2298 }
2299
2300 int kvmppc_reset_htab(int shift_hint)
2301 {
2302 uint32_t shift = shift_hint;
2303
2304 if (!kvm_enabled()) {
2305 /* Full emulation, tell caller to allocate htab itself */
2306 return 0;
2307 }
2308 if (kvm_vm_check_extension(kvm_state, KVM_CAP_PPC_ALLOC_HTAB)) {
2309 int ret;
2310 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_ALLOCATE_HTAB, &shift);
2311 if (ret == -ENOTTY) {
2312 /*
2313 * At least some versions of PR KVM advertise the
2314 * capability, but don't implement the ioctl(). Oops.
2315 * Return 0 so that we allocate the htab in qemu, as is
2316 * correct for PR.
2317 */
2318 return 0;
2319 } else if (ret < 0) {
2320 return ret;
2321 }
2322 return shift;
2323 }
2324
2325 /*
2326 * We have a kernel that predates the htab reset calls. For PR
2327 * KVM, we need to allocate the htab ourselves, for an HV KVM of
2328 * this era, it has allocated a 16MB fixed size hash table
2329 * already.
2330 */
2331 if (kvmppc_is_pr(kvm_state)) {
2332 /* PR - tell caller to allocate htab */
2333 return 0;
2334 } else {
2335 /* HV - assume 16MB kernel allocated htab */
2336 return 24;
2337 }
2338 }
2339
2340 static inline uint32_t mfpvr(void)
2341 {
2342 uint32_t pvr;
2343
2344 asm ("mfpvr %0"
2345 : "=r"(pvr));
2346 return pvr;
2347 }
2348
2349 static void alter_insns(uint64_t *word, uint64_t flags, bool on)
2350 {
2351 if (on) {
2352 *word |= flags;
2353 } else {
2354 *word &= ~flags;
2355 }
2356 }
2357
2358 static void kvmppc_host_cpu_class_init(ObjectClass *oc, void *data)
2359 {
2360 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
2361 uint32_t dcache_size = kvmppc_read_int_cpu_dt("d-cache-size");
2362 uint32_t icache_size = kvmppc_read_int_cpu_dt("i-cache-size");
2363
2364 /* Now fix up the class with information we can query from the host */
2365 pcc->pvr = mfpvr();
2366
2367 alter_insns(&pcc->insns_flags, PPC_ALTIVEC,
2368 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_ALTIVEC);
2369 alter_insns(&pcc->insns_flags2, PPC2_VSX,
2370 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_VSX);
2371 alter_insns(&pcc->insns_flags2, PPC2_DFP,
2372 qemu_getauxval(AT_HWCAP) & PPC_FEATURE_HAS_DFP);
2373
2374 if (dcache_size != -1) {
2375 pcc->l1_dcache_size = dcache_size;
2376 }
2377
2378 if (icache_size != -1) {
2379 pcc->l1_icache_size = icache_size;
2380 }
2381
2382 #if defined(TARGET_PPC64)
2383 pcc->radix_page_info = kvm_get_radix_page_info();
2384
2385 if ((pcc->pvr & 0xffffff00) == CPU_POWERPC_POWER9_DD1) {
2386 /*
2387 * POWER9 DD1 has some bugs which make it not really ISA 3.00
2388 * compliant. More importantly, advertising ISA 3.00
2389 * architected mode may prevent guests from activating
2390 * necessary DD1 workarounds.
2391 */
2392 pcc->pcr_supported &= ~(PCR_COMPAT_3_00 | PCR_COMPAT_2_07
2393 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05);
2394 }
2395 #endif /* defined(TARGET_PPC64) */
2396 }
2397
2398 bool kvmppc_has_cap_epr(void)
2399 {
2400 return cap_epr;
2401 }
2402
2403 bool kvmppc_has_cap_fixup_hcalls(void)
2404 {
2405 return cap_fixup_hcalls;
2406 }
2407
2408 bool kvmppc_has_cap_htm(void)
2409 {
2410 return cap_htm;
2411 }
2412
2413 bool kvmppc_has_cap_mmu_radix(void)
2414 {
2415 return cap_mmu_radix;
2416 }
2417
2418 bool kvmppc_has_cap_mmu_hash_v3(void)
2419 {
2420 return cap_mmu_hash_v3;
2421 }
2422
2423 static bool kvmppc_power8_host(void)
2424 {
2425 bool ret = false;
2426 #ifdef TARGET_PPC64
2427 {
2428 uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
2429 ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
2430 (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
2431 (base_pvr == CPU_POWERPC_POWER8_BASE);
2432 }
2433 #endif /* TARGET_PPC64 */
2434 return ret;
2435 }
2436
2437 static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
2438 {
2439 bool l1d_thread_priv_req = !kvmppc_power8_host();
2440
2441 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
2442 return 2;
2443 } else if ((!l1d_thread_priv_req ||
2444 c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
2445 (c.character & c.character_mask
2446 & (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
2447 return 1;
2448 }
2449
2450 return 0;
2451 }
2452
2453 static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
2454 {
2455 if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_BNDS_CHK_SPEC_BAR) {
2456 return 2;
2457 } else if (c.character & c.character_mask & H_CPU_CHAR_SPEC_BAR_ORI31) {
2458 return 1;
2459 }
2460
2461 return 0;
2462 }
2463
2464 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
2465 {
2466 if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
2467 (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
2468 (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
2469 return SPAPR_CAP_FIXED_NA;
2470 } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
2471 return SPAPR_CAP_WORKAROUND;
2472 } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
2473 return SPAPR_CAP_FIXED_CCD;
2474 } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
2475 return SPAPR_CAP_FIXED_IBS;
2476 }
2477
2478 return 0;
2479 }
2480
2481 static int parse_cap_ppc_count_cache_flush_assist(struct kvm_ppc_cpu_char c)
2482 {
2483 if (c.character & c.character_mask & H_CPU_CHAR_BCCTR_FLUSH_ASSIST) {
2484 return 1;
2485 }
2486 return 0;
2487 }
2488
2489 bool kvmppc_has_cap_xive(void)
2490 {
2491 return cap_xive;
2492 }
2493
2494 static void kvmppc_get_cpu_characteristics(KVMState *s)
2495 {
2496 struct kvm_ppc_cpu_char c;
2497 int ret;
2498
2499 /* Assume broken */
2500 cap_ppc_safe_cache = 0;
2501 cap_ppc_safe_bounds_check = 0;
2502 cap_ppc_safe_indirect_branch = 0;
2503
2504 ret = kvm_vm_check_extension(s, KVM_CAP_PPC_GET_CPU_CHAR);
2505 if (!ret) {
2506 return;
2507 }
2508 ret = kvm_vm_ioctl(s, KVM_PPC_GET_CPU_CHAR, &c);
2509 if (ret < 0) {
2510 return;
2511 }
2512
2513 cap_ppc_safe_cache = parse_cap_ppc_safe_cache(c);
2514 cap_ppc_safe_bounds_check = parse_cap_ppc_safe_bounds_check(c);
2515 cap_ppc_safe_indirect_branch = parse_cap_ppc_safe_indirect_branch(c);
2516 cap_ppc_count_cache_flush_assist =
2517 parse_cap_ppc_count_cache_flush_assist(c);
2518 }
2519
2520 int kvmppc_get_cap_safe_cache(void)
2521 {
2522 return cap_ppc_safe_cache;
2523 }
2524
2525 int kvmppc_get_cap_safe_bounds_check(void)
2526 {
2527 return cap_ppc_safe_bounds_check;
2528 }
2529
2530 int kvmppc_get_cap_safe_indirect_branch(void)
2531 {
2532 return cap_ppc_safe_indirect_branch;
2533 }
2534
2535 int kvmppc_get_cap_count_cache_flush_assist(void)
2536 {
2537 return cap_ppc_count_cache_flush_assist;
2538 }
2539
2540 bool kvmppc_has_cap_nested_kvm_hv(void)
2541 {
2542 return !!cap_ppc_nested_kvm_hv;
2543 }
2544
2545 int kvmppc_set_cap_nested_kvm_hv(int enable)
2546 {
2547 return kvm_vm_enable_cap(kvm_state, KVM_CAP_PPC_NESTED_HV, 0, enable);
2548 }
2549
2550 bool kvmppc_has_cap_spapr_vfio(void)
2551 {
2552 return cap_spapr_vfio;
2553 }
2554
2555 int kvmppc_get_cap_large_decr(void)
2556 {
2557 return cap_large_decr;
2558 }
2559
2560 int kvmppc_enable_cap_large_decr(PowerPCCPU *cpu, int enable)
2561 {
2562 CPUState *cs = CPU(cpu);
2563 uint64_t lpcr;
2564
2565 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2566 /* Do we need to modify the LPCR? */
2567 if (!!(lpcr & LPCR_LD) != !!enable) {
2568 if (enable) {
2569 lpcr |= LPCR_LD;
2570 } else {
2571 lpcr &= ~LPCR_LD;
2572 }
2573 kvm_set_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2574 kvm_get_one_reg(cs, KVM_REG_PPC_LPCR_64, &lpcr);
2575
2576 if (!!(lpcr & LPCR_LD) != !!enable) {
2577 return -1;
2578 }
2579 }
2580
2581 return 0;
2582 }
2583
2584 PowerPCCPUClass *kvm_ppc_get_host_cpu_class(void)
2585 {
2586 uint32_t host_pvr = mfpvr();
2587 PowerPCCPUClass *pvr_pcc;
2588
2589 pvr_pcc = ppc_cpu_class_by_pvr(host_pvr);
2590 if (pvr_pcc == NULL) {
2591 pvr_pcc = ppc_cpu_class_by_pvr_mask(host_pvr);
2592 }
2593
2594 return pvr_pcc;
2595 }
2596
2597 static int kvm_ppc_register_host_cpu_type(MachineState *ms)
2598 {
2599 TypeInfo type_info = {
2600 .name = TYPE_HOST_POWERPC_CPU,
2601 .class_init = kvmppc_host_cpu_class_init,
2602 };
2603 MachineClass *mc = MACHINE_GET_CLASS(ms);
2604 PowerPCCPUClass *pvr_pcc;
2605 ObjectClass *oc;
2606 DeviceClass *dc;
2607 int i;
2608
2609 pvr_pcc = kvm_ppc_get_host_cpu_class();
2610 if (pvr_pcc == NULL) {
2611 return -1;
2612 }
2613 type_info.parent = object_class_get_name(OBJECT_CLASS(pvr_pcc));
2614 type_register(&type_info);
2615 if (object_dynamic_cast(OBJECT(ms), TYPE_SPAPR_MACHINE)) {
2616 /* override TCG default cpu type with 'host' cpu model */
2617 mc->default_cpu_type = TYPE_HOST_POWERPC_CPU;
2618 }
2619
2620 oc = object_class_by_name(type_info.name);
2621 g_assert(oc);
2622
2623 /*
2624 * Update generic CPU family class alias (e.g. on a POWER8NVL host,
2625 * we want "POWER8" to be a "family" alias that points to the current
2626 * host CPU type, too)
2627 */
2628 dc = DEVICE_CLASS(ppc_cpu_get_family_class(pvr_pcc));
2629 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
2630 if (strcasecmp(ppc_cpu_aliases[i].alias, dc->desc) == 0) {
2631 char *suffix;
2632
2633 ppc_cpu_aliases[i].model = g_strdup(object_class_get_name(oc));
2634 suffix = strstr(ppc_cpu_aliases[i].model, POWERPC_CPU_TYPE_SUFFIX);
2635 if (suffix) {
2636 *suffix = 0;
2637 }
2638 break;
2639 }
2640 }
2641
2642 return 0;
2643 }
2644
2645 int kvmppc_define_rtas_kernel_token(uint32_t token, const char *function)
2646 {
2647 struct kvm_rtas_token_args args = {
2648 .token = token,
2649 };
2650
2651 if (!kvm_check_extension(kvm_state, KVM_CAP_PPC_RTAS)) {
2652 return -ENOENT;
2653 }
2654
2655 strncpy(args.name, function, sizeof(args.name) - 1);
2656
2657 return kvm_vm_ioctl(kvm_state, KVM_PPC_RTAS_DEFINE_TOKEN, &args);
2658 }
2659
2660 int kvmppc_get_htab_fd(bool write, uint64_t index, Error **errp)
2661 {
2662 struct kvm_get_htab_fd s = {
2663 .flags = write ? KVM_GET_HTAB_WRITE : 0,
2664 .start_index = index,
2665 };
2666 int ret;
2667
2668 if (!cap_htab_fd) {
2669 error_setg(errp, "KVM version doesn't support %s the HPT",
2670 write ? "writing" : "reading");
2671 return -ENOTSUP;
2672 }
2673
2674 ret = kvm_vm_ioctl(kvm_state, KVM_PPC_GET_HTAB_FD, &s);
2675 if (ret < 0) {
2676 error_setg(errp, "Unable to open fd for %s HPT %s KVM: %s",
2677 write ? "writing" : "reading", write ? "to" : "from",
2678 strerror(errno));
2679 return -errno;
2680 }
2681
2682 return ret;
2683 }
2684
2685 int kvmppc_save_htab(QEMUFile *f, int fd, size_t bufsize, int64_t max_ns)
2686 {
2687 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
2688 uint8_t buf[bufsize];
2689 ssize_t rc;
2690
2691 do {
2692 rc = read(fd, buf, bufsize);
2693 if (rc < 0) {
2694 fprintf(stderr, "Error reading data from KVM HTAB fd: %s\n",
2695 strerror(errno));
2696 return rc;
2697 } else if (rc) {
2698 uint8_t *buffer = buf;
2699 ssize_t n = rc;
2700 while (n) {
2701 struct kvm_get_htab_header *head =
2702 (struct kvm_get_htab_header *) buffer;
2703 size_t chunksize = sizeof(*head) +
2704 HASH_PTE_SIZE_64 * head->n_valid;
2705
2706 qemu_put_be32(f, head->index);
2707 qemu_put_be16(f, head->n_valid);
2708 qemu_put_be16(f, head->n_invalid);
2709 qemu_put_buffer(f, (void *)(head + 1),
2710 HASH_PTE_SIZE_64 * head->n_valid);
2711
2712 buffer += chunksize;
2713 n -= chunksize;
2714 }
2715 }
2716 } while ((rc != 0)
2717 && ((max_ns < 0) ||
2718 ((qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) < max_ns)));
2719
2720 return (rc == 0) ? 1 : 0;
2721 }
2722
2723 int kvmppc_load_htab_chunk(QEMUFile *f, int fd, uint32_t index,
2724 uint16_t n_valid, uint16_t n_invalid)
2725 {
2726 struct kvm_get_htab_header *buf;
2727 size_t chunksize = sizeof(*buf) + n_valid * HASH_PTE_SIZE_64;
2728 ssize_t rc;
2729
2730 buf = alloca(chunksize);
2731 buf->index = index;
2732 buf->n_valid = n_valid;
2733 buf->n_invalid = n_invalid;
2734
2735 qemu_get_buffer(f, (void *)(buf + 1), HASH_PTE_SIZE_64 * n_valid);
2736
2737 rc = write(fd, buf, chunksize);
2738 if (rc < 0) {
2739 fprintf(stderr, "Error writing KVM hash table: %s\n",
2740 strerror(errno));
2741 return rc;
2742 }
2743 if (rc != chunksize) {
2744 /* We should never get a short write on a single chunk */
2745 fprintf(stderr, "Short write, restoring KVM hash table\n");
2746 return -1;
2747 }
2748 return 0;
2749 }
2750
2751 bool kvm_arch_stop_on_emulation_error(CPUState *cpu)
2752 {
2753 return true;
2754 }
2755
2756 void kvm_arch_init_irq_routing(KVMState *s)
2757 {
2758 }
2759
2760 void kvmppc_read_hptes(ppc_hash_pte64_t *hptes, hwaddr ptex, int n)
2761 {
2762 int fd, rc;
2763 int i;
2764
2765 fd = kvmppc_get_htab_fd(false, ptex, &error_abort);
2766
2767 i = 0;
2768 while (i < n) {
2769 struct kvm_get_htab_header *hdr;
2770 int m = n < HPTES_PER_GROUP ? n : HPTES_PER_GROUP;
2771 char buf[sizeof(*hdr) + m * HASH_PTE_SIZE_64];
2772
2773 rc = read(fd, buf, sizeof(buf));
2774 if (rc < 0) {
2775 hw_error("kvmppc_read_hptes: Unable to read HPTEs");
2776 }
2777
2778 hdr = (struct kvm_get_htab_header *)buf;
2779 while ((i < n) && ((char *)hdr < (buf + rc))) {
2780 int invalid = hdr->n_invalid, valid = hdr->n_valid;
2781
2782 if (hdr->index != (ptex + i)) {
2783 hw_error("kvmppc_read_hptes: Unexpected HPTE index %"PRIu32
2784 " != (%"HWADDR_PRIu" + %d", hdr->index, ptex, i);
2785 }
2786
2787 if (n - i < valid) {
2788 valid = n - i;
2789 }
2790 memcpy(hptes + i, hdr + 1, HASH_PTE_SIZE_64 * valid);
2791 i += valid;
2792
2793 if ((n - i) < invalid) {
2794 invalid = n - i;
2795 }
2796 memset(hptes + i, 0, invalid * HASH_PTE_SIZE_64);
2797 i += invalid;
2798
2799 hdr = (struct kvm_get_htab_header *)
2800 ((char *)(hdr + 1) + HASH_PTE_SIZE_64 * hdr->n_valid);
2801 }
2802 }
2803
2804 close(fd);
2805 }
2806
2807 void kvmppc_write_hpte(hwaddr ptex, uint64_t pte0, uint64_t pte1)
2808 {
2809 int fd, rc;
2810 struct {
2811 struct kvm_get_htab_header hdr;
2812 uint64_t pte0;
2813 uint64_t pte1;
2814 } buf;
2815
2816 fd = kvmppc_get_htab_fd(true, 0 /* Ignored */, &error_abort);
2817
2818 buf.hdr.n_valid = 1;
2819 buf.hdr.n_invalid = 0;
2820 buf.hdr.index = ptex;
2821 buf.pte0 = cpu_to_be64(pte0);
2822 buf.pte1 = cpu_to_be64(pte1);
2823
2824 rc = write(fd, &buf, sizeof(buf));
2825 if (rc != sizeof(buf)) {
2826 hw_error("kvmppc_write_hpte: Unable to update KVM HPT");
2827 }
2828 close(fd);
2829 }
2830
2831 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
2832 uint64_t address, uint32_t data, PCIDevice *dev)
2833 {
2834 return 0;
2835 }
2836
2837 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
2838 int vector, PCIDevice *dev)
2839 {
2840 return 0;
2841 }
2842
2843 int kvm_arch_release_virq_post(int virq)
2844 {
2845 return 0;
2846 }
2847
2848 int kvm_arch_msi_data_to_gsi(uint32_t data)
2849 {
2850 return data & 0xffff;
2851 }
2852
2853 int kvmppc_enable_hwrng(void)
2854 {
2855 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_PPC_HWRNG)) {
2856 return -1;
2857 }
2858
2859 return kvmppc_enable_hcall(kvm_state, H_RANDOM);
2860 }
2861
2862 void kvmppc_check_papr_resize_hpt(Error **errp)
2863 {
2864 if (!kvm_enabled()) {
2865 return; /* No KVM, we're good */
2866 }
2867
2868 if (cap_resize_hpt) {
2869 return; /* Kernel has explicit support, we're good */
2870 }
2871
2872 /* Otherwise fallback on looking for PR KVM */
2873 if (kvmppc_is_pr(kvm_state)) {
2874 return;
2875 }
2876
2877 error_setg(errp,
2878 "Hash page table resizing not available with this KVM version");
2879 }
2880
2881 int kvmppc_resize_hpt_prepare(PowerPCCPU *cpu, target_ulong flags, int shift)
2882 {
2883 CPUState *cs = CPU(cpu);
2884 struct kvm_ppc_resize_hpt rhpt = {
2885 .flags = flags,
2886 .shift = shift,
2887 };
2888
2889 if (!cap_resize_hpt) {
2890 return -ENOSYS;
2891 }
2892
2893 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_PREPARE, &rhpt);
2894 }
2895
2896 int kvmppc_resize_hpt_commit(PowerPCCPU *cpu, target_ulong flags, int shift)
2897 {
2898 CPUState *cs = CPU(cpu);
2899 struct kvm_ppc_resize_hpt rhpt = {
2900 .flags = flags,
2901 .shift = shift,
2902 };
2903
2904 if (!cap_resize_hpt) {
2905 return -ENOSYS;
2906 }
2907
2908 return kvm_vm_ioctl(cs->kvm_state, KVM_PPC_RESIZE_HPT_COMMIT, &rhpt);
2909 }
2910
2911 /*
2912 * This is a helper function to detect a post migration scenario
2913 * in which a guest, running as KVM-HV, freezes in cpu_post_load because
2914 * the guest kernel can't handle a PVR value other than the actual host
2915 * PVR in KVM_SET_SREGS, even if pvr_match() returns true.
2916 *
2917 * If we don't have cap_ppc_pvr_compat and we're not running in PR
2918 * (so, we're HV), return true. The workaround itself is done in
2919 * cpu_post_load.
2920 *
2921 * The order here is important: we'll only check for KVM PR as a
2922 * fallback if the guest kernel can't handle the situation itself.
2923 * We need to avoid as much as possible querying the running KVM type
2924 * in QEMU level.
2925 */
2926 bool kvmppc_pvr_workaround_required(PowerPCCPU *cpu)
2927 {
2928 CPUState *cs = CPU(cpu);
2929
2930 if (!kvm_enabled()) {
2931 return false;
2932 }
2933
2934 if (cap_ppc_pvr_compat) {
2935 return false;
2936 }
2937
2938 return !kvmppc_is_pr(cs->kvm_state);
2939 }
2940
2941 void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online)
2942 {
2943 CPUState *cs = CPU(cpu);
2944
2945 if (kvm_enabled()) {
2946 kvm_set_one_reg(cs, KVM_REG_PPC_ONLINE, &online);
2947 }
2948 }
2949
2950 void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset)
2951 {
2952 CPUState *cs = CPU(cpu);
2953
2954 if (kvm_enabled()) {
2955 kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset);
2956 }
2957 }
armbru's QEMU hackery