target/ppc/misc_helper.c

   1 /*
   2  * Miscellaneous PowerPC emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/exec-all.h"
  23 #include "exec/helper-proto.h"
  24 #include "qemu/error-report.h"
  25 #include "qemu/main-loop.h"
  26
  27 #include "helper_regs.h"
  28
  29 /*****************************************************************************/
  30 /* SPR accesses */
  31 void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  32 {
  33     qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  34              env->spr[sprn]);
  35 }
  36
  37 void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  38 {
  39     qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  40              env->spr[sprn]);
  41 }
  42
  43 #ifdef TARGET_PPC64
  44 static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
  45                                uint32_t sprn, uint32_t cause,
  46                                uintptr_t raddr)
  47 {
  48     qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
  49
  50     env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
  51     cause &= FSCR_IC_MASK;
  52     env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
  53
  54     raise_exception_err_ra(env, POWERPC_EXCP_FU, 0, raddr);
  55 }
  56 #endif
  57
  58 void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
  59                                 uint32_t sprn, uint32_t cause)
  60 {
  61 #ifdef TARGET_PPC64
  62     if (env->spr[SPR_FSCR] & (1ULL << bit)) {
  63         /* Facility is enabled, continue */
  64         return;
  65     }
  66     raise_fu_exception(env, bit, sprn, cause, GETPC());
  67 #endif
  68 }
  69
  70 void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
  71                                uint32_t sprn, uint32_t cause)
  72 {
  73 #ifdef TARGET_PPC64
  74     if (env->msr & (1ULL << bit)) {
  75         /* Facility is enabled, continue */
  76         return;
  77     }
  78     raise_fu_exception(env, bit, sprn, cause, GETPC());
  79 #endif
  80 }
  81
  82 #if !defined(CONFIG_USER_ONLY)
  83
  84 void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  85 {
  86     if (env->spr[SPR_SDR1] != val) {
  87         ppc_store_sdr1(env, val);
  88         tlb_flush(env_cpu(env));
  89     }
  90 }
  91
  92 #if defined(TARGET_PPC64)
  93 void helper_store_ptcr(CPUPPCState *env, target_ulong val)
  94 {
  95     if (env->spr[SPR_PTCR] != val) {
  96         ppc_store_ptcr(env, val);
  97         tlb_flush(env_cpu(env));
  98     }
  99 }
 100
 101 void helper_store_pcr(CPUPPCState *env, target_ulong value)
 102 {
 103     PowerPCCPU *cpu = env_archcpu(env);
 104     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 105
 106     env->spr[SPR_PCR] = value & pcc->pcr_mask;
 107 }
 108 #endif /* defined(TARGET_PPC64) */
 109
 110 void helper_store_pidr(CPUPPCState *env, target_ulong val)
 111 {
 112     env->spr[SPR_BOOKS_PID] = val;
 113     tlb_flush(env_cpu(env));
 114 }
 115
 116 void helper_store_lpidr(CPUPPCState *env, target_ulong val)
 117 {
 118     env->spr[SPR_LPIDR] = val;
 119
 120     /*
 121      * We need to flush the TLB on LPID changes as we only tag HV vs
 122      * guest in TCG TLB. Also the quadrants means the HV will
 123      * potentially access and cache entries for the current LPID as
 124      * well.
 125      */
 126     tlb_flush(env_cpu(env));
 127 }
 128
 129 void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
 130 {
 131     target_ulong hid0;
 132
 133     hid0 = env->spr[SPR_HID0];
 134     if ((val ^ hid0) & 0x00000008) {
 135         /* Change current endianness */
 136         env->hflags &= ~(1 << MSR_LE);
 137         env->hflags_nmsr &= ~(1 << MSR_LE);
 138         env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
 139         env->hflags |= env->hflags_nmsr;
 140         qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
 141                  val & 0x8 ? 'l' : 'b', env->hflags);
 142     }
 143     env->spr[SPR_HID0] = (uint32_t)val;
 144 }
 145
 146 void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
 147 {
 148     if (likely(env->pb[num] != value)) {
 149         env->pb[num] = value;
 150         /* Should be optimized */
 151         tlb_flush(env_cpu(env));
 152     }
 153 }
 154
 155 void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
 156 {
 157     store_40x_dbcr0(env, val);
 158 }
 159
 160 void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
 161 {
 162     store_40x_sler(env, val);
 163 }
 164 #endif
 165 /*****************************************************************************/
 166 /* PowerPC 601 specific instructions (POWER bridge) */
 167
 168 target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 169 {
 170     switch (arg) {
 171     case 0x0CUL:
 172         /* Instruction cache line size */
 173         return env->icache_line_size;
 174         break;
 175     case 0x0DUL:
 176         /* Data cache line size */
 177         return env->dcache_line_size;
 178         break;
 179     case 0x0EUL:
 180         /* Minimum cache line size */
 181         return (env->icache_line_size < env->dcache_line_size) ?
 182             env->icache_line_size : env->dcache_line_size;
 183         break;
 184     case 0x0FUL:
 185         /* Maximum cache line size */
 186         return (env->icache_line_size > env->dcache_line_size) ?
 187             env->icache_line_size : env->dcache_line_size;
 188         break;
 189     default:
 190         /* Undefined */
 191         return 0;
 192         break;
 193     }
 194 }
 195
 196 /*****************************************************************************/
 197 /* Special registers manipulation */
 198
 199 /* GDBstub can read and write MSR... */
 200 void ppc_store_msr(CPUPPCState *env, target_ulong value)
 201 {
 202     hreg_store_msr(env, value, 0);
 203 }
 204
 205 /*
 206  * This code is lifted from MacOnLinux. It is called whenever THRM1,2
 207  * or 3 is read an fixes up the values in such a way that will make
 208  * MacOS not hang. These registers exist on some 75x and 74xx
 209  * processors.
 210  */
 211 void helper_fixup_thrm(CPUPPCState *env)
 212 {
 213     target_ulong v, t;
 214     int i;
 215
 216 #define THRM1_TIN       (1 << 31)
 217 #define THRM1_TIV       (1 << 30)
 218 #define THRM1_THRES(x)  (((x) & 0x7f) << 23)
 219 #define THRM1_TID       (1 << 2)
 220 #define THRM1_TIE       (1 << 1)
 221 #define THRM1_V         (1 << 0)
 222 #define THRM3_E         (1 << 0)
 223
 224     if (!(env->spr[SPR_THRM3] & THRM3_E)) {
 225         return;
 226     }
 227
 228     /* Note: Thermal interrupts are unimplemented */
 229     for (i = SPR_THRM1; i <= SPR_THRM2; i++) {
 230         v = env->spr[i];
 231         if (!(v & THRM1_V)) {
 232             continue;
 233         }
 234         v |= THRM1_TIV;
 235         v &= ~THRM1_TIN;
 236         t = v & THRM1_THRES(127);
 237         if ((v & THRM1_TID) && t < THRM1_THRES(24)) {
 238             v |= THRM1_TIN;
 239         }
 240         if (!(v & THRM1_TID) && t > THRM1_THRES(24)) {
 241             v |= THRM1_TIN;
 242         }
 243         env->spr[i] = v;
 244     }
 245 }