qapi: drop the sentinel in enum array
[qemu/armbru.git] / target / m68k / gdbstub.c
blobc7f44c9bb32be14ef0323fce8b243e1bf59a46fb
1 /*
2 * m68k gdb server stub
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "cpu.h"
23 #include "exec/gdbstub.h"
25 int m68k_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
27 M68kCPU *cpu = M68K_CPU(cs);
28 CPUM68KState *env = &cpu->env;
30 if (n < 8) {
31 /* D0-D7 */
32 return gdb_get_reg32(mem_buf, env->dregs[n]);
33 } else if (n < 16) {
34 /* A0-A7 */
35 return gdb_get_reg32(mem_buf, env->aregs[n - 8]);
36 } else {
37 switch (n) {
38 case 16:
39 return gdb_get_reg32(mem_buf, env->sr);
40 case 17:
41 return gdb_get_reg32(mem_buf, env->pc);
44 /* FP registers not included here because they vary between
45 ColdFire and m68k. Use XML bits for these. */
46 return 0;
49 int m68k_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
51 M68kCPU *cpu = M68K_CPU(cs);
52 CPUM68KState *env = &cpu->env;
53 uint32_t tmp;
55 tmp = ldl_p(mem_buf);
57 if (n < 8) {
58 /* D0-D7 */
59 env->dregs[n] = tmp;
60 } else if (n < 16) {
61 /* A0-A7 */
62 env->aregs[n - 8] = tmp;
63 } else {
64 switch (n) {
65 case 16:
66 env->sr = tmp;
67 break;
68 case 17:
69 env->pc = tmp;
70 break;
71 default:
72 return 0;
75 return 4;