target-hppa/cpu.h

   1 /*
   2  *  HPPA virtual CPU header
   3  *
   4  *  Copyright (c) 2005-2009 Stuart Brady <stuart.brady@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Library General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Library General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Library General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20
  21 #ifndef CPU_HPPA_H
  22 #define CPU_HPPA_H
  23
  24 #include "config.h"
  25
  26 #if !defined(TARGET_HPPA64)
  27 #define TARGET_LONG_BITS 32
  28 #else
  29 #define TARGET_LONG_BITS 64
  30 #endif
  31
  32 #define CPUState struct CPUHPPAState
  33
  34 #include "cpu-defs.h"
  35
  36 #include <setjmp.h>
  37
  38 #include "softfloat.h"
  39
  40 #define TARGET_HAS_ICE
  41
  42 #define ELF_MACHINE     EM_PARISC
  43
  44 /* Group 1 interruptions */
  45 #define EXCP_HPMC       1       /* High-priority machine check */
  46 /* Group 2 interruptions */
  47 #define EXCP_POWERFAIL  2
  48 #define EXCP_RCVRCTR    3
  49 #define EXCP_EXTINT     4
  50 #define EXCP_LPMC       5
  51 #define EXCP_PERFMON    29
  52 /* Group 3 interruptions */
  53 #define EXCP_ITLBMISS   6
  54 #define EXCP_IMEMTRAP   7
  55 #define EXCP_ILLEGAL    8
  56 #define EXCP_BREAK      9
  57 #define EXCP_PRIVOP     10
  58 #define EXCP_PRIVREG    11
  59 #define EXCP_OVERFLOW   12
  60 #define EXCP_CONDITIONAL 13
  61 #define EXCP_ASSISTEX   14
  62 #define EXCP_DTLBMISS   15
  63 #define EXCP_NAITLBMISS 16
  64 #define EXCP_NADTLBMISS 17
  65 #define EXCP_DMEMACCESS 26
  66 #define EXCP_DMEMPROT   27
  67 #define EXCP_UNALIGNED  28
  68 #define EXCP_DMEMPROT2  19
  69 #define EXCP_TLBDIRTY   20
  70 #define EXCP_PAGEREF    21
  71 #define EXCP_ASSISTEMU  22
  72 /* Group 4 interruptions */
  73 #define EXCP_HIPRIVXFER 23
  74 #define EXCP_LOPRIVXFER 24
  75 #define EXCP_TAKENBR    25
  76
  77 /* the shadow registers map to the following general registers */
  78 // int shrmap[] = { 1, 6, 9, 16, 17, 24, 25 };
  79
  80 #define PSW_I   0x00000001
  81 #define PSW_D   0x00000002
  82 #define PSW_P   0x00000004
  83 #define PSW_Q   0x00000008
  84 #define PSW_R   0x00000010
  85 #define PSW_F   0x00000020
  86 #define PSW_G   0x00000040
  87 #define PSW_O   0x00000080
  88 #define PSW_CB  0x0000ff00
  89 #define PSW_CB0 0x00000100
  90 #define PSW_CB1 0x00000200
  91 #define PSW_CB2 0x00000400
  92 #define PSW_CB3 0x00000800
  93 #define PSW_CB4 0x00001000
  94 #define PSW_CB5 0x00002000
  95 #define PSW_CB6 0x00004000
  96 #define PSW_CB7 0x00008000
  97 #define PSW_M   0x00010000
  98 #define PSW_V   0x00020000
  99 #define PSW_C   0x00040000
 100 #define PSW_B   0x00080000
 101 #define PSW_X   0x00100000
 102 #define PSW_N   0x00200000
 103 #define PSW_L   0x00400000
 104 #define PSW_H   0x00800000
 105 #define PSW_T   0x01000000
 106 #define PSW_S   0x02000000
 107 #define PSW_E   0x04000000
 108 #define PSW_W   0x08000000
 109 #define PSW_Z   0x40000000
 110 #define PSW_Y   0x80000000
 111
 112 #define PSW_CB_SHIFT    8
 113
 114 #define NB_MMU_MODES 2
 115
 116 typedef struct CPUHPPAState {
 117     target_ulong gr[32];  /* General Registers */
 118     target_ulong shr[7];  /* SHadow Registers */
 119     uint32_t sr[8];       /* Space Registers */
 120     uint32_t cr[32];      /* Control Registers */
 121 #if 0
 122     uint32_t cpr[n][8];   /* Co-Processor Registers */
 123 #endif
 124     uint32_t fpr[32];     /* Floating-Point Registers */
 125
 126     uint32_t psw;         /* Processor Status Word */
 127     target_ulong iaoq[2]; /* Instruction Address Offset Queue */
 128     uint32_t iasq[2];     /* Instruction Address Space Queue */
 129     target_ulong iiaoq_back;
 130     uint32_t iiasq_back;
 131
 132     uint8_t priv_level;
 133
 134  /*  gr[0]  : permanently 0
 135   *  gr[1]  : target for ADDIL
 136   *  gr[31] : link register for BLE
 137   */
 138
 139     int interrupt_index;
 140
 141     CPU_COMMON
 142
 143     /* Fields after the common ones are preserved on reset.  */
 144     struct hppa_boot_info *boot_info;
 145 } CPUHPPAState;
 146
 147 #define TARGET_PAGE_BITS 12
 148
 149 #define cpu_init cpu_hppa_init
 150 #define cpu_exec cpu_hppa_exec
 151 #define cpu_gen_code cpu_hppa_gen_code
 152 #define cpu_signal_handler cpu_hppa_signal_handler
 153
 154 /* MMU modes definitions */
 155 #define MMU_MODE0_SUFFIX _kernel
 156 #define MMU_MODE1_SUFFIX _user
 157 #define MMU_USER_IDX 0
 158 static inline int cpu_mmu_index (CPUState *env)
 159 {
 160 #if defined(CONFIG_USER_ONLY)
 161     return 0;
 162 #else
 163     return (env->iaoq[0] & 3) != 0 ? 1 : 0;
 164 #endif
 165 }
 166
 167 #if defined(CONFIG_USER_ONLY)
 168 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 169 {
 170     if (newsp)
 171         env->gr[30] = newsp;
 172     /* XXXXX */
 173 }
 174 #endif
 175
 176 #include "cpu-all.h"
 177 #include "exec-all.h"
 178
 179 CPUHPPAState *cpu_hppa_init(const char *cpu_model);
 180 void hppa_translate_init(void);
 181 int cpu_hppa_exec(CPUHPPAState *s);
 182 int cpu_hppa_signal_handler(int host_signum, void *pinfo,
 183                             void *puc);
 184 int cpu_hppa_handle_mmu_fault(CPUHPPAState *env, target_ulong address, int rw,
 185                               int mmu_idx, int is_softmmu);
 186 void do_interrupt(CPUHPPAState *env);
 187
 188 void hppa_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 189
 190 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 191 {
 192     env->iaoq[0] = tb->pc;
 193     env->iaoq[1] = tb->cs_base;
 194 }
 195
 196 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 197                                         target_ulong *cs_base, int *flags)
 198 {
 199     *flags = env->psw & PSW_N; /* XXX: use more bits? */
 200     *pc = env->iaoq[0];
 201     *cs_base = env->iaoq[1];
 202 }
 203
 204 #endif