target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18 #include <sys/utsname.h>
  19
  20 #include <linux/kvm.h>
  21
  22 #include "qemu-common.h"
  23 #include "sysemu.h"
  24 #include "kvm.h"
  25 #include "cpu.h"
  26 #include "gdbstub.h"
  27 #include "host-utils.h"
  28 #include "hw/pc.h"
  29 #include "hw/apic.h"
  30 #include "ioport.h"
  31 #include "kvm_x86.h"
  32
  33 #ifdef CONFIG_KVM_PARA
  34 #include <linux/kvm_para.h>
  35 #endif
  36 //
  37 //#define DEBUG_KVM
  38
  39 #ifdef DEBUG_KVM
  40 #define DPRINTF(fmt, ...) \
  41     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...) \
  44     do { } while (0)
  45 #endif
  46
  47 #define MSR_KVM_WALL_CLOCK  0x11
  48 #define MSR_KVM_SYSTEM_TIME 0x12
  49
  50 #ifndef BUS_MCEERR_AR
  51 #define BUS_MCEERR_AR 4
  52 #endif
  53 #ifndef BUS_MCEERR_AO
  54 #define BUS_MCEERR_AO 5
  55 #endif
  56
  57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
  58     KVM_CAP_INFO(SET_TSS_ADDR),
  59     KVM_CAP_INFO(EXT_CPUID),
  60     KVM_CAP_INFO(MP_STATE),
  61     KVM_CAP_LAST_INFO
  62 };
  63
  64 static bool has_msr_star;
  65 static bool has_msr_hsave_pa;
  66 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
  67 static bool has_msr_async_pf_en;
  68 #endif
  69 static int lm_capable_kernel;
  70
  71 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  72 {
  73     struct kvm_cpuid2 *cpuid;
  74     int r, size;
  75
  76     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  77     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  78     cpuid->nent = max;
  79     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  80     if (r == 0 && cpuid->nent >= max) {
  81         r = -E2BIG;
  82     }
  83     if (r < 0) {
  84         if (r == -E2BIG) {
  85             qemu_free(cpuid);
  86             return NULL;
  87         } else {
  88             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  89                     strerror(-r));
  90             exit(1);
  91         }
  92     }
  93     return cpuid;
  94 }
  95
  96 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  97                                       uint32_t index, int reg)
  98 {
  99     struct kvm_cpuid2 *cpuid;
 100     int i, max;
 101     uint32_t ret = 0;
 102     uint32_t cpuid_1_edx;
 103
 104     max = 1;
 105     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
 106         max *= 2;
 107     }
 108
 109     for (i = 0; i < cpuid->nent; ++i) {
 110         if (cpuid->entries[i].function == function &&
 111             cpuid->entries[i].index == index) {
 112             switch (reg) {
 113             case R_EAX:
 114                 ret = cpuid->entries[i].eax;
 115                 break;
 116             case R_EBX:
 117                 ret = cpuid->entries[i].ebx;
 118                 break;
 119             case R_ECX:
 120                 ret = cpuid->entries[i].ecx;
 121                 break;
 122             case R_EDX:
 123                 ret = cpuid->entries[i].edx;
 124                 switch (function) {
 125                 case 1:
 126                     /* KVM before 2.6.30 misreports the following features */
 127                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 128                     break;
 129                 case 0x80000001:
 130                     /* On Intel, kvm returns cpuid according to the Intel spec,
 131                      * so add missing bits according to the AMD spec:
 132                      */
 133                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 134                     ret |= cpuid_1_edx & 0x183f7ff;
 135                     break;
 136                 }
 137                 break;
 138             }
 139         }
 140     }
 141
 142     qemu_free(cpuid);
 143
 144     return ret;
 145 }
 146
 147 #ifdef CONFIG_KVM_PARA
 148 struct kvm_para_features {
 149     int cap;
 150     int feature;
 151 } para_features[] = {
 152     { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 153     { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 154     { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 155 #ifdef KVM_CAP_ASYNC_PF
 156     { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
 157 #endif
 158     { -1, -1 }
 159 };
 160
 161 static int get_para_features(CPUState *env)
 162 {
 163     int i, features = 0;
 164
 165     for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 166         if (kvm_check_extension(env->kvm_state, para_features[i].cap)) {
 167             features |= (1 << para_features[i].feature);
 168         }
 169     }
 170 #ifdef KVM_CAP_ASYNC_PF
 171     has_msr_async_pf_en = features & (1 << KVM_FEATURE_ASYNC_PF);
 172 #endif
 173     return features;
 174 }
 175 #endif
 176
 177 #ifdef KVM_CAP_MCE
 178 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 179                                      int *max_banks)
 180 {
 181     int r;
 182
 183     r = kvm_check_extension(s, KVM_CAP_MCE);
 184     if (r > 0) {
 185         *max_banks = r;
 186         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 187     }
 188     return -ENOSYS;
 189 }
 190
 191 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 192 {
 193     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 194 }
 195
 196 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 197 {
 198     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 199 }
 200
 201 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 202 {
 203     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 204     int r;
 205
 206     kmsrs->nmsrs = n;
 207     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 208     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 209     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 210     free(kmsrs);
 211     return r;
 212 }
 213
 214 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 215 static int kvm_mce_in_progress(CPUState *env)
 216 {
 217     struct kvm_msr_entry msr_mcg_status = {
 218         .index = MSR_MCG_STATUS,
 219     };
 220     int r;
 221
 222     r = kvm_get_msr(env, &msr_mcg_status, 1);
 223     if (r == -1 || r == 0) {
 224         fprintf(stderr, "Failed to get MCE status\n");
 225         return 0;
 226     }
 227     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 228 }
 229
 230 struct kvm_x86_mce_data
 231 {
 232     CPUState *env;
 233     struct kvm_x86_mce *mce;
 234     int abort_on_error;
 235 };
 236
 237 static void kvm_do_inject_x86_mce(void *_data)
 238 {
 239     struct kvm_x86_mce_data *data = _data;
 240     int r;
 241
 242     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 243     if ((data->env->mcg_cap & MCG_SER_P) &&
 244         !(data->mce->status & MCI_STATUS_AR)) {
 245         if (kvm_mce_in_progress(data->env)) {
 246             return;
 247         }
 248     }
 249
 250     r = kvm_set_mce(data->env, data->mce);
 251     if (r < 0) {
 252         perror("kvm_set_mce FAILED");
 253         if (data->abort_on_error) {
 254             abort();
 255         }
 256     }
 257 }
 258
 259 static void kvm_inject_x86_mce_on(CPUState *env, struct kvm_x86_mce *mce,
 260                                   int flag)
 261 {
 262     struct kvm_x86_mce_data data = {
 263         .env = env,
 264         .mce = mce,
 265         .abort_on_error = (flag & ABORT_ON_ERROR),
 266     };
 267
 268     if (!env->mcg_cap) {
 269         fprintf(stderr, "MCE support is not enabled!\n");
 270         return;
 271     }
 272
 273     run_on_cpu(env, kvm_do_inject_x86_mce, &data);
 274 }
 275
 276 static void kvm_mce_broadcast_rest(CPUState *env);
 277 #endif
 278
 279 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 280                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 281                         int flag)
 282 {
 283 #ifdef KVM_CAP_MCE
 284     struct kvm_x86_mce mce = {
 285         .bank = bank,
 286         .status = status,
 287         .mcg_status = mcg_status,
 288         .addr = addr,
 289         .misc = misc,
 290     };
 291
 292     if (flag & MCE_BROADCAST) {
 293         kvm_mce_broadcast_rest(cenv);
 294     }
 295
 296     kvm_inject_x86_mce_on(cenv, &mce, flag);
 297 #else
 298     if (flag & ABORT_ON_ERROR) {
 299         abort();
 300     }
 301 #endif
 302 }
 303
 304 int kvm_arch_init_vcpu(CPUState *env)
 305 {
 306     struct {
 307         struct kvm_cpuid2 cpuid;
 308         struct kvm_cpuid_entry2 entries[100];
 309     } __attribute__((packed)) cpuid_data;
 310     uint32_t limit, i, j, cpuid_i;
 311     uint32_t unused;
 312     struct kvm_cpuid_entry2 *c;
 313 #ifdef CONFIG_KVM_PARA
 314     uint32_t signature[3];
 315 #endif
 316
 317     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 318
 319     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 320     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 321     env->cpuid_ext_features |= i;
 322
 323     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 324                                                              0, R_EDX);
 325     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 326                                                              0, R_ECX);
 327     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 328                                                              0, R_EDX);
 329
 330
 331     cpuid_i = 0;
 332
 333 #ifdef CONFIG_KVM_PARA
 334     /* Paravirtualization CPUIDs */
 335     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 336     c = &cpuid_data.entries[cpuid_i++];
 337     memset(c, 0, sizeof(*c));
 338     c->function = KVM_CPUID_SIGNATURE;
 339     c->eax = 0;
 340     c->ebx = signature[0];
 341     c->ecx = signature[1];
 342     c->edx = signature[2];
 343
 344     c = &cpuid_data.entries[cpuid_i++];
 345     memset(c, 0, sizeof(*c));
 346     c->function = KVM_CPUID_FEATURES;
 347     c->eax = env->cpuid_kvm_features & get_para_features(env);
 348 #endif
 349
 350     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 351
 352     for (i = 0; i <= limit; i++) {
 353         c = &cpuid_data.entries[cpuid_i++];
 354
 355         switch (i) {
 356         case 2: {
 357             /* Keep reading function 2 till all the input is received */
 358             int times;
 359
 360             c->function = i;
 361             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 362                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 363             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 364             times = c->eax & 0xff;
 365
 366             for (j = 1; j < times; ++j) {
 367                 c = &cpuid_data.entries[cpuid_i++];
 368                 c->function = i;
 369                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 370                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 371             }
 372             break;
 373         }
 374         case 4:
 375         case 0xb:
 376         case 0xd:
 377             for (j = 0; ; j++) {
 378                 c->function = i;
 379                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 380                 c->index = j;
 381                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 382
 383                 if (i == 4 && c->eax == 0) {
 384                     break;
 385                 }
 386                 if (i == 0xb && !(c->ecx & 0xff00)) {
 387                     break;
 388                 }
 389                 if (i == 0xd && c->eax == 0) {
 390                     break;
 391                 }
 392                 c = &cpuid_data.entries[cpuid_i++];
 393             }
 394             break;
 395         default:
 396             c->function = i;
 397             c->flags = 0;
 398             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 399             break;
 400         }
 401     }
 402     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 403
 404     for (i = 0x80000000; i <= limit; i++) {
 405         c = &cpuid_data.entries[cpuid_i++];
 406
 407         c->function = i;
 408         c->flags = 0;
 409         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 410     }
 411
 412     cpuid_data.cpuid.nent = cpuid_i;
 413
 414 #ifdef KVM_CAP_MCE
 415     if (((env->cpuid_version >> 8)&0xF) >= 6
 416         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 417         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 418         uint64_t mcg_cap;
 419         int banks;
 420
 421         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks)) {
 422             perror("kvm_get_mce_cap_supported FAILED");
 423         } else {
 424             if (banks > MCE_BANKS_DEF)
 425                 banks = MCE_BANKS_DEF;
 426             mcg_cap &= MCE_CAP_DEF;
 427             mcg_cap |= banks;
 428             if (kvm_setup_mce(env, &mcg_cap)) {
 429                 perror("kvm_setup_mce FAILED");
 430             } else {
 431                 env->mcg_cap = mcg_cap;
 432             }
 433         }
 434     }
 435 #endif
 436
 437     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 438 }
 439
 440 void kvm_arch_reset_vcpu(CPUState *env)
 441 {
 442     env->exception_injected = -1;
 443     env->interrupt_injected = -1;
 444     env->xcr0 = 1;
 445     if (kvm_irqchip_in_kernel()) {
 446         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 447                                           KVM_MP_STATE_UNINITIALIZED;
 448     } else {
 449         env->mp_state = KVM_MP_STATE_RUNNABLE;
 450     }
 451 }
 452
 453 static int kvm_get_supported_msrs(KVMState *s)
 454 {
 455     static int kvm_supported_msrs;
 456     int ret = 0;
 457
 458     /* first time */
 459     if (kvm_supported_msrs == 0) {
 460         struct kvm_msr_list msr_list, *kvm_msr_list;
 461
 462         kvm_supported_msrs = -1;
 463
 464         /* Obtain MSR list from KVM.  These are the MSRs that we must
 465          * save/restore */
 466         msr_list.nmsrs = 0;
 467         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
 468         if (ret < 0 && ret != -E2BIG) {
 469             return ret;
 470         }
 471         /* Old kernel modules had a bug and could write beyond the provided
 472            memory. Allocate at least a safe amount of 1K. */
 473         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 474                                               msr_list.nmsrs *
 475                                               sizeof(msr_list.indices[0])));
 476
 477         kvm_msr_list->nmsrs = msr_list.nmsrs;
 478         ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 479         if (ret >= 0) {
 480             int i;
 481
 482             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 483                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 484                     has_msr_star = true;
 485                     continue;
 486                 }
 487                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 488                     has_msr_hsave_pa = true;
 489                     continue;
 490                 }
 491             }
 492         }
 493
 494         free(kvm_msr_list);
 495     }
 496
 497     return ret;
 498 }
 499
 500 int kvm_arch_init(KVMState *s)
 501 {
 502     uint64_t identity_base = 0xfffbc000;
 503     int ret;
 504     struct utsname utsname;
 505
 506     ret = kvm_get_supported_msrs(s);
 507     if (ret < 0) {
 508         return ret;
 509     }
 510
 511     uname(&utsname);
 512     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
 513
 514     /*
 515      * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
 516      * In order to use vm86 mode, an EPT identity map and a TSS  are needed.
 517      * Since these must be part of guest physical memory, we need to allocate
 518      * them, both by setting their start addresses in the kernel and by
 519      * creating a corresponding e820 entry. We need 4 pages before the BIOS.
 520      *
 521      * Older KVM versions may not support setting the identity map base. In
 522      * that case we need to stick with the default, i.e. a 256K maximum BIOS
 523      * size.
 524      */
 525 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 526     if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 527         /* Allows up to 16M BIOSes. */
 528         identity_base = 0xfeffc000;
 529
 530         ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
 531         if (ret < 0) {
 532             return ret;
 533         }
 534     }
 535 #endif
 536     /* Set TSS base one page after EPT identity map. */
 537     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
 538     if (ret < 0) {
 539         return ret;
 540     }
 541
 542     /* Tell fw_cfg to notify the BIOS to reserve the range. */
 543     ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
 544     if (ret < 0) {
 545         fprintf(stderr, "e820_add_entry() table is full\n");
 546         return ret;
 547     }
 548
 549     return 0;
 550 }
 551
 552 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 553 {
 554     lhs->selector = rhs->selector;
 555     lhs->base = rhs->base;
 556     lhs->limit = rhs->limit;
 557     lhs->type = 3;
 558     lhs->present = 1;
 559     lhs->dpl = 3;
 560     lhs->db = 0;
 561     lhs->s = 1;
 562     lhs->l = 0;
 563     lhs->g = 0;
 564     lhs->avl = 0;
 565     lhs->unusable = 0;
 566 }
 567
 568 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 569 {
 570     unsigned flags = rhs->flags;
 571     lhs->selector = rhs->selector;
 572     lhs->base = rhs->base;
 573     lhs->limit = rhs->limit;
 574     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 575     lhs->present = (flags & DESC_P_MASK) != 0;
 576     lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
 577     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 578     lhs->s = (flags & DESC_S_MASK) != 0;
 579     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 580     lhs->g = (flags & DESC_G_MASK) != 0;
 581     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 582     lhs->unusable = 0;
 583 }
 584
 585 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 586 {
 587     lhs->selector = rhs->selector;
 588     lhs->base = rhs->base;
 589     lhs->limit = rhs->limit;
 590     lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
 591                  (rhs->present * DESC_P_MASK) |
 592                  (rhs->dpl << DESC_DPL_SHIFT) |
 593                  (rhs->db << DESC_B_SHIFT) |
 594                  (rhs->s * DESC_S_MASK) |
 595                  (rhs->l << DESC_L_SHIFT) |
 596                  (rhs->g * DESC_G_MASK) |
 597                  (rhs->avl * DESC_AVL_MASK);
 598 }
 599
 600 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 601 {
 602     if (set) {
 603         *kvm_reg = *qemu_reg;
 604     } else {
 605         *qemu_reg = *kvm_reg;
 606     }
 607 }
 608
 609 static int kvm_getput_regs(CPUState *env, int set)
 610 {
 611     struct kvm_regs regs;
 612     int ret = 0;
 613
 614     if (!set) {
 615         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 616         if (ret < 0) {
 617             return ret;
 618         }
 619     }
 620
 621     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 622     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 623     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 624     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 625     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 626     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 627     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 628     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 629 #ifdef TARGET_X86_64
 630     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 631     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 632     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 633     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 634     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 635     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 636     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 637     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 638 #endif
 639
 640     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 641     kvm_getput_reg(&regs.rip, &env->eip, set);
 642
 643     if (set) {
 644         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 645     }
 646
 647     return ret;
 648 }
 649
 650 static int kvm_put_fpu(CPUState *env)
 651 {
 652     struct kvm_fpu fpu;
 653     int i;
 654
 655     memset(&fpu, 0, sizeof fpu);
 656     fpu.fsw = env->fpus & ~(7 << 11);
 657     fpu.fsw |= (env->fpstt & 7) << 11;
 658     fpu.fcw = env->fpuc;
 659     for (i = 0; i < 8; ++i) {
 660         fpu.ftwx |= (!env->fptags[i]) << i;
 661     }
 662     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 663     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 664     fpu.mxcsr = env->mxcsr;
 665
 666     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 667 }
 668
 669 #ifdef KVM_CAP_XSAVE
 670 #define XSAVE_CWD_RIP     2
 671 #define XSAVE_CWD_RDP     4
 672 #define XSAVE_MXCSR       6
 673 #define XSAVE_ST_SPACE    8
 674 #define XSAVE_XMM_SPACE   40
 675 #define XSAVE_XSTATE_BV   128
 676 #define XSAVE_YMMH_SPACE  144
 677 #endif
 678
 679 static int kvm_put_xsave(CPUState *env)
 680 {
 681 #ifdef KVM_CAP_XSAVE
 682     int i, r;
 683     struct kvm_xsave* xsave;
 684     uint16_t cwd, swd, twd, fop;
 685
 686     if (!kvm_has_xsave()) {
 687         return kvm_put_fpu(env);
 688     }
 689
 690     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 691     memset(xsave, 0, sizeof(struct kvm_xsave));
 692     cwd = swd = twd = fop = 0;
 693     swd = env->fpus & ~(7 << 11);
 694     swd |= (env->fpstt & 7) << 11;
 695     cwd = env->fpuc;
 696     for (i = 0; i < 8; ++i) {
 697         twd |= (!env->fptags[i]) << i;
 698     }
 699     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 700     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 701     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 702             sizeof env->fpregs);
 703     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 704             sizeof env->xmm_regs);
 705     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 706     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 707     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 708             sizeof env->ymmh_regs);
 709     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 710     qemu_free(xsave);
 711     return r;
 712 #else
 713     return kvm_put_fpu(env);
 714 #endif
 715 }
 716
 717 static int kvm_put_xcrs(CPUState *env)
 718 {
 719 #ifdef KVM_CAP_XCRS
 720     struct kvm_xcrs xcrs;
 721
 722     if (!kvm_has_xcrs()) {
 723         return 0;
 724     }
 725
 726     xcrs.nr_xcrs = 1;
 727     xcrs.flags = 0;
 728     xcrs.xcrs[0].xcr = 0;
 729     xcrs.xcrs[0].value = env->xcr0;
 730     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 731 #else
 732     return 0;
 733 #endif
 734 }
 735
 736 static int kvm_put_sregs(CPUState *env)
 737 {
 738     struct kvm_sregs sregs;
 739
 740     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 741     if (env->interrupt_injected >= 0) {
 742         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 743                 (uint64_t)1 << (env->interrupt_injected % 64);
 744     }
 745
 746     if ((env->eflags & VM_MASK)) {
 747         set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 748         set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 749         set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 750         set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 751         set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 752         set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 753     } else {
 754         set_seg(&sregs.cs, &env->segs[R_CS]);
 755         set_seg(&sregs.ds, &env->segs[R_DS]);
 756         set_seg(&sregs.es, &env->segs[R_ES]);
 757         set_seg(&sregs.fs, &env->segs[R_FS]);
 758         set_seg(&sregs.gs, &env->segs[R_GS]);
 759         set_seg(&sregs.ss, &env->segs[R_SS]);
 760     }
 761
 762     set_seg(&sregs.tr, &env->tr);
 763     set_seg(&sregs.ldt, &env->ldt);
 764
 765     sregs.idt.limit = env->idt.limit;
 766     sregs.idt.base = env->idt.base;
 767     sregs.gdt.limit = env->gdt.limit;
 768     sregs.gdt.base = env->gdt.base;
 769
 770     sregs.cr0 = env->cr[0];
 771     sregs.cr2 = env->cr[2];
 772     sregs.cr3 = env->cr[3];
 773     sregs.cr4 = env->cr[4];
 774
 775     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 776     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 777
 778     sregs.efer = env->efer;
 779
 780     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 781 }
 782
 783 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 784                               uint32_t index, uint64_t value)
 785 {
 786     entry->index = index;
 787     entry->data = value;
 788 }
 789
 790 static int kvm_put_msrs(CPUState *env, int level)
 791 {
 792     struct {
 793         struct kvm_msrs info;
 794         struct kvm_msr_entry entries[100];
 795     } msr_data;
 796     struct kvm_msr_entry *msrs = msr_data.entries;
 797     int n = 0;
 798
 799     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 800     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 801     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 802     if (has_msr_star) {
 803         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 804     }
 805     if (has_msr_hsave_pa) {
 806         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 807     }
 808 #ifdef TARGET_X86_64
 809     if (lm_capable_kernel) {
 810         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 811         kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 812         kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 813         kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 814     }
 815 #endif
 816     if (level == KVM_PUT_FULL_STATE) {
 817         /*
 818          * KVM is yet unable to synchronize TSC values of multiple VCPUs on
 819          * writeback. Until this is fixed, we only write the offset to SMP
 820          * guests after migration, desynchronizing the VCPUs, but avoiding
 821          * huge jump-backs that would occur without any writeback at all.
 822          */
 823         if (smp_cpus == 1 || env->tsc != 0) {
 824             kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 825         }
 826     }
 827     /*
 828      * The following paravirtual MSRs have side effects on the guest or are
 829      * too heavy for normal writeback. Limit them to reset or full state
 830      * updates.
 831      */
 832     if (level >= KVM_PUT_RESET_STATE) {
 833         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 834                           env->system_time_msr);
 835         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 836 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
 837         if (has_msr_async_pf_en) {
 838             kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
 839                               env->async_pf_en_msr);
 840         }
 841 #endif
 842     }
 843 #ifdef KVM_CAP_MCE
 844     if (env->mcg_cap) {
 845         int i;
 846
 847         if (level == KVM_PUT_RESET_STATE) {
 848             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 849         } else if (level == KVM_PUT_FULL_STATE) {
 850             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 851             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 852             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
 853                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 854             }
 855         }
 856     }
 857 #endif
 858
 859     msr_data.info.nmsrs = n;
 860
 861     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 862
 863 }
 864
 865
 866 static int kvm_get_fpu(CPUState *env)
 867 {
 868     struct kvm_fpu fpu;
 869     int i, ret;
 870
 871     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 872     if (ret < 0) {
 873         return ret;
 874     }
 875
 876     env->fpstt = (fpu.fsw >> 11) & 7;
 877     env->fpus = fpu.fsw;
 878     env->fpuc = fpu.fcw;
 879     for (i = 0; i < 8; ++i) {
 880         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 881     }
 882     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 883     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 884     env->mxcsr = fpu.mxcsr;
 885
 886     return 0;
 887 }
 888
 889 static int kvm_get_xsave(CPUState *env)
 890 {
 891 #ifdef KVM_CAP_XSAVE
 892     struct kvm_xsave* xsave;
 893     int ret, i;
 894     uint16_t cwd, swd, twd, fop;
 895
 896     if (!kvm_has_xsave()) {
 897         return kvm_get_fpu(env);
 898     }
 899
 900     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 901     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 902     if (ret < 0) {
 903         qemu_free(xsave);
 904         return ret;
 905     }
 906
 907     cwd = (uint16_t)xsave->region[0];
 908     swd = (uint16_t)(xsave->region[0] >> 16);
 909     twd = (uint16_t)xsave->region[1];
 910     fop = (uint16_t)(xsave->region[1] >> 16);
 911     env->fpstt = (swd >> 11) & 7;
 912     env->fpus = swd;
 913     env->fpuc = cwd;
 914     for (i = 0; i < 8; ++i) {
 915         env->fptags[i] = !((twd >> i) & 1);
 916     }
 917     env->mxcsr = xsave->region[XSAVE_MXCSR];
 918     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 919             sizeof env->fpregs);
 920     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 921             sizeof env->xmm_regs);
 922     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 923     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 924             sizeof env->ymmh_regs);
 925     qemu_free(xsave);
 926     return 0;
 927 #else
 928     return kvm_get_fpu(env);
 929 #endif
 930 }
 931
 932 static int kvm_get_xcrs(CPUState *env)
 933 {
 934 #ifdef KVM_CAP_XCRS
 935     int i, ret;
 936     struct kvm_xcrs xcrs;
 937
 938     if (!kvm_has_xcrs()) {
 939         return 0;
 940     }
 941
 942     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 943     if (ret < 0) {
 944         return ret;
 945     }
 946
 947     for (i = 0; i < xcrs.nr_xcrs; i++) {
 948         /* Only support xcr0 now */
 949         if (xcrs.xcrs[0].xcr == 0) {
 950             env->xcr0 = xcrs.xcrs[0].value;
 951             break;
 952         }
 953     }
 954     return 0;
 955 #else
 956     return 0;
 957 #endif
 958 }
 959
 960 static int kvm_get_sregs(CPUState *env)
 961 {
 962     struct kvm_sregs sregs;
 963     uint32_t hflags;
 964     int bit, i, ret;
 965
 966     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 967     if (ret < 0) {
 968         return ret;
 969     }
 970
 971     /* There can only be one pending IRQ set in the bitmap at a time, so try
 972        to find it and save its number instead (-1 for none). */
 973     env->interrupt_injected = -1;
 974     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 975         if (sregs.interrupt_bitmap[i]) {
 976             bit = ctz64(sregs.interrupt_bitmap[i]);
 977             env->interrupt_injected = i * 64 + bit;
 978             break;
 979         }
 980     }
 981
 982     get_seg(&env->segs[R_CS], &sregs.cs);
 983     get_seg(&env->segs[R_DS], &sregs.ds);
 984     get_seg(&env->segs[R_ES], &sregs.es);
 985     get_seg(&env->segs[R_FS], &sregs.fs);
 986     get_seg(&env->segs[R_GS], &sregs.gs);
 987     get_seg(&env->segs[R_SS], &sregs.ss);
 988
 989     get_seg(&env->tr, &sregs.tr);
 990     get_seg(&env->ldt, &sregs.ldt);
 991
 992     env->idt.limit = sregs.idt.limit;
 993     env->idt.base = sregs.idt.base;
 994     env->gdt.limit = sregs.gdt.limit;
 995     env->gdt.base = sregs.gdt.base;
 996
 997     env->cr[0] = sregs.cr0;
 998     env->cr[2] = sregs.cr2;
 999     env->cr[3] = sregs.cr3;
1000     env->cr[4] = sregs.cr4;
1001
1002     cpu_set_apic_base(env->apic_state, sregs.apic_base);
1003
1004     env->efer = sregs.efer;
1005     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
1006
1007 #define HFLAG_COPY_MASK \
1008     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1009        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1010        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1011        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1012
1013     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1014     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1015     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1016                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1017     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1018     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1019                 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1020
1021     if (env->efer & MSR_EFER_LMA) {
1022         hflags |= HF_LMA_MASK;
1023     }
1024
1025     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1026         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1027     } else {
1028         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1029                     (DESC_B_SHIFT - HF_CS32_SHIFT);
1030         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1031                     (DESC_B_SHIFT - HF_SS32_SHIFT);
1032         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1033             !(hflags & HF_CS32_MASK)) {
1034             hflags |= HF_ADDSEG_MASK;
1035         } else {
1036             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1037                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1038         }
1039     }
1040     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1041
1042     return 0;
1043 }
1044
1045 static int kvm_get_msrs(CPUState *env)
1046 {
1047     struct {
1048         struct kvm_msrs info;
1049         struct kvm_msr_entry entries[100];
1050     } msr_data;
1051     struct kvm_msr_entry *msrs = msr_data.entries;
1052     int ret, i, n;
1053
1054     n = 0;
1055     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1056     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1057     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1058     if (has_msr_star) {
1059         msrs[n++].index = MSR_STAR;
1060     }
1061     if (has_msr_hsave_pa) {
1062         msrs[n++].index = MSR_VM_HSAVE_PA;
1063     }
1064     msrs[n++].index = MSR_IA32_TSC;
1065 #ifdef TARGET_X86_64
1066     if (lm_capable_kernel) {
1067         msrs[n++].index = MSR_CSTAR;
1068         msrs[n++].index = MSR_KERNELGSBASE;
1069         msrs[n++].index = MSR_FMASK;
1070         msrs[n++].index = MSR_LSTAR;
1071     }
1072 #endif
1073     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1074     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1075 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1076     if (has_msr_async_pf_en) {
1077         msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1078     }
1079 #endif
1080
1081 #ifdef KVM_CAP_MCE
1082     if (env->mcg_cap) {
1083         msrs[n++].index = MSR_MCG_STATUS;
1084         msrs[n++].index = MSR_MCG_CTL;
1085         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1086             msrs[n++].index = MSR_MC0_CTL + i;
1087         }
1088     }
1089 #endif
1090
1091     msr_data.info.nmsrs = n;
1092     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1093     if (ret < 0) {
1094         return ret;
1095     }
1096
1097     for (i = 0; i < ret; i++) {
1098         switch (msrs[i].index) {
1099         case MSR_IA32_SYSENTER_CS:
1100             env->sysenter_cs = msrs[i].data;
1101             break;
1102         case MSR_IA32_SYSENTER_ESP:
1103             env->sysenter_esp = msrs[i].data;
1104             break;
1105         case MSR_IA32_SYSENTER_EIP:
1106             env->sysenter_eip = msrs[i].data;
1107             break;
1108         case MSR_STAR:
1109             env->star = msrs[i].data;
1110             break;
1111 #ifdef TARGET_X86_64
1112         case MSR_CSTAR:
1113             env->cstar = msrs[i].data;
1114             break;
1115         case MSR_KERNELGSBASE:
1116             env->kernelgsbase = msrs[i].data;
1117             break;
1118         case MSR_FMASK:
1119             env->fmask = msrs[i].data;
1120             break;
1121         case MSR_LSTAR:
1122             env->lstar = msrs[i].data;
1123             break;
1124 #endif
1125         case MSR_IA32_TSC:
1126             env->tsc = msrs[i].data;
1127             break;
1128         case MSR_VM_HSAVE_PA:
1129             env->vm_hsave = msrs[i].data;
1130             break;
1131         case MSR_KVM_SYSTEM_TIME:
1132             env->system_time_msr = msrs[i].data;
1133             break;
1134         case MSR_KVM_WALL_CLOCK:
1135             env->wall_clock_msr = msrs[i].data;
1136             break;
1137 #ifdef KVM_CAP_MCE
1138         case MSR_MCG_STATUS:
1139             env->mcg_status = msrs[i].data;
1140             break;
1141         case MSR_MCG_CTL:
1142             env->mcg_ctl = msrs[i].data;
1143             break;
1144 #endif
1145         default:
1146 #ifdef KVM_CAP_MCE
1147             if (msrs[i].index >= MSR_MC0_CTL &&
1148                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1149                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1150             }
1151 #endif
1152             break;
1153 #if defined(CONFIG_KVM_PARA) && defined(KVM_CAP_ASYNC_PF)
1154         case MSR_KVM_ASYNC_PF_EN:
1155             env->async_pf_en_msr = msrs[i].data;
1156             break;
1157 #endif
1158         }
1159     }
1160
1161     return 0;
1162 }
1163
1164 static int kvm_put_mp_state(CPUState *env)
1165 {
1166     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1167
1168     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1169 }
1170
1171 static int kvm_get_mp_state(CPUState *env)
1172 {
1173     struct kvm_mp_state mp_state;
1174     int ret;
1175
1176     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1177     if (ret < 0) {
1178         return ret;
1179     }
1180     env->mp_state = mp_state.mp_state;
1181     if (kvm_irqchip_in_kernel()) {
1182         env->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1183     }
1184     return 0;
1185 }
1186
1187 static int kvm_put_vcpu_events(CPUState *env, int level)
1188 {
1189 #ifdef KVM_CAP_VCPU_EVENTS
1190     struct kvm_vcpu_events events;
1191
1192     if (!kvm_has_vcpu_events()) {
1193         return 0;
1194     }
1195
1196     events.exception.injected = (env->exception_injected >= 0);
1197     events.exception.nr = env->exception_injected;
1198     events.exception.has_error_code = env->has_error_code;
1199     events.exception.error_code = env->error_code;
1200
1201     events.interrupt.injected = (env->interrupt_injected >= 0);
1202     events.interrupt.nr = env->interrupt_injected;
1203     events.interrupt.soft = env->soft_interrupt;
1204
1205     events.nmi.injected = env->nmi_injected;
1206     events.nmi.pending = env->nmi_pending;
1207     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1208
1209     events.sipi_vector = env->sipi_vector;
1210
1211     events.flags = 0;
1212     if (level >= KVM_PUT_RESET_STATE) {
1213         events.flags |=
1214             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1215     }
1216
1217     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1218 #else
1219     return 0;
1220 #endif
1221 }
1222
1223 static int kvm_get_vcpu_events(CPUState *env)
1224 {
1225 #ifdef KVM_CAP_VCPU_EVENTS
1226     struct kvm_vcpu_events events;
1227     int ret;
1228
1229     if (!kvm_has_vcpu_events()) {
1230         return 0;
1231     }
1232
1233     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1234     if (ret < 0) {
1235        return ret;
1236     }
1237     env->exception_injected =
1238        events.exception.injected ? events.exception.nr : -1;
1239     env->has_error_code = events.exception.has_error_code;
1240     env->error_code = events.exception.error_code;
1241
1242     env->interrupt_injected =
1243         events.interrupt.injected ? events.interrupt.nr : -1;
1244     env->soft_interrupt = events.interrupt.soft;
1245
1246     env->nmi_injected = events.nmi.injected;
1247     env->nmi_pending = events.nmi.pending;
1248     if (events.nmi.masked) {
1249         env->hflags2 |= HF2_NMI_MASK;
1250     } else {
1251         env->hflags2 &= ~HF2_NMI_MASK;
1252     }
1253
1254     env->sipi_vector = events.sipi_vector;
1255 #endif
1256
1257     return 0;
1258 }
1259
1260 static int kvm_guest_debug_workarounds(CPUState *env)
1261 {
1262     int ret = 0;
1263 #ifdef KVM_CAP_SET_GUEST_DEBUG
1264     unsigned long reinject_trap = 0;
1265
1266     if (!kvm_has_vcpu_events()) {
1267         if (env->exception_injected == 1) {
1268             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1269         } else if (env->exception_injected == 3) {
1270             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1271         }
1272         env->exception_injected = -1;
1273     }
1274
1275     /*
1276      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1277      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1278      * by updating the debug state once again if single-stepping is on.
1279      * Another reason to call kvm_update_guest_debug here is a pending debug
1280      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1281      * reinject them via SET_GUEST_DEBUG.
1282      */
1283     if (reinject_trap ||
1284         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1285         ret = kvm_update_guest_debug(env, reinject_trap);
1286     }
1287 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1288     return ret;
1289 }
1290
1291 static int kvm_put_debugregs(CPUState *env)
1292 {
1293 #ifdef KVM_CAP_DEBUGREGS
1294     struct kvm_debugregs dbgregs;
1295     int i;
1296
1297     if (!kvm_has_debugregs()) {
1298         return 0;
1299     }
1300
1301     for (i = 0; i < 4; i++) {
1302         dbgregs.db[i] = env->dr[i];
1303     }
1304     dbgregs.dr6 = env->dr[6];
1305     dbgregs.dr7 = env->dr[7];
1306     dbgregs.flags = 0;
1307
1308     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1309 #else
1310     return 0;
1311 #endif
1312 }
1313
1314 static int kvm_get_debugregs(CPUState *env)
1315 {
1316 #ifdef KVM_CAP_DEBUGREGS
1317     struct kvm_debugregs dbgregs;
1318     int i, ret;
1319
1320     if (!kvm_has_debugregs()) {
1321         return 0;
1322     }
1323
1324     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1325     if (ret < 0) {
1326         return ret;
1327     }
1328     for (i = 0; i < 4; i++) {
1329         env->dr[i] = dbgregs.db[i];
1330     }
1331     env->dr[4] = env->dr[6] = dbgregs.dr6;
1332     env->dr[5] = env->dr[7] = dbgregs.dr7;
1333 #endif
1334
1335     return 0;
1336 }
1337
1338 int kvm_arch_put_registers(CPUState *env, int level)
1339 {
1340     int ret;
1341
1342     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1343
1344     ret = kvm_getput_regs(env, 1);
1345     if (ret < 0) {
1346         return ret;
1347     }
1348     ret = kvm_put_xsave(env);
1349     if (ret < 0) {
1350         return ret;
1351     }
1352     ret = kvm_put_xcrs(env);
1353     if (ret < 0) {
1354         return ret;
1355     }
1356     ret = kvm_put_sregs(env);
1357     if (ret < 0) {
1358         return ret;
1359     }
1360     ret = kvm_put_msrs(env, level);
1361     if (ret < 0) {
1362         return ret;
1363     }
1364     if (level >= KVM_PUT_RESET_STATE) {
1365         ret = kvm_put_mp_state(env);
1366         if (ret < 0) {
1367             return ret;
1368         }
1369     }
1370     ret = kvm_put_vcpu_events(env, level);
1371     if (ret < 0) {
1372         return ret;
1373     }
1374     ret = kvm_put_debugregs(env);
1375     if (ret < 0) {
1376         return ret;
1377     }
1378     /* must be last */
1379     ret = kvm_guest_debug_workarounds(env);
1380     if (ret < 0) {
1381         return ret;
1382     }
1383     return 0;
1384 }
1385
1386 int kvm_arch_get_registers(CPUState *env)
1387 {
1388     int ret;
1389
1390     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1391
1392     ret = kvm_getput_regs(env, 0);
1393     if (ret < 0) {
1394         return ret;
1395     }
1396     ret = kvm_get_xsave(env);
1397     if (ret < 0) {
1398         return ret;
1399     }
1400     ret = kvm_get_xcrs(env);
1401     if (ret < 0) {
1402         return ret;
1403     }
1404     ret = kvm_get_sregs(env);
1405     if (ret < 0) {
1406         return ret;
1407     }
1408     ret = kvm_get_msrs(env);
1409     if (ret < 0) {
1410         return ret;
1411     }
1412     ret = kvm_get_mp_state(env);
1413     if (ret < 0) {
1414         return ret;
1415     }
1416     ret = kvm_get_vcpu_events(env);
1417     if (ret < 0) {
1418         return ret;
1419     }
1420     ret = kvm_get_debugregs(env);
1421     if (ret < 0) {
1422         return ret;
1423     }
1424     return 0;
1425 }
1426
1427 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1428 {
1429     /* Inject NMI */
1430     if (env->interrupt_request & CPU_INTERRUPT_NMI) {
1431         env->interrupt_request &= ~CPU_INTERRUPT_NMI;
1432         DPRINTF("injected NMI\n");
1433         kvm_vcpu_ioctl(env, KVM_NMI);
1434     }
1435
1436     /* Try to inject an interrupt if the guest can accept it */
1437     if (run->ready_for_interrupt_injection &&
1438         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1439         (env->eflags & IF_MASK)) {
1440         int irq;
1441
1442         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1443         irq = cpu_get_pic_interrupt(env);
1444         if (irq >= 0) {
1445             struct kvm_interrupt intr;
1446             intr.irq = irq;
1447             /* FIXME: errors */
1448             DPRINTF("injected interrupt %d\n", irq);
1449             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1450         }
1451     }
1452
1453     /* If we have an interrupt but the guest is not ready to receive an
1454      * interrupt, request an interrupt window exit.  This will
1455      * cause a return to userspace as soon as the guest is ready to
1456      * receive interrupts. */
1457     if ((env->interrupt_request & CPU_INTERRUPT_HARD)) {
1458         run->request_interrupt_window = 1;
1459     } else {
1460         run->request_interrupt_window = 0;
1461     }
1462
1463     DPRINTF("setting tpr\n");
1464     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1465
1466     return 0;
1467 }
1468
1469 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1470 {
1471     if (run->if_flag) {
1472         env->eflags |= IF_MASK;
1473     } else {
1474         env->eflags &= ~IF_MASK;
1475     }
1476     cpu_set_apic_tpr(env->apic_state, run->cr8);
1477     cpu_set_apic_base(env->apic_state, run->apic_base);
1478
1479     return 0;
1480 }
1481
1482 int kvm_arch_process_irqchip_events(CPUState *env)
1483 {
1484     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1485         kvm_cpu_synchronize_state(env);
1486         do_cpu_init(env);
1487         env->exception_index = EXCP_HALTED;
1488     }
1489
1490     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1491         kvm_cpu_synchronize_state(env);
1492         do_cpu_sipi(env);
1493     }
1494
1495     return env->halted;
1496 }
1497
1498 static int kvm_handle_halt(CPUState *env)
1499 {
1500     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1501           (env->eflags & IF_MASK)) &&
1502         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1503         env->halted = 1;
1504         env->exception_index = EXCP_HLT;
1505         return 0;
1506     }
1507
1508     return 1;
1509 }
1510
1511 static bool host_supports_vmx(void)
1512 {
1513     uint32_t ecx, unused;
1514
1515     host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
1516     return ecx & CPUID_EXT_VMX;
1517 }
1518
1519 #define VMX_INVALID_GUEST_STATE 0x80000021
1520
1521 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1522 {
1523     uint64_t code;
1524     int ret = 0;
1525
1526     switch (run->exit_reason) {
1527     case KVM_EXIT_HLT:
1528         DPRINTF("handle_hlt\n");
1529         ret = kvm_handle_halt(env);
1530         break;
1531     case KVM_EXIT_SET_TPR:
1532         ret = 1;
1533         break;
1534     case KVM_EXIT_FAIL_ENTRY:
1535         code = run->fail_entry.hardware_entry_failure_reason;
1536         fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
1537                 code);
1538         if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
1539             fprintf(stderr,
1540                     "\nIf you're runnning a guest on an Intel machine without "
1541                         "unrestricted mode\n"
1542                     "support, the failure can be most likely due to the guest "
1543                         "entering an invalid\n"
1544                     "state for Intel VT. For example, the guest maybe running "
1545                         "in big real mode\n"
1546                     "which is not supported on less recent Intel processors."
1547                         "\n\n");
1548         }
1549         ret = -1;
1550         break;
1551     case KVM_EXIT_EXCEPTION:
1552         fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
1553                 run->ex.exception, run->ex.error_code);
1554         ret = -1;
1555         break;
1556     default:
1557         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
1558         ret = -1;
1559         break;
1560     }
1561
1562     return ret;
1563 }
1564
1565 #ifdef KVM_CAP_SET_GUEST_DEBUG
1566 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1567 {
1568     static const uint8_t int3 = 0xcc;
1569
1570     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1571         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1)) {
1572         return -EINVAL;
1573     }
1574     return 0;
1575 }
1576
1577 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1578 {
1579     uint8_t int3;
1580
1581     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1582         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
1583         return -EINVAL;
1584     }
1585     return 0;
1586 }
1587
1588 static struct {
1589     target_ulong addr;
1590     int len;
1591     int type;
1592 } hw_breakpoint[4];
1593
1594 static int nb_hw_breakpoint;
1595
1596 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1597 {
1598     int n;
1599
1600     for (n = 0; n < nb_hw_breakpoint; n++) {
1601         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1602             (hw_breakpoint[n].len == len || len == -1)) {
1603             return n;
1604         }
1605     }
1606     return -1;
1607 }
1608
1609 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1610                                   target_ulong len, int type)
1611 {
1612     switch (type) {
1613     case GDB_BREAKPOINT_HW:
1614         len = 1;
1615         break;
1616     case GDB_WATCHPOINT_WRITE:
1617     case GDB_WATCHPOINT_ACCESS:
1618         switch (len) {
1619         case 1:
1620             break;
1621         case 2:
1622         case 4:
1623         case 8:
1624             if (addr & (len - 1)) {
1625                 return -EINVAL;
1626             }
1627             break;
1628         default:
1629             return -EINVAL;
1630         }
1631         break;
1632     default:
1633         return -ENOSYS;
1634     }
1635
1636     if (nb_hw_breakpoint == 4) {
1637         return -ENOBUFS;
1638     }
1639     if (find_hw_breakpoint(addr, len, type) >= 0) {
1640         return -EEXIST;
1641     }
1642     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1643     hw_breakpoint[nb_hw_breakpoint].len = len;
1644     hw_breakpoint[nb_hw_breakpoint].type = type;
1645     nb_hw_breakpoint++;
1646
1647     return 0;
1648 }
1649
1650 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1651                                   target_ulong len, int type)
1652 {
1653     int n;
1654
1655     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1656     if (n < 0) {
1657         return -ENOENT;
1658     }
1659     nb_hw_breakpoint--;
1660     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1661
1662     return 0;
1663 }
1664
1665 void kvm_arch_remove_all_hw_breakpoints(void)
1666 {
1667     nb_hw_breakpoint = 0;
1668 }
1669
1670 static CPUWatchpoint hw_watchpoint;
1671
1672 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1673 {
1674     int handle = 0;
1675     int n;
1676
1677     if (arch_info->exception == 1) {
1678         if (arch_info->dr6 & (1 << 14)) {
1679             if (cpu_single_env->singlestep_enabled) {
1680                 handle = 1;
1681             }
1682         } else {
1683             for (n = 0; n < 4; n++) {
1684                 if (arch_info->dr6 & (1 << n)) {
1685                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1686                     case 0x0:
1687                         handle = 1;
1688                         break;
1689                     case 0x1:
1690                         handle = 1;
1691                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1692                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1693                         hw_watchpoint.flags = BP_MEM_WRITE;
1694                         break;
1695                     case 0x3:
1696                         handle = 1;
1697                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1698                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1699                         hw_watchpoint.flags = BP_MEM_ACCESS;
1700                         break;
1701                     }
1702                 }
1703             }
1704         }
1705     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
1706         handle = 1;
1707     }
1708     if (!handle) {
1709         cpu_synchronize_state(cpu_single_env);
1710         assert(cpu_single_env->exception_injected == -1);
1711
1712         cpu_single_env->exception_injected = arch_info->exception;
1713         cpu_single_env->has_error_code = 0;
1714     }
1715
1716     return handle;
1717 }
1718
1719 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1720 {
1721     const uint8_t type_code[] = {
1722         [GDB_BREAKPOINT_HW] = 0x0,
1723         [GDB_WATCHPOINT_WRITE] = 0x1,
1724         [GDB_WATCHPOINT_ACCESS] = 0x3
1725     };
1726     const uint8_t len_code[] = {
1727         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1728     };
1729     int n;
1730
1731     if (kvm_sw_breakpoints_active(env)) {
1732         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1733     }
1734     if (nb_hw_breakpoint > 0) {
1735         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1736         dbg->arch.debugreg[7] = 0x0600;
1737         for (n = 0; n < nb_hw_breakpoint; n++) {
1738             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1739             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1740                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1741                 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
1742         }
1743     }
1744 }
1745 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1746
1747 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1748 {
1749     return !(env->cr[0] & CR0_PE_MASK) ||
1750            ((env->segs[R_CS].selector  & 3) != 3);
1751 }
1752
1753 static void hardware_memory_error(void)
1754 {
1755     fprintf(stderr, "Hardware memory error!\n");
1756     exit(1);
1757 }
1758
1759 #ifdef KVM_CAP_MCE
1760 static void kvm_mce_broadcast_rest(CPUState *env)
1761 {
1762     struct kvm_x86_mce mce = {
1763         .bank = 1,
1764         .status = MCI_STATUS_VAL | MCI_STATUS_UC,
1765         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1766         .addr = 0,
1767         .misc = 0,
1768     };
1769     CPUState *cenv;
1770
1771     /* Broadcast MCA signal for processor version 06H_EH and above */
1772     if (cpu_x86_support_mca_broadcast(env)) {
1773         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1774             if (cenv == env) {
1775                 continue;
1776             }
1777             kvm_inject_x86_mce_on(cenv, &mce, ABORT_ON_ERROR);
1778         }
1779     }
1780 }
1781
1782 static void kvm_mce_inj_srar_dataload(CPUState *env, target_phys_addr_t paddr)
1783 {
1784     struct kvm_x86_mce mce = {
1785         .bank = 9,
1786         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1787                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1788                   | MCI_STATUS_AR | 0x134,
1789         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV,
1790         .addr = paddr,
1791         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1792     };
1793     int r;
1794
1795     r = kvm_set_mce(env, &mce);
1796     if (r < 0) {
1797         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1798         abort();
1799     }
1800     kvm_mce_broadcast_rest(env);
1801 }
1802
1803 static void kvm_mce_inj_srao_memscrub(CPUState *env, target_phys_addr_t paddr)
1804 {
1805     struct kvm_x86_mce mce = {
1806         .bank = 9,
1807         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1808                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1809                   | 0xc0,
1810         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1811         .addr = paddr,
1812         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1813     };
1814     int r;
1815
1816     r = kvm_set_mce(env, &mce);
1817     if (r < 0) {
1818         fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1819         abort();
1820     }
1821     kvm_mce_broadcast_rest(env);
1822 }
1823
1824 static void kvm_mce_inj_srao_memscrub2(CPUState *env, target_phys_addr_t paddr)
1825 {
1826     struct kvm_x86_mce mce = {
1827         .bank = 9,
1828         .status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1829                   | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1830                   | 0xc0,
1831         .mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV,
1832         .addr = paddr,
1833         .misc = (MCM_ADDR_PHYS << 6) | 0xc,
1834     };
1835
1836     kvm_inject_x86_mce_on(env, &mce, ABORT_ON_ERROR);
1837     kvm_mce_broadcast_rest(env);
1838 }
1839
1840 #endif
1841
1842 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1843 {
1844 #if defined(KVM_CAP_MCE)
1845     void *vaddr;
1846     ram_addr_t ram_addr;
1847     target_phys_addr_t paddr;
1848
1849     if ((env->mcg_cap & MCG_SER_P) && addr
1850         && (code == BUS_MCEERR_AR
1851             || code == BUS_MCEERR_AO)) {
1852         vaddr = (void *)addr;
1853         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1854             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1855             fprintf(stderr, "Hardware memory error for memory used by "
1856                     "QEMU itself instead of guest system!\n");
1857             /* Hope we are lucky for AO MCE */
1858             if (code == BUS_MCEERR_AO) {
1859                 return 0;
1860             } else {
1861                 hardware_memory_error();
1862             }
1863         }
1864
1865         if (code == BUS_MCEERR_AR) {
1866             /* Fake an Intel architectural Data Load SRAR UCR */
1867             kvm_mce_inj_srar_dataload(env, paddr);
1868         } else {
1869             /*
1870              * If there is an MCE excpetion being processed, ignore
1871              * this SRAO MCE
1872              */
1873             if (!kvm_mce_in_progress(env)) {
1874                 /* Fake an Intel architectural Memory scrubbing UCR */
1875                 kvm_mce_inj_srao_memscrub(env, paddr);
1876             }
1877         }
1878     } else
1879 #endif
1880     {
1881         if (code == BUS_MCEERR_AO) {
1882             return 0;
1883         } else if (code == BUS_MCEERR_AR) {
1884             hardware_memory_error();
1885         } else {
1886             return 1;
1887         }
1888     }
1889     return 0;
1890 }
1891
1892 int kvm_on_sigbus(int code, void *addr)
1893 {
1894 #if defined(KVM_CAP_MCE)
1895     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1896         void *vaddr;
1897         ram_addr_t ram_addr;
1898         target_phys_addr_t paddr;
1899
1900         /* Hope we are lucky for AO MCE */
1901         vaddr = addr;
1902         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1903             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1904             fprintf(stderr, "Hardware memory error for memory used by "
1905                     "QEMU itself instead of guest system!: %p\n", addr);
1906             return 0;
1907         }
1908         kvm_mce_inj_srao_memscrub2(first_cpu, paddr);
1909     } else
1910 #endif
1911     {
1912         if (code == BUS_MCEERR_AO) {
1913             return 0;
1914         } else if (code == BUS_MCEERR_AR) {
1915             hardware_memory_error();
1916         } else {
1917             return 1;
1918         }
1919     }
1920     return 0;
1921 }