tcg/tcg-opc.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #ifndef DEF2
  25 #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0)
  26 #endif
  27
  28 /* predefined ops */
  29 DEF2(end, 0, 0, 0, 0) /* must be kept first */
  30 DEF2(nop, 0, 0, 0, 0)
  31 DEF2(nop1, 0, 0, 1, 0)
  32 DEF2(nop2, 0, 0, 2, 0)
  33 DEF2(nop3, 0, 0, 3, 0)
  34 DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */
  35
  36 DEF2(discard, 1, 0, 0, 0)
  37
  38 DEF2(set_label, 0, 0, 1, 0)
  39 DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
  40 DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  41 DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  42
  43 DEF2(mov_i32, 1, 1, 0, 0)
  44 DEF2(movi_i32, 1, 0, 1, 0)
  45 DEF2(setcond_i32, 1, 2, 1, 0)
  46 /* load/store */
  47 DEF2(ld8u_i32, 1, 1, 1, 0)
  48 DEF2(ld8s_i32, 1, 1, 1, 0)
  49 DEF2(ld16u_i32, 1, 1, 1, 0)
  50 DEF2(ld16s_i32, 1, 1, 1, 0)
  51 DEF2(ld_i32, 1, 1, 1, 0)
  52 DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  53 DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  54 DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
  55 /* arith */
  56 DEF2(add_i32, 1, 2, 0, 0)
  57 DEF2(sub_i32, 1, 2, 0, 0)
  58 DEF2(mul_i32, 1, 2, 0, 0)
  59 #ifdef TCG_TARGET_HAS_div_i32
  60 DEF2(div_i32, 1, 2, 0, 0)
  61 DEF2(divu_i32, 1, 2, 0, 0)
  62 DEF2(rem_i32, 1, 2, 0, 0)
  63 DEF2(remu_i32, 1, 2, 0, 0)
  64 #else
  65 DEF2(div2_i32, 2, 3, 0, 0)
  66 DEF2(divu2_i32, 2, 3, 0, 0)
  67 #endif
  68 DEF2(and_i32, 1, 2, 0, 0)
  69 DEF2(or_i32, 1, 2, 0, 0)
  70 DEF2(xor_i32, 1, 2, 0, 0)
  71 /* shifts/rotates */
  72 DEF2(shl_i32, 1, 2, 0, 0)
  73 DEF2(shr_i32, 1, 2, 0, 0)
  74 DEF2(sar_i32, 1, 2, 0, 0)
  75 #ifdef TCG_TARGET_HAS_rot_i32
  76 DEF2(rotl_i32, 1, 2, 0, 0)
  77 DEF2(rotr_i32, 1, 2, 0, 0)
  78 #endif
  79
  80 DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  81 #if TCG_TARGET_REG_BITS == 32
  82 DEF2(add2_i32, 2, 4, 0, 0)
  83 DEF2(sub2_i32, 2, 4, 0, 0)
  84 DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
  85 DEF2(mulu2_i32, 2, 2, 0, 0)
  86 DEF2(setcond2_i32, 1, 4, 1, 0)
  87 #endif
  88 #ifdef TCG_TARGET_HAS_ext8s_i32
  89 DEF2(ext8s_i32, 1, 1, 0, 0)
  90 #endif
  91 #ifdef TCG_TARGET_HAS_ext16s_i32
  92 DEF2(ext16s_i32, 1, 1, 0, 0)
  93 #endif
  94 #ifdef TCG_TARGET_HAS_ext8u_i32
  95 DEF2(ext8u_i32, 1, 1, 0, 0)
  96 #endif
  97 #ifdef TCG_TARGET_HAS_ext16u_i32
  98 DEF2(ext16u_i32, 1, 1, 0, 0)
  99 #endif
 100 #ifdef TCG_TARGET_HAS_bswap16_i32
 101 DEF2(bswap16_i32, 1, 1, 0, 0)
 102 #endif
 103 #ifdef TCG_TARGET_HAS_bswap32_i32
 104 DEF2(bswap32_i32, 1, 1, 0, 0)
 105 #endif
 106 #ifdef TCG_TARGET_HAS_not_i32
 107 DEF2(not_i32, 1, 1, 0, 0)
 108 #endif
 109 #ifdef TCG_TARGET_HAS_neg_i32
 110 DEF2(neg_i32, 1, 1, 0, 0)
 111 #endif
 112 #ifdef TCG_TARGET_HAS_andc_i32
 113 DEF2(andc_i32, 1, 2, 0, 0)
 114 #endif
 115 #ifdef TCG_TARGET_HAS_orc_i32
 116 DEF2(orc_i32, 1, 2, 0, 0)
 117 #endif
 118
 119 #if TCG_TARGET_REG_BITS == 64
 120 DEF2(mov_i64, 1, 1, 0, 0)
 121 DEF2(movi_i64, 1, 0, 1, 0)
 122 DEF2(setcond_i64, 1, 2, 1, 0)
 123 /* load/store */
 124 DEF2(ld8u_i64, 1, 1, 1, 0)
 125 DEF2(ld8s_i64, 1, 1, 1, 0)
 126 DEF2(ld16u_i64, 1, 1, 1, 0)
 127 DEF2(ld16s_i64, 1, 1, 1, 0)
 128 DEF2(ld32u_i64, 1, 1, 1, 0)
 129 DEF2(ld32s_i64, 1, 1, 1, 0)
 130 DEF2(ld_i64, 1, 1, 1, 0)
 131 DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 132 DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 133 DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 134 DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS)
 135 /* arith */
 136 DEF2(add_i64, 1, 2, 0, 0)
 137 DEF2(sub_i64, 1, 2, 0, 0)
 138 DEF2(mul_i64, 1, 2, 0, 0)
 139 #ifdef TCG_TARGET_HAS_div_i64
 140 DEF2(div_i64, 1, 2, 0, 0)
 141 DEF2(divu_i64, 1, 2, 0, 0)
 142 DEF2(rem_i64, 1, 2, 0, 0)
 143 DEF2(remu_i64, 1, 2, 0, 0)
 144 #else
 145 DEF2(div2_i64, 2, 3, 0, 0)
 146 DEF2(divu2_i64, 2, 3, 0, 0)
 147 #endif
 148 DEF2(and_i64, 1, 2, 0, 0)
 149 DEF2(or_i64, 1, 2, 0, 0)
 150 DEF2(xor_i64, 1, 2, 0, 0)
 151 /* shifts/rotates */
 152 DEF2(shl_i64, 1, 2, 0, 0)
 153 DEF2(shr_i64, 1, 2, 0, 0)
 154 DEF2(sar_i64, 1, 2, 0, 0)
 155 #ifdef TCG_TARGET_HAS_rot_i64
 156 DEF2(rotl_i64, 1, 2, 0, 0)
 157 DEF2(rotr_i64, 1, 2, 0, 0)
 158 #endif
 159
 160 DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 161 #ifdef TCG_TARGET_HAS_ext8s_i64
 162 DEF2(ext8s_i64, 1, 1, 0, 0)
 163 #endif
 164 #ifdef TCG_TARGET_HAS_ext16s_i64
 165 DEF2(ext16s_i64, 1, 1, 0, 0)
 166 #endif
 167 #ifdef TCG_TARGET_HAS_ext32s_i64
 168 DEF2(ext32s_i64, 1, 1, 0, 0)
 169 #endif
 170 #ifdef TCG_TARGET_HAS_ext8u_i64
 171 DEF2(ext8u_i64, 1, 1, 0, 0)
 172 #endif
 173 #ifdef TCG_TARGET_HAS_ext16u_i64
 174 DEF2(ext16u_i64, 1, 1, 0, 0)
 175 #endif
 176 #ifdef TCG_TARGET_HAS_ext32u_i64
 177 DEF2(ext32u_i64, 1, 1, 0, 0)
 178 #endif
 179 #ifdef TCG_TARGET_HAS_bswap16_i64
 180 DEF2(bswap16_i64, 1, 1, 0, 0)
 181 #endif
 182 #ifdef TCG_TARGET_HAS_bswap32_i64
 183 DEF2(bswap32_i64, 1, 1, 0, 0)
 184 #endif
 185 #ifdef TCG_TARGET_HAS_bswap64_i64
 186 DEF2(bswap64_i64, 1, 1, 0, 0)
 187 #endif
 188 #ifdef TCG_TARGET_HAS_not_i64
 189 DEF2(not_i64, 1, 1, 0, 0)
 190 #endif
 191 #ifdef TCG_TARGET_HAS_neg_i64
 192 DEF2(neg_i64, 1, 1, 0, 0)
 193 #endif
 194 #ifdef TCG_TARGET_HAS_andc_i64
 195 DEF2(andc_i64, 1, 2, 0, 0)
 196 #endif
 197 #ifdef TCG_TARGET_HAS_orc_i64
 198 DEF2(orc_i64, 1, 2, 0, 0)
 199 #endif
 200 #endif
 201
 202 /* QEMU specific */
 203 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
 204 DEF2(debug_insn_start, 0, 0, 2, 0)
 205 #else
 206 DEF2(debug_insn_start, 0, 0, 1, 0)
 207 #endif
 208 DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 209 DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
 210 /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
 211    constants must be defined */
 212 #if TCG_TARGET_REG_BITS == 32
 213 #if TARGET_LONG_BITS == 32
 214 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 215 #else
 216 DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 217 #endif
 218 #if TARGET_LONG_BITS == 32
 219 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 220 #else
 221 DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 222 #endif
 223 #if TARGET_LONG_BITS == 32
 224 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 225 #else
 226 DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 227 #endif
 228 #if TARGET_LONG_BITS == 32
 229 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 230 #else
 231 DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 232 #endif
 233 #if TARGET_LONG_BITS == 32
 234 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 235 #else
 236 DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 237 #endif
 238 #if TARGET_LONG_BITS == 32
 239 DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 240 #else
 241 DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 242 #endif
 243
 244 #if TARGET_LONG_BITS == 32
 245 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 246 #else
 247 DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 248 #endif
 249 #if TARGET_LONG_BITS == 32
 250 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 251 #else
 252 DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 253 #endif
 254 #if TARGET_LONG_BITS == 32
 255 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 256 #else
 257 DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 258 #endif
 259 #if TARGET_LONG_BITS == 32
 260 DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 261 #else
 262 DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 263 #endif
 264
 265 #else /* TCG_TARGET_REG_BITS == 32 */
 266
 267 DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 268 DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 269 DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 270 DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 271 DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 272 DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 273 DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 274
 275 DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 276 DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 277 DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 278 DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 279
 280 #endif /* TCG_TARGET_REG_BITS != 32 */
 281
 282 #undef DEF2