target-unicore32/cpu.h

   1 /*
   2  * UniCore32 virtual CPU header
   3  *
   4  * Copyright (C) 2010-2011 GUAN Xue-tao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef __CPU_UC32_H__
  11 #define __CPU_UC32_H__
  12
  13 #define TARGET_LONG_BITS                32
  14 #define TARGET_PAGE_BITS                12
  15
  16 #define TARGET_PHYS_ADDR_SPACE_BITS     32
  17 #define TARGET_VIRT_ADDR_SPACE_BITS     32
  18
  19 #define ELF_MACHINE             EM_UNICORE32
  20
  21 #define CPUState                struct CPUState_UniCore32
  22
  23 #include "cpu-defs.h"
  24 #include "softfloat.h"
  25
  26 #define NB_MMU_MODES            2
  27
  28 typedef struct CPUState_UniCore32 {
  29     /* Regs for current mode.  */
  30     uint32_t regs[32];
  31     /* Frequently accessed ASR bits are stored separately for efficiently.
  32        This contains all the other bits.  Use asr_{read,write} to access
  33        the whole ASR.  */
  34     uint32_t uncached_asr;
  35     uint32_t bsr;
  36
  37     /* Banked registers.  */
  38     uint32_t banked_bsr[6];
  39     uint32_t banked_r29[6];
  40     uint32_t banked_r30[6];
  41
  42     /* asr flag cache for faster execution */
  43     uint32_t CF; /* 0 or 1 */
  44     uint32_t VF; /* V is the bit 31. All other bits are undefined */
  45     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
  46     uint32_t ZF; /* Z set if zero.  */
  47
  48     /* System control coprocessor (cp0) */
  49     struct {
  50         uint32_t c0_cpuid;
  51         uint32_t c0_cachetype;
  52         uint32_t c1_sys; /* System control register.  */
  53         uint32_t c2_base; /* MMU translation table base.  */
  54         uint32_t c3_faultstatus; /* Fault status registers.  */
  55         uint32_t c4_faultaddr; /* Fault address registers.  */
  56         uint32_t c5_cacheop; /* Cache operation registers.  */
  57         uint32_t c6_tlbop; /* TLB operation registers. */
  58     } cp0;
  59
  60     /* UniCore-F64 coprocessor state.  */
  61     struct {
  62         float64 regs[16];
  63         uint32_t xregs[32];
  64         float_status fp_status;
  65     } ucf64;
  66
  67     CPU_COMMON
  68
  69     /* Internal CPU feature flags.  */
  70     uint32_t features;
  71
  72 } CPUState_UniCore32;
  73
  74 #define ASR_M                   (0x1f)
  75 #define ASR_MODE_USER           (0x10)
  76 #define ASR_MODE_INTR           (0x12)
  77 #define ASR_MODE_PRIV           (0x13)
  78 #define ASR_MODE_TRAP           (0x17)
  79 #define ASR_MODE_EXTN           (0x1b)
  80 #define ASR_MODE_SUSR           (0x1f)
  81 #define ASR_I                   (1 << 7)
  82 #define ASR_V                   (1 << 28)
  83 #define ASR_C                   (1 << 29)
  84 #define ASR_Z                   (1 << 30)
  85 #define ASR_N                   (1 << 31)
  86 #define ASR_NZCV                (ASR_N | ASR_Z | ASR_C | ASR_V)
  87 #define ASR_RESERVED            (~(ASR_M | ASR_I | ASR_NZCV))
  88
  89 #define UC32_EXCP_PRIV          (ASR_MODE_PRIV)
  90 #define UC32_EXCP_TRAP          (ASR_MODE_TRAP)
  91
  92 /* Return the current ASR value.  */
  93 target_ulong cpu_asr_read(CPUState *env1);
  94 /* Set the ASR.  Note that some bits of mask must be all-set or all-clear.  */
  95 void cpu_asr_write(CPUState *env1, target_ulong val, target_ulong mask);
  96
  97 /* UniCore-F64 system registers.  */
  98 #define UC32_UCF64_FPSCR                (31)
  99 #define UCF64_FPSCR_MASK                (0x27ffffff)
 100 #define UCF64_FPSCR_RND_MASK            (0x7)
 101 #define UCF64_FPSCR_RND(r)              (((r) >>  0) & UCF64_FPSCR_RND_MASK)
 102 #define UCF64_FPSCR_TRAPEN_MASK         (0x7f)
 103 #define UCF64_FPSCR_TRAPEN(r)           (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
 104 #define UCF64_FPSCR_FLAG_MASK           (0x3ff)
 105 #define UCF64_FPSCR_FLAG(r)             (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
 106 #define UCF64_FPSCR_FLAG_ZERO           (1 << 17)
 107 #define UCF64_FPSCR_FLAG_INFINITY       (1 << 18)
 108 #define UCF64_FPSCR_FLAG_INVALID        (1 << 19)
 109 #define UCF64_FPSCR_FLAG_UNDERFLOW      (1 << 20)
 110 #define UCF64_FPSCR_FLAG_OVERFLOW       (1 << 21)
 111 #define UCF64_FPSCR_FLAG_INEXACT        (1 << 22)
 112 #define UCF64_FPSCR_FLAG_HUGEINT        (1 << 23)
 113 #define UCF64_FPSCR_FLAG_DENORMAL       (1 << 24)
 114 #define UCF64_FPSCR_FLAG_UNIMP          (1 << 25)
 115 #define UCF64_FPSCR_FLAG_DIVZERO        (1 << 26)
 116
 117 #define UC32_HWCAP_CMOV                 4 /* 1 << 2 */
 118 #define UC32_HWCAP_UCF64                8 /* 1 << 3 */
 119
 120 #define UC32_CPUID(env)                 (env->cp0.c0_cpuid)
 121 #define UC32_CPUID_UCV2                 0x40010863
 122 #define UC32_CPUID_ANY                  0xffffffff
 123
 124 #define cpu_init                        uc32_cpu_init
 125 #define cpu_exec                        uc32_cpu_exec
 126 #define cpu_signal_handler              uc32_cpu_signal_handler
 127 #define cpu_handle_mmu_fault            uc32_cpu_handle_mmu_fault
 128
 129 CPUState *uc32_cpu_init(const char *cpu_model);
 130 int uc32_cpu_exec(CPUState *s);
 131 int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
 132 int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
 133                               int mmu_idx, int is_softmuu);
 134
 135 #define CPU_SAVE_VERSION 2
 136
 137 /* MMU modes definitions */
 138 #define MMU_MODE0_SUFFIX _kernel
 139 #define MMU_MODE1_SUFFIX _user
 140 #define MMU_USER_IDX 1
 141 static inline int cpu_mmu_index(CPUState *env)
 142 {
 143     return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
 144 }
 145
 146 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 147 {
 148     if (newsp) {
 149         env->regs[29] = newsp;
 150     }
 151     env->regs[0] = 0;
 152 }
 153
 154 static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
 155 {
 156     env->regs[16] = newtls;
 157 }
 158
 159 #include "cpu-all.h"
 160 #include "exec-all.h"
 161
 162 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 163 {
 164     env->regs[31] = tb->pc;
 165 }
 166
 167 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 168                                         target_ulong *cs_base, int *flags)
 169 {
 170     *pc = env->regs[31];
 171     *cs_base = 0;
 172     *flags = 0;
 173     if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
 174         *flags |= (1 << 6);
 175     }
 176 }
 177
 178 void uc32_translate_init(void);
 179 void do_interrupt(CPUState *);
 180 void switch_mode(CPUState_UniCore32 *, int);
 181
 182 static inline bool cpu_has_work(CPUState *env)
 183 {
 184     return env->interrupt_request &
 185         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 186 }
 187
 188 #endif /* __CPU_UC32_H__ */