target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25
  26 //#define DEBUG_KVM
  27
  28 #ifdef DEBUG_KVM
  29 #define dprintf(fmt, ...) \
  30     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  31 #else
  32 #define dprintf(fmt, ...) \
  33     do { } while (0)
  34 #endif
  35
  36 int kvm_arch_init_vcpu(CPUState *env)
  37 {
  38     struct {
  39         struct kvm_cpuid2 cpuid;
  40         struct kvm_cpuid_entry2 entries[100];
  41     } __attribute__((packed)) cpuid_data;
  42     uint32_t limit, i, j, cpuid_i;
  43     uint32_t unused;
  44
  45     cpuid_i = 0;
  46
  47     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
  48
  49     for (i = 0; i <= limit; i++) {
  50         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
  51
  52         switch (i) {
  53         case 2: {
  54             /* Keep reading function 2 till all the input is received */
  55             int times;
  56
  57             c->function = i;
  58             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
  59                        KVM_CPUID_FLAG_STATE_READ_NEXT;
  60             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  61             times = c->eax & 0xff;
  62
  63             for (j = 1; j < times; ++j) {
  64                 c = &cpuid_data.entries[cpuid_i++];
  65                 c->function = i;
  66                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
  67                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  68             }
  69             break;
  70         }
  71         case 4:
  72         case 0xb:
  73         case 0xd:
  74             for (j = 0; ; j++) {
  75                 c->function = i;
  76                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  77                 c->index = j;
  78                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
  79
  80                 if (i == 4 && c->eax == 0)
  81                     break;
  82                 if (i == 0xb && !(c->ecx & 0xff00))
  83                     break;
  84                 if (i == 0xd && c->eax == 0)
  85                     break;
  86
  87                 c = &cpuid_data.entries[cpuid_i++];
  88             }
  89             break;
  90         default:
  91             c->function = i;
  92             c->flags = 0;
  93             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
  94             break;
  95         }
  96     }
  97     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
  98
  99     for (i = 0x80000000; i <= limit; i++) {
 100         struct kvm_cpuid_entry2 *c = &cpuid_data.entries[cpuid_i++];
 101
 102         c->function = i;
 103         c->flags = 0;
 104         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 105     }
 106
 107     cpuid_data.cpuid.nent = cpuid_i;
 108
 109     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 110 }
 111
 112 static int kvm_has_msr_star(CPUState *env)
 113 {
 114     static int has_msr_star;
 115     int ret;
 116
 117     /* first time */
 118     if (has_msr_star == 0) {
 119         struct kvm_msr_list msr_list, *kvm_msr_list;
 120
 121         has_msr_star = -1;
 122
 123         /* Obtain MSR list from KVM.  These are the MSRs that we must
 124          * save/restore */
 125         msr_list.nmsrs = 0;
 126         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 127         if (ret < 0)
 128             return 0;
 129
 130         kvm_msr_list = qemu_mallocz(sizeof(msr_list) +
 131                                     msr_list.nmsrs * sizeof(msr_list.indices[0]));
 132
 133         kvm_msr_list->nmsrs = msr_list.nmsrs;
 134         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 135         if (ret >= 0) {
 136             int i;
 137
 138             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 139                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 140                     has_msr_star = 1;
 141                     break;
 142                 }
 143             }
 144         }
 145
 146         free(kvm_msr_list);
 147     }
 148
 149     if (has_msr_star == 1)
 150         return 1;
 151     return 0;
 152 }
 153
 154 int kvm_arch_init(KVMState *s, int smp_cpus)
 155 {
 156     int ret;
 157
 158     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 159      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 160      * must be part of guest physical memory, we need to allocate it.  Older
 161      * versions of KVM just assumed that it would be at the end of physical
 162      * memory but that doesn't work with more than 4GB of memory.  We simply
 163      * refuse to work with those older versions of KVM. */
 164     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 165     if (ret <= 0) {
 166         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 167         return ret;
 168     }
 169
 170     /* this address is 3 pages before the bios, and the bios should present
 171      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 172      * this?
 173      */
 174     return kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 175 }
 176
 177 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 178 {
 179     lhs->selector = rhs->selector;
 180     lhs->base = rhs->base;
 181     lhs->limit = rhs->limit;
 182     lhs->type = 3;
 183     lhs->present = 1;
 184     lhs->dpl = 3;
 185     lhs->db = 0;
 186     lhs->s = 1;
 187     lhs->l = 0;
 188     lhs->g = 0;
 189     lhs->avl = 0;
 190     lhs->unusable = 0;
 191 }
 192
 193 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 194 {
 195     unsigned flags = rhs->flags;
 196     lhs->selector = rhs->selector;
 197     lhs->base = rhs->base;
 198     lhs->limit = rhs->limit;
 199     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 200     lhs->present = (flags & DESC_P_MASK) != 0;
 201     lhs->dpl = rhs->selector & 3;
 202     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 203     lhs->s = (flags & DESC_S_MASK) != 0;
 204     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 205     lhs->g = (flags & DESC_G_MASK) != 0;
 206     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 207     lhs->unusable = 0;
 208 }
 209
 210 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 211 {
 212     lhs->selector = rhs->selector;
 213     lhs->base = rhs->base;
 214     lhs->limit = rhs->limit;
 215     lhs->flags =
 216         (rhs->type << DESC_TYPE_SHIFT)
 217         | (rhs->present * DESC_P_MASK)
 218         | (rhs->dpl << DESC_DPL_SHIFT)
 219         | (rhs->db << DESC_B_SHIFT)
 220         | (rhs->s * DESC_S_MASK)
 221         | (rhs->l << DESC_L_SHIFT)
 222         | (rhs->g * DESC_G_MASK)
 223         | (rhs->avl * DESC_AVL_MASK);
 224 }
 225
 226 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 227 {
 228     if (set)
 229         *kvm_reg = *qemu_reg;
 230     else
 231         *qemu_reg = *kvm_reg;
 232 }
 233
 234 static int kvm_getput_regs(CPUState *env, int set)
 235 {
 236     struct kvm_regs regs;
 237     int ret = 0;
 238
 239     if (!set) {
 240         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 241         if (ret < 0)
 242             return ret;
 243     }
 244
 245     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 246     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 247     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 248     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 249     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 250     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 251     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 252     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 253 #ifdef TARGET_X86_64
 254     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 255     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 256     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 257     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 258     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 259     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 260     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 261     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 262 #endif
 263
 264     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 265     kvm_getput_reg(&regs.rip, &env->eip, set);
 266
 267     if (set)
 268         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 269
 270     return ret;
 271 }
 272
 273 static int kvm_put_fpu(CPUState *env)
 274 {
 275     struct kvm_fpu fpu;
 276     int i;
 277
 278     memset(&fpu, 0, sizeof fpu);
 279     fpu.fsw = env->fpus & ~(7 << 11);
 280     fpu.fsw |= (env->fpstt & 7) << 11;
 281     fpu.fcw = env->fpuc;
 282     for (i = 0; i < 8; ++i)
 283         fpu.ftwx |= (!env->fptags[i]) << i;
 284     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 285     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 286     fpu.mxcsr = env->mxcsr;
 287
 288     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 289 }
 290
 291 static int kvm_put_sregs(CPUState *env)
 292 {
 293     struct kvm_sregs sregs;
 294
 295     memcpy(sregs.interrupt_bitmap,
 296            env->interrupt_bitmap,
 297            sizeof(sregs.interrupt_bitmap));
 298
 299     if ((env->eflags & VM_MASK)) {
 300             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 301             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 302             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 303             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 304             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 305             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 306     } else {
 307             set_seg(&sregs.cs, &env->segs[R_CS]);
 308             set_seg(&sregs.ds, &env->segs[R_DS]);
 309             set_seg(&sregs.es, &env->segs[R_ES]);
 310             set_seg(&sregs.fs, &env->segs[R_FS]);
 311             set_seg(&sregs.gs, &env->segs[R_GS]);
 312             set_seg(&sregs.ss, &env->segs[R_SS]);
 313
 314             if (env->cr[0] & CR0_PE_MASK) {
 315                 /* force ss cpl to cs cpl */
 316                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 317                         (sregs.cs.selector & 3);
 318                 sregs.ss.dpl = sregs.ss.selector & 3;
 319             }
 320     }
 321
 322     set_seg(&sregs.tr, &env->tr);
 323     set_seg(&sregs.ldt, &env->ldt);
 324
 325     sregs.idt.limit = env->idt.limit;
 326     sregs.idt.base = env->idt.base;
 327     sregs.gdt.limit = env->gdt.limit;
 328     sregs.gdt.base = env->gdt.base;
 329
 330     sregs.cr0 = env->cr[0];
 331     sregs.cr2 = env->cr[2];
 332     sregs.cr3 = env->cr[3];
 333     sregs.cr4 = env->cr[4];
 334
 335     sregs.cr8 = cpu_get_apic_tpr(env);
 336     sregs.apic_base = cpu_get_apic_base(env);
 337
 338     sregs.efer = env->efer;
 339
 340     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 341 }
 342
 343 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 344                               uint32_t index, uint64_t value)
 345 {
 346     entry->index = index;
 347     entry->data = value;
 348 }
 349
 350 static int kvm_put_msrs(CPUState *env)
 351 {
 352     struct {
 353         struct kvm_msrs info;
 354         struct kvm_msr_entry entries[100];
 355     } msr_data;
 356     struct kvm_msr_entry *msrs = msr_data.entries;
 357     int n = 0;
 358
 359     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 360     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 361     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 362     if (kvm_has_msr_star(env))
 363         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 364     kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 365 #ifdef TARGET_X86_64
 366     /* FIXME if lm capable */
 367     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 368     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 369     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 370     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 371 #endif
 372     msr_data.info.nmsrs = n;
 373
 374     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 375
 376 }
 377
 378
 379 static int kvm_get_fpu(CPUState *env)
 380 {
 381     struct kvm_fpu fpu;
 382     int i, ret;
 383
 384     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 385     if (ret < 0)
 386         return ret;
 387
 388     env->fpstt = (fpu.fsw >> 11) & 7;
 389     env->fpus = fpu.fsw;
 390     env->fpuc = fpu.fcw;
 391     for (i = 0; i < 8; ++i)
 392         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 393     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 394     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 395     env->mxcsr = fpu.mxcsr;
 396
 397     return 0;
 398 }
 399
 400 static int kvm_get_sregs(CPUState *env)
 401 {
 402     struct kvm_sregs sregs;
 403     uint32_t hflags;
 404     int ret;
 405
 406     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 407     if (ret < 0)
 408         return ret;
 409
 410     memcpy(env->interrupt_bitmap,
 411            sregs.interrupt_bitmap,
 412            sizeof(sregs.interrupt_bitmap));
 413
 414     get_seg(&env->segs[R_CS], &sregs.cs);
 415     get_seg(&env->segs[R_DS], &sregs.ds);
 416     get_seg(&env->segs[R_ES], &sregs.es);
 417     get_seg(&env->segs[R_FS], &sregs.fs);
 418     get_seg(&env->segs[R_GS], &sregs.gs);
 419     get_seg(&env->segs[R_SS], &sregs.ss);
 420
 421     get_seg(&env->tr, &sregs.tr);
 422     get_seg(&env->ldt, &sregs.ldt);
 423
 424     env->idt.limit = sregs.idt.limit;
 425     env->idt.base = sregs.idt.base;
 426     env->gdt.limit = sregs.gdt.limit;
 427     env->gdt.base = sregs.gdt.base;
 428
 429     env->cr[0] = sregs.cr0;
 430     env->cr[2] = sregs.cr2;
 431     env->cr[3] = sregs.cr3;
 432     env->cr[4] = sregs.cr4;
 433
 434     cpu_set_apic_base(env, sregs.apic_base);
 435
 436     env->efer = sregs.efer;
 437     //cpu_set_apic_tpr(env, sregs.cr8);
 438
 439 #define HFLAG_COPY_MASK ~( \
 440                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 441                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 442                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 443                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 444
 445
 446
 447     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 448     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 449     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 450             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 451     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 452     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 453             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 454
 455     if (env->efer & MSR_EFER_LMA) {
 456         hflags |= HF_LMA_MASK;
 457     }
 458
 459     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 460         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 461     } else {
 462         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 463                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 464         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 465                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 466         if (!(env->cr[0] & CR0_PE_MASK) ||
 467                    (env->eflags & VM_MASK) ||
 468                    !(hflags & HF_CS32_MASK)) {
 469                 hflags |= HF_ADDSEG_MASK;
 470             } else {
 471                 hflags |= ((env->segs[R_DS].base |
 472                                 env->segs[R_ES].base |
 473                                 env->segs[R_SS].base) != 0) <<
 474                     HF_ADDSEG_SHIFT;
 475             }
 476     }
 477     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 478
 479     return 0;
 480 }
 481
 482 static int kvm_get_msrs(CPUState *env)
 483 {
 484     struct {
 485         struct kvm_msrs info;
 486         struct kvm_msr_entry entries[100];
 487     } msr_data;
 488     struct kvm_msr_entry *msrs = msr_data.entries;
 489     int ret, i, n;
 490
 491     n = 0;
 492     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 493     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 494     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 495     if (kvm_has_msr_star(env))
 496         msrs[n++].index = MSR_STAR;
 497     msrs[n++].index = MSR_IA32_TSC;
 498 #ifdef TARGET_X86_64
 499     /* FIXME lm_capable_kernel */
 500     msrs[n++].index = MSR_CSTAR;
 501     msrs[n++].index = MSR_KERNELGSBASE;
 502     msrs[n++].index = MSR_FMASK;
 503     msrs[n++].index = MSR_LSTAR;
 504 #endif
 505     msr_data.info.nmsrs = n;
 506     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 507     if (ret < 0)
 508         return ret;
 509
 510     for (i = 0; i < ret; i++) {
 511         switch (msrs[i].index) {
 512         case MSR_IA32_SYSENTER_CS:
 513             env->sysenter_cs = msrs[i].data;
 514             break;
 515         case MSR_IA32_SYSENTER_ESP:
 516             env->sysenter_esp = msrs[i].data;
 517             break;
 518         case MSR_IA32_SYSENTER_EIP:
 519             env->sysenter_eip = msrs[i].data;
 520             break;
 521         case MSR_STAR:
 522             env->star = msrs[i].data;
 523             break;
 524 #ifdef TARGET_X86_64
 525         case MSR_CSTAR:
 526             env->cstar = msrs[i].data;
 527             break;
 528         case MSR_KERNELGSBASE:
 529             env->kernelgsbase = msrs[i].data;
 530             break;
 531         case MSR_FMASK:
 532             env->fmask = msrs[i].data;
 533             break;
 534         case MSR_LSTAR:
 535             env->lstar = msrs[i].data;
 536             break;
 537 #endif
 538         case MSR_IA32_TSC:
 539             env->tsc = msrs[i].data;
 540             break;
 541         }
 542     }
 543
 544     return 0;
 545 }
 546
 547 int kvm_arch_put_registers(CPUState *env)
 548 {
 549     int ret;
 550
 551     ret = kvm_getput_regs(env, 1);
 552     if (ret < 0)
 553         return ret;
 554
 555     ret = kvm_put_fpu(env);
 556     if (ret < 0)
 557         return ret;
 558
 559     ret = kvm_put_sregs(env);
 560     if (ret < 0)
 561         return ret;
 562
 563     ret = kvm_put_msrs(env);
 564     if (ret < 0)
 565         return ret;
 566
 567     return 0;
 568 }
 569
 570 int kvm_arch_get_registers(CPUState *env)
 571 {
 572     int ret;
 573
 574     ret = kvm_getput_regs(env, 0);
 575     if (ret < 0)
 576         return ret;
 577
 578     ret = kvm_get_fpu(env);
 579     if (ret < 0)
 580         return ret;
 581
 582     ret = kvm_get_sregs(env);
 583     if (ret < 0)
 584         return ret;
 585
 586     ret = kvm_get_msrs(env);
 587     if (ret < 0)
 588         return ret;
 589
 590     return 0;
 591 }
 592
 593 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
 594 {
 595     /* Try to inject an interrupt if the guest can accept it */
 596     if (run->ready_for_interrupt_injection &&
 597         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 598         (env->eflags & IF_MASK)) {
 599         int irq;
 600
 601         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 602         irq = cpu_get_pic_interrupt(env);
 603         if (irq >= 0) {
 604             struct kvm_interrupt intr;
 605             intr.irq = irq;
 606             /* FIXME: errors */
 607             dprintf("injected interrupt %d\n", irq);
 608             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
 609         }
 610     }
 611
 612     /* If we have an interrupt but the guest is not ready to receive an
 613      * interrupt, request an interrupt window exit.  This will
 614      * cause a return to userspace as soon as the guest is ready to
 615      * receive interrupts. */
 616     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
 617         run->request_interrupt_window = 1;
 618     else
 619         run->request_interrupt_window = 0;
 620
 621     dprintf("setting tpr\n");
 622     run->cr8 = cpu_get_apic_tpr(env);
 623
 624     return 0;
 625 }
 626
 627 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
 628 {
 629     if (run->if_flag)
 630         env->eflags |= IF_MASK;
 631     else
 632         env->eflags &= ~IF_MASK;
 633
 634     cpu_set_apic_tpr(env, run->cr8);
 635     cpu_set_apic_base(env, run->apic_base);
 636
 637     return 0;
 638 }
 639
 640 static int kvm_handle_halt(CPUState *env)
 641 {
 642     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 643           (env->eflags & IF_MASK)) &&
 644         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 645         env->halted = 1;
 646         env->exception_index = EXCP_HLT;
 647         return 0;
 648     }
 649
 650     return 1;
 651 }
 652
 653 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
 654 {
 655     int ret = 0;
 656
 657     switch (run->exit_reason) {
 658     case KVM_EXIT_HLT:
 659         dprintf("handle_hlt\n");
 660         ret = kvm_handle_halt(env);
 661         break;
 662     }
 663
 664     return ret;
 665 }