hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "apic.h"
  29 #include "isa.h"
  30 #include "hpet_emul.h"
  31 #include "mc146818rtc.h"
  32
  33 //#define DEBUG_CMOS
  34
  35 #ifdef DEBUG_CMOS
  36 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  37 #else
  38 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  39 #endif
  40
  41 #define RTC_REINJECT_ON_ACK_COUNT 20
  42
  43 #define RTC_SECONDS             0
  44 #define RTC_SECONDS_ALARM       1
  45 #define RTC_MINUTES             2
  46 #define RTC_MINUTES_ALARM       3
  47 #define RTC_HOURS               4
  48 #define RTC_HOURS_ALARM         5
  49 #define RTC_ALARM_DONT_CARE    0xC0
  50
  51 #define RTC_DAY_OF_WEEK         6
  52 #define RTC_DAY_OF_MONTH        7
  53 #define RTC_MONTH               8
  54 #define RTC_YEAR                9
  55
  56 #define RTC_REG_A               10
  57 #define RTC_REG_B               11
  58 #define RTC_REG_C               12
  59 #define RTC_REG_D               13
  60
  61 #define REG_A_UIP 0x80
  62
  63 #define REG_B_SET  0x80
  64 #define REG_B_PIE  0x40
  65 #define REG_B_AIE  0x20
  66 #define REG_B_UIE  0x10
  67 #define REG_B_SQWE 0x08
  68 #define REG_B_DM   0x04
  69
  70 #define REG_C_UF   0x10
  71 #define REG_C_IRQF 0x80
  72 #define REG_C_PF   0x40
  73 #define REG_C_AF   0x20
  74
  75 typedef struct RTCState {
  76     ISADevice dev;
  77     uint8_t cmos_data[128];
  78     uint8_t cmos_index;
  79     struct tm current_tm;
  80     int32_t base_year;
  81     qemu_irq irq;
  82     qemu_irq sqw_irq;
  83     int it_shift;
  84     /* periodic timer */
  85     QEMUTimer *periodic_timer;
  86     int64_t next_periodic_time;
  87     /* second update */
  88     int64_t next_second_time;
  89     uint16_t irq_reinject_on_ack_count;
  90     uint32_t irq_coalesced;
  91     uint32_t period;
  92     QEMUTimer *coalesced_timer;
  93     QEMUTimer *second_timer;
  94     QEMUTimer *second_timer2;
  95 } RTCState;
  96
  97 static void rtc_irq_raise(qemu_irq irq)
  98 {
  99     /* When HPET is operating in legacy mode, RTC interrupts are disabled
 100      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
 101      * mode is established while interrupt is raised. We want it to
 102      * be lowered in any case
 103      */
 104 #if defined TARGET_I386
 105     if (!hpet_in_legacy_mode())
 106 #endif
 107         qemu_irq_raise(irq);
 108 }
 109
 110 static void rtc_set_time(RTCState *s);
 111 static void rtc_copy_date(RTCState *s);
 112
 113 #ifdef TARGET_I386
 114 static void rtc_coalesced_timer_update(RTCState *s)
 115 {
 116     if (s->irq_coalesced == 0) {
 117         qemu_del_timer(s->coalesced_timer);
 118     } else {
 119         /* divide each RTC interval to 2 - 8 smaller intervals */
 120         int c = MIN(s->irq_coalesced, 7) + 1;
 121         int64_t next_clock = qemu_get_clock(rtc_clock) +
 122             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 123         qemu_mod_timer(s->coalesced_timer, next_clock);
 124     }
 125 }
 126
 127 static void rtc_coalesced_timer(void *opaque)
 128 {
 129     RTCState *s = opaque;
 130
 131     if (s->irq_coalesced != 0) {
 132         apic_reset_irq_delivered();
 133         s->cmos_data[RTC_REG_C] |= 0xc0;
 134         rtc_irq_raise(s->irq);
 135         if (apic_get_irq_delivered()) {
 136             s->irq_coalesced--;
 137         }
 138     }
 139
 140     rtc_coalesced_timer_update(s);
 141 }
 142 #endif
 143
 144 static void rtc_timer_update(RTCState *s, int64_t current_time)
 145 {
 146     int period_code, period;
 147     int64_t cur_clock, next_irq_clock;
 148     int enable_pie;
 149
 150     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 151 #if defined TARGET_I386
 152     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 153      * disabled anyway.
 154      */
 155     enable_pie = !hpet_in_legacy_mode();
 156 #else
 157     enable_pie = 1;
 158 #endif
 159     if (period_code != 0
 160         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 161             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 162         if (period_code <= 2)
 163             period_code += 7;
 164         /* period in 32 Khz cycles */
 165         period = 1 << (period_code - 1);
 166 #ifdef TARGET_I386
 167         if(period != s->period)
 168             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 169         s->period = period;
 170 #endif
 171         /* compute 32 khz clock */
 172         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 173         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 174         s->next_periodic_time =
 175             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 176         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 177     } else {
 178 #ifdef TARGET_I386
 179         s->irq_coalesced = 0;
 180 #endif
 181         qemu_del_timer(s->periodic_timer);
 182     }
 183 }
 184
 185 static void rtc_periodic_timer(void *opaque)
 186 {
 187     RTCState *s = opaque;
 188
 189     rtc_timer_update(s, s->next_periodic_time);
 190     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 191         s->cmos_data[RTC_REG_C] |= 0xc0;
 192 #ifdef TARGET_I386
 193         if(rtc_td_hack) {
 194             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 195                 s->irq_reinject_on_ack_count = 0;
 196             apic_reset_irq_delivered();
 197             rtc_irq_raise(s->irq);
 198             if (!apic_get_irq_delivered()) {
 199                 s->irq_coalesced++;
 200                 rtc_coalesced_timer_update(s);
 201             }
 202         } else
 203 #endif
 204         rtc_irq_raise(s->irq);
 205     }
 206     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 207         /* Not square wave at all but we don't want 2048Hz interrupts!
 208            Must be seen as a pulse.  */
 209         qemu_irq_raise(s->sqw_irq);
 210     }
 211 }
 212
 213 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 214 {
 215     RTCState *s = opaque;
 216
 217     if ((addr & 1) == 0) {
 218         s->cmos_index = data & 0x7f;
 219     } else {
 220         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02x\n",
 221                      s->cmos_index, data);
 222         switch(s->cmos_index) {
 223         case RTC_SECONDS_ALARM:
 224         case RTC_MINUTES_ALARM:
 225         case RTC_HOURS_ALARM:
 226             /* XXX: not supported */
 227             s->cmos_data[s->cmos_index] = data;
 228             break;
 229         case RTC_SECONDS:
 230         case RTC_MINUTES:
 231         case RTC_HOURS:
 232         case RTC_DAY_OF_WEEK:
 233         case RTC_DAY_OF_MONTH:
 234         case RTC_MONTH:
 235         case RTC_YEAR:
 236             s->cmos_data[s->cmos_index] = data;
 237             /* if in set mode, do not update the time */
 238             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 239                 rtc_set_time(s);
 240             }
 241             break;
 242         case RTC_REG_A:
 243             /* UIP bit is read only */
 244             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 245                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 246             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 247             break;
 248         case RTC_REG_B:
 249             if (data & REG_B_SET) {
 250                 /* set mode: reset UIP mode */
 251                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 252                 data &= ~REG_B_UIE;
 253             } else {
 254                 /* if disabling set mode, update the time */
 255                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 256                     rtc_set_time(s);
 257                 }
 258             }
 259             s->cmos_data[RTC_REG_B] = data;
 260             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 261             break;
 262         case RTC_REG_C:
 263         case RTC_REG_D:
 264             /* cannot write to them */
 265             break;
 266         default:
 267             s->cmos_data[s->cmos_index] = data;
 268             break;
 269         }
 270     }
 271 }
 272
 273 static inline int rtc_to_bcd(RTCState *s, int a)
 274 {
 275     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 276         return a;
 277     } else {
 278         return ((a / 10) << 4) | (a % 10);
 279     }
 280 }
 281
 282 static inline int rtc_from_bcd(RTCState *s, int a)
 283 {
 284     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 285         return a;
 286     } else {
 287         return ((a >> 4) * 10) + (a & 0x0f);
 288     }
 289 }
 290
 291 static void rtc_set_time(RTCState *s)
 292 {
 293     struct tm *tm = &s->current_tm;
 294
 295     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 296     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 297     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 298     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 299         (s->cmos_data[RTC_HOURS] & 0x80)) {
 300         tm->tm_hour += 12;
 301     }
 302     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 303     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 304     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 305     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 306
 307     rtc_change_mon_event(tm);
 308 }
 309
 310 static void rtc_copy_date(RTCState *s)
 311 {
 312     const struct tm *tm = &s->current_tm;
 313     int year;
 314
 315     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 316     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 317     if (s->cmos_data[RTC_REG_B] & 0x02) {
 318         /* 24 hour format */
 319         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 320     } else {
 321         /* 12 hour format */
 322         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 323         if (tm->tm_hour >= 12)
 324             s->cmos_data[RTC_HOURS] |= 0x80;
 325     }
 326     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 327     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 328     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 329     year = (tm->tm_year - s->base_year) % 100;
 330     if (year < 0)
 331         year += 100;
 332     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 333 }
 334
 335 /* month is between 0 and 11. */
 336 static int get_days_in_month(int month, int year)
 337 {
 338     static const int days_tab[12] = {
 339         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 340     };
 341     int d;
 342     if ((unsigned )month >= 12)
 343         return 31;
 344     d = days_tab[month];
 345     if (month == 1) {
 346         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 347             d++;
 348     }
 349     return d;
 350 }
 351
 352 /* update 'tm' to the next second */
 353 static void rtc_next_second(struct tm *tm)
 354 {
 355     int days_in_month;
 356
 357     tm->tm_sec++;
 358     if ((unsigned)tm->tm_sec >= 60) {
 359         tm->tm_sec = 0;
 360         tm->tm_min++;
 361         if ((unsigned)tm->tm_min >= 60) {
 362             tm->tm_min = 0;
 363             tm->tm_hour++;
 364             if ((unsigned)tm->tm_hour >= 24) {
 365                 tm->tm_hour = 0;
 366                 /* next day */
 367                 tm->tm_wday++;
 368                 if ((unsigned)tm->tm_wday >= 7)
 369                     tm->tm_wday = 0;
 370                 days_in_month = get_days_in_month(tm->tm_mon,
 371                                                   tm->tm_year + 1900);
 372                 tm->tm_mday++;
 373                 if (tm->tm_mday < 1) {
 374                     tm->tm_mday = 1;
 375                 } else if (tm->tm_mday > days_in_month) {
 376                     tm->tm_mday = 1;
 377                     tm->tm_mon++;
 378                     if (tm->tm_mon >= 12) {
 379                         tm->tm_mon = 0;
 380                         tm->tm_year++;
 381                     }
 382                 }
 383             }
 384         }
 385     }
 386 }
 387
 388
 389 static void rtc_update_second(void *opaque)
 390 {
 391     RTCState *s = opaque;
 392     int64_t delay;
 393
 394     /* if the oscillator is not in normal operation, we do not update */
 395     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 396         s->next_second_time += get_ticks_per_sec();
 397         qemu_mod_timer(s->second_timer, s->next_second_time);
 398     } else {
 399         rtc_next_second(&s->current_tm);
 400
 401         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 402             /* update in progress bit */
 403             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 404         }
 405         /* should be 244 us = 8 / 32768 seconds, but currently the
 406            timers do not have the necessary resolution. */
 407         delay = (get_ticks_per_sec() * 1) / 100;
 408         if (delay < 1)
 409             delay = 1;
 410         qemu_mod_timer(s->second_timer2,
 411                        s->next_second_time + delay);
 412     }
 413 }
 414
 415 static void rtc_update_second2(void *opaque)
 416 {
 417     RTCState *s = opaque;
 418
 419     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 420         rtc_copy_date(s);
 421     }
 422
 423     /* check alarm */
 424     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 425         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 426              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 427             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 428              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 429             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 430              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 431
 432             s->cmos_data[RTC_REG_C] |= 0xa0;
 433             rtc_irq_raise(s->irq);
 434         }
 435     }
 436
 437     /* update ended interrupt */
 438     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 439     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 440       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 441       rtc_irq_raise(s->irq);
 442     }
 443
 444     /* clear update in progress bit */
 445     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 446
 447     s->next_second_time += get_ticks_per_sec();
 448     qemu_mod_timer(s->second_timer, s->next_second_time);
 449 }
 450
 451 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 452 {
 453     RTCState *s = opaque;
 454     int ret;
 455     if ((addr & 1) == 0) {
 456         return 0xff;
 457     } else {
 458         switch(s->cmos_index) {
 459         case RTC_SECONDS:
 460         case RTC_MINUTES:
 461         case RTC_HOURS:
 462         case RTC_DAY_OF_WEEK:
 463         case RTC_DAY_OF_MONTH:
 464         case RTC_MONTH:
 465         case RTC_YEAR:
 466             ret = s->cmos_data[s->cmos_index];
 467             break;
 468         case RTC_REG_A:
 469             ret = s->cmos_data[s->cmos_index];
 470             break;
 471         case RTC_REG_C:
 472             ret = s->cmos_data[s->cmos_index];
 473             qemu_irq_lower(s->irq);
 474 #ifdef TARGET_I386
 475             if(s->irq_coalesced &&
 476                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 477                 s->irq_reinject_on_ack_count++;
 478                 apic_reset_irq_delivered();
 479                 qemu_irq_raise(s->irq);
 480                 if (apic_get_irq_delivered())
 481                     s->irq_coalesced--;
 482                 break;
 483             }
 484 #endif
 485
 486             s->cmos_data[RTC_REG_C] = 0x00;
 487             break;
 488         default:
 489             ret = s->cmos_data[s->cmos_index];
 490             break;
 491         }
 492         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 493                      s->cmos_index, ret);
 494         return ret;
 495     }
 496 }
 497
 498 void rtc_set_memory(ISADevice *dev, int addr, int val)
 499 {
 500     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 501     if (addr >= 0 && addr <= 127)
 502         s->cmos_data[addr] = val;
 503 }
 504
 505 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 506 {
 507     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 508     s->current_tm = *tm;
 509     rtc_copy_date(s);
 510 }
 511
 512 /* PC cmos mappings */
 513 #define REG_IBM_CENTURY_BYTE        0x32
 514 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 515
 516 static void rtc_set_date_from_host(ISADevice *dev)
 517 {
 518     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 519     struct tm tm;
 520     int val;
 521
 522     /* set the CMOS date */
 523     qemu_get_timedate(&tm, 0);
 524     rtc_set_date(dev, &tm);
 525
 526     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 527     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 528     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 529 }
 530
 531 static int rtc_post_load(void *opaque, int version_id)
 532 {
 533 #ifdef TARGET_I386
 534     RTCState *s = opaque;
 535
 536     if (version_id >= 2) {
 537         if (rtc_td_hack) {
 538             rtc_coalesced_timer_update(s);
 539         }
 540     }
 541 #endif
 542     return 0;
 543 }
 544
 545 static const VMStateDescription vmstate_rtc = {
 546     .name = "mc146818rtc",
 547     .version_id = 2,
 548     .minimum_version_id = 1,
 549     .minimum_version_id_old = 1,
 550     .post_load = rtc_post_load,
 551     .fields      = (VMStateField []) {
 552         VMSTATE_BUFFER(cmos_data, RTCState),
 553         VMSTATE_UINT8(cmos_index, RTCState),
 554         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 555         VMSTATE_INT32(current_tm.tm_min, RTCState),
 556         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 557         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 558         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 559         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 560         VMSTATE_INT32(current_tm.tm_year, RTCState),
 561         VMSTATE_TIMER(periodic_timer, RTCState),
 562         VMSTATE_INT64(next_periodic_time, RTCState),
 563         VMSTATE_INT64(next_second_time, RTCState),
 564         VMSTATE_TIMER(second_timer, RTCState),
 565         VMSTATE_TIMER(second_timer2, RTCState),
 566         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 567         VMSTATE_UINT32_V(period, RTCState, 2),
 568         VMSTATE_END_OF_LIST()
 569     }
 570 };
 571
 572 static void rtc_reset(void *opaque)
 573 {
 574     RTCState *s = opaque;
 575
 576     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 577     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 578
 579     qemu_irq_lower(s->irq);
 580
 581 #ifdef TARGET_I386
 582     if (rtc_td_hack)
 583             s->irq_coalesced = 0;
 584 #endif
 585 }
 586
 587 static int rtc_initfn(ISADevice *dev)
 588 {
 589     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 590     int base = 0x70;
 591     int isairq = 8;
 592
 593     isa_init_irq(dev, &s->irq, isairq);
 594
 595     s->cmos_data[RTC_REG_A] = 0x26;
 596     s->cmos_data[RTC_REG_B] = 0x02;
 597     s->cmos_data[RTC_REG_C] = 0x00;
 598     s->cmos_data[RTC_REG_D] = 0x80;
 599
 600     rtc_set_date_from_host(dev);
 601
 602     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 603 #ifdef TARGET_I386
 604     if (rtc_td_hack)
 605         s->coalesced_timer =
 606             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 607 #endif
 608     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 609     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 610
 611     s->next_second_time =
 612         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 613     qemu_mod_timer(s->second_timer2, s->next_second_time);
 614
 615     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 616     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 617
 618     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 619     qemu_register_reset(rtc_reset, s);
 620     return 0;
 621 }
 622
 623 ISADevice *rtc_init(int base_year)
 624 {
 625     ISADevice *dev;
 626
 627     dev = isa_create("mc146818rtc");
 628     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 629     qdev_init_nofail(&dev->qdev);
 630     return dev;
 631 }
 632
 633 static ISADeviceInfo mc146818rtc_info = {
 634     .qdev.name     = "mc146818rtc",
 635     .qdev.size     = sizeof(RTCState),
 636     .qdev.no_user  = 1,
 637     .qdev.vmsd     = &vmstate_rtc,
 638     .init          = rtc_initfn,
 639     .qdev.props    = (Property[]) {
 640         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 641         DEFINE_PROP_END_OF_LIST(),
 642     }
 643 };
 644
 645 static void mc146818rtc_register(void)
 646 {
 647     isa_qdev_register(&mc146818rtc_info);
 648 }
 649 device_init(mc146818rtc_register)