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[qemu/mdroth.git] / target-cris / translate.c
blobe09aaa9e9d13894808b9fb0a0eb093cb683fc8c0
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include <stdarg.h>
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <string.h>
30 #include <inttypes.h>
31
32 #include "cpu.h"
33 #include "exec-all.h"
34 #include "disas.h"
35 #include "tcg-op.h"
36 #include "helper.h"
37 #include "mmu.h"
38 #include "crisv32-decode.h"
39 #include "qemu-common.h"
40
41 #define GEN_HELPER 1
42 #include "helper.h"
43
44 #define DISAS_CRIS 0
45 #if DISAS_CRIS
46 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
47 #else
48 # define LOG_DIS(...) do { } while (0)
49 #endif
50
51 #define D(x)
52 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
53 #define BUG_ON(x) ({if (x) BUG();})
54
55 #define DISAS_SWI 5
56
57 /* Used by the decoder. */
58 #define EXTRACT_FIELD(src, start, end) \
59 (((src) >> start) & ((1 << (end - start + 1)) - 1))
60
61 #define CC_MASK_NZ 0xc
62 #define CC_MASK_NZV 0xe
63 #define CC_MASK_NZVC 0xf
64 #define CC_MASK_RNZV 0x10e
65
66 static TCGv_ptr cpu_env;
67 static TCGv cpu_R[16];
68 static TCGv cpu_PR[16];
69 static TCGv cc_x;
70 static TCGv cc_src;
71 static TCGv cc_dest;
72 static TCGv cc_result;
73 static TCGv cc_op;
74 static TCGv cc_size;
75 static TCGv cc_mask;
76
77 static TCGv env_btaken;
78 static TCGv env_btarget;
79 static TCGv env_pc;
80
81 #include "gen-icount.h"
82
83 /* This is the state at translation time. */
84 typedef struct DisasContext {
85 CPUState *env;
86 target_ulong pc, ppc;
87
88 /* Decoder. */
89 unsigned int (*decoder)(struct DisasContext *dc);
90 uint32_t ir;
91 uint32_t opcode;
92 unsigned int op1;
93 unsigned int op2;
94 unsigned int zsize, zzsize;
95 unsigned int mode;
96 unsigned int postinc;
97
98 unsigned int size;
99 unsigned int src;
100 unsigned int dst;
101 unsigned int cond;
102
103 int update_cc;
104 int cc_op;
105 int cc_size;
106 uint32_t cc_mask;
107
108 int cc_size_uptodate; /* -1 invalid or last written value. */
109
110 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
111 int flags_uptodate; /* Wether or not $ccs is uptodate. */
112 int flagx_known; /* Wether or not flags_x has the x flag known at
113 translation time. */
114 int flags_x;
115
116 int clear_x; /* Clear x after this insn? */
117 int clear_prefix; /* Clear prefix after this insn? */
118 int clear_locked_irq; /* Clear the irq lockout. */
119 int cpustate_changed;
120 unsigned int tb_flags; /* tb dependent flags. */
121 int is_jmp;
122
123 #define JMP_NOJMP 0
124 #define JMP_DIRECT 1
125 #define JMP_DIRECT_CC 2
126 #define JMP_INDIRECT 3
127 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
128 uint32_t jmp_pc;
129
130 int delayed_branch;
131
132 struct TranslationBlock *tb;
133 int singlestep_enabled;
134 } DisasContext;
135
136 static void gen_BUG(DisasContext *dc, const char *file, int line)
137 {
138 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
139 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
140 cpu_abort(dc->env, "%s:%d\n", file, line);
141 }
142
143 static const char *regnames[] =
144 {
145 "$r0", "$r1", "$r2", "$r3",
146 "$r4", "$r5", "$r6", "$r7",
147 "$r8", "$r9", "$r10", "$r11",
148 "$r12", "$r13", "$sp", "$acr",
149 };
150 static const char *pregnames[] =
151 {
152 "$bz", "$vr", "$pid", "$srs",
153 "$wz", "$exs", "$eda", "$mof",
154 "$dz", "$ebp", "$erp", "$srp",
155 "$nrp", "$ccs", "$usp", "$spc",
156 };
157
158 /* We need this table to handle preg-moves with implicit width. */
159 static int preg_sizes[] = {
160 1, /* bz. */
161 1, /* vr. */
162 4, /* pid. */
163 1, /* srs. */
164 2, /* wz. */
165 4, 4, 4,
166 4, 4, 4, 4,
167 4, 4, 4, 4,
168 };
169
170 #define t_gen_mov_TN_env(tn, member) \
171 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
172 #define t_gen_mov_env_TN(member, tn) \
173 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
174
175 static inline void t_gen_mov_TN_reg(TCGv tn, int r)
176 {
177 if (r < 0 || r > 15)
178 fprintf(stderr, "wrong register read $r%d\n", r);
179 tcg_gen_mov_tl(tn, cpu_R[r]);
180 }
181 static inline void t_gen_mov_reg_TN(int r, TCGv tn)
182 {
183 if (r < 0 || r > 15)
184 fprintf(stderr, "wrong register write $r%d\n", r);
185 tcg_gen_mov_tl(cpu_R[r], tn);
186 }
187
188 static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
189 {
190 if (offset > sizeof (CPUState))
191 fprintf(stderr, "wrong load from env from off=%d\n", offset);
192 tcg_gen_ld_tl(tn, cpu_env, offset);
193 }
194 static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
195 {
196 if (offset > sizeof (CPUState))
197 fprintf(stderr, "wrong store to env at off=%d\n", offset);
198 tcg_gen_st_tl(tn, cpu_env, offset);
199 }
200
201 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
202 {
203 if (r < 0 || r > 15)
204 fprintf(stderr, "wrong register read $p%d\n", r);
205 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
206 tcg_gen_mov_tl(tn, tcg_const_tl(0));
207 else if (r == PR_VR)
208 tcg_gen_mov_tl(tn, tcg_const_tl(32));
209 else
210 tcg_gen_mov_tl(tn, cpu_PR[r]);
211 }
212 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
213 {
214 if (r < 0 || r > 15)
215 fprintf(stderr, "wrong register write $p%d\n", r);
216 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
217 return;
218 else if (r == PR_SRS)
219 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
220 else {
221 if (r == PR_PID)
222 gen_helper_tlb_flush_pid(tn);
223 if (dc->tb_flags & S_FLAG && r == PR_SPC)
224 gen_helper_spc_write(tn);
225 else if (r == PR_CCS)
226 dc->cpustate_changed = 1;
227 tcg_gen_mov_tl(cpu_PR[r], tn);
228 }
229 }
230
231 /* Sign extend at translation time. */
232 static int sign_extend(unsigned int val, unsigned int width)
233 {
234 int sval;
235
236 /* LSL. */
237 val <<= 31 - width;
238 sval = val;
239 /* ASR. */
240 sval >>= 31 - width;
241 return sval;
242 }
243
244 static int cris_fetch(DisasContext *dc, uint32_t addr,
245 unsigned int size, unsigned int sign)
246 {
247 int r;
248
249 switch (size) {
250 case 4:
251 {
252 r = ldl_code(addr);
253 break;
254 }
255 case 2:
256 {
257 if (sign) {
258 r = ldsw_code(addr);
259 } else {
260 r = lduw_code(addr);
261 }
262 break;
263 }
264 case 1:
265 {
266 if (sign) {
267 r = ldsb_code(addr);
268 } else {
269 r = ldub_code(addr);
270 }
271 break;
272 }
273 default:
274 cpu_abort(dc->env, "Invalid fetch size %d\n", size);
275 break;
276 }
277 return r;
278 }
279
280 static void cris_lock_irq(DisasContext *dc)
281 {
282 dc->clear_locked_irq = 0;
283 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
284 }
285
286 static inline void t_gen_raise_exception(uint32_t index)
287 {
288 TCGv_i32 tmp = tcg_const_i32(index);
289 gen_helper_raise_exception(tmp);
290 tcg_temp_free_i32(tmp);
291 }
292
293 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
294 {
295 TCGv t0, t_31;
296
297 t0 = tcg_temp_new();
298 t_31 = tcg_const_tl(31);
299 tcg_gen_shl_tl(d, a, b);
300
301 tcg_gen_sub_tl(t0, t_31, b);
302 tcg_gen_sar_tl(t0, t0, t_31);
303 tcg_gen_and_tl(t0, t0, d);
304 tcg_gen_xor_tl(d, d, t0);
305 tcg_temp_free(t0);
306 tcg_temp_free(t_31);
307 }
308
309 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
310 {
311 TCGv t0, t_31;
312
313 t0 = tcg_temp_new();
314 t_31 = tcg_temp_new();
315 tcg_gen_shr_tl(d, a, b);
316
317 tcg_gen_movi_tl(t_31, 31);
318 tcg_gen_sub_tl(t0, t_31, b);
319 tcg_gen_sar_tl(t0, t0, t_31);
320 tcg_gen_and_tl(t0, t0, d);
321 tcg_gen_xor_tl(d, d, t0);
322 tcg_temp_free(t0);
323 tcg_temp_free(t_31);
324 }
325
326 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
327 {
328 TCGv t0, t_31;
329
330 t0 = tcg_temp_new();
331 t_31 = tcg_temp_new();
332 tcg_gen_sar_tl(d, a, b);
333
334 tcg_gen_movi_tl(t_31, 31);
335 tcg_gen_sub_tl(t0, t_31, b);
336 tcg_gen_sar_tl(t0, t0, t_31);
337 tcg_gen_or_tl(d, d, t0);
338 tcg_temp_free(t0);
339 tcg_temp_free(t_31);
340 }
341
342 /* 64-bit signed mul, lower result in d and upper in d2. */
343 static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
344 {
345 TCGv_i64 t0, t1;
346
347 t0 = tcg_temp_new_i64();
348 t1 = tcg_temp_new_i64();
349
350 tcg_gen_ext_i32_i64(t0, a);
351 tcg_gen_ext_i32_i64(t1, b);
352 tcg_gen_mul_i64(t0, t0, t1);
353
354 tcg_gen_trunc_i64_i32(d, t0);
355 tcg_gen_shri_i64(t0, t0, 32);
356 tcg_gen_trunc_i64_i32(d2, t0);
357
358 tcg_temp_free_i64(t0);
359 tcg_temp_free_i64(t1);
360 }
361
362 /* 64-bit unsigned muls, lower result in d and upper in d2. */
363 static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
364 {
365 TCGv_i64 t0, t1;
366
367 t0 = tcg_temp_new_i64();
368 t1 = tcg_temp_new_i64();
369
370 tcg_gen_extu_i32_i64(t0, a);
371 tcg_gen_extu_i32_i64(t1, b);
372 tcg_gen_mul_i64(t0, t0, t1);
373
374 tcg_gen_trunc_i64_i32(d, t0);
375 tcg_gen_shri_i64(t0, t0, 32);
376 tcg_gen_trunc_i64_i32(d2, t0);
377
378 tcg_temp_free_i64(t0);
379 tcg_temp_free_i64(t1);
380 }
381
382 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
383 {
384 int l1;
385
386 l1 = gen_new_label();
387
388 /*
389 * d <<= 1
390 * if (d >= s)
391 * d -= s;
392 */
393 tcg_gen_shli_tl(d, a, 1);
394 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
395 tcg_gen_sub_tl(d, d, b);
396 gen_set_label(l1);
397 }
398
399 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
400 {
401 TCGv t;
402
403 /*
404 * d <<= 1
405 * if (n)
406 * d += s;
407 */
408 t = tcg_temp_new();
409 tcg_gen_shli_tl(d, a, 1);
410 tcg_gen_shli_tl(t, ccs, 31 - 3);
411 tcg_gen_sari_tl(t, t, 31);
412 tcg_gen_and_tl(t, t, b);
413 tcg_gen_add_tl(d, d, t);
414 tcg_temp_free(t);
415 }
416
417 /* Extended arithmetics on CRIS. */
418 static inline void t_gen_add_flag(TCGv d, int flag)
419 {
420 TCGv c;
421
422 c = tcg_temp_new();
423 t_gen_mov_TN_preg(c, PR_CCS);
424 /* Propagate carry into d. */
425 tcg_gen_andi_tl(c, c, 1 << flag);
426 if (flag)
427 tcg_gen_shri_tl(c, c, flag);
428 tcg_gen_add_tl(d, d, c);
429 tcg_temp_free(c);
430 }
431
432 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
433 {
434 if (dc->flagx_known) {
435 if (dc->flags_x) {
436 TCGv c;
437
438 c = tcg_temp_new();
439 t_gen_mov_TN_preg(c, PR_CCS);
440 /* C flag is already at bit 0. */
441 tcg_gen_andi_tl(c, c, C_FLAG);
442 tcg_gen_add_tl(d, d, c);
443 tcg_temp_free(c);
444 }
445 } else {
446 TCGv x, c;
447
448 x = tcg_temp_new();
449 c = tcg_temp_new();
450 t_gen_mov_TN_preg(x, PR_CCS);
451 tcg_gen_mov_tl(c, x);
452
453 /* Propagate carry into d if X is set. Branch free. */
454 tcg_gen_andi_tl(c, c, C_FLAG);
455 tcg_gen_andi_tl(x, x, X_FLAG);
456 tcg_gen_shri_tl(x, x, 4);
457
458 tcg_gen_and_tl(x, x, c);
459 tcg_gen_add_tl(d, d, x);
460 tcg_temp_free(x);
461 tcg_temp_free(c);
462 }
463 }
464
465 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
466 {
467 if (dc->flagx_known) {
468 if (dc->flags_x) {
469 TCGv c;
470
471 c = tcg_temp_new();
472 t_gen_mov_TN_preg(c, PR_CCS);
473 /* C flag is already at bit 0. */
474 tcg_gen_andi_tl(c, c, C_FLAG);
475 tcg_gen_sub_tl(d, d, c);
476 tcg_temp_free(c);
477 }
478 } else {
479 TCGv x, c;
480
481 x = tcg_temp_new();
482 c = tcg_temp_new();
483 t_gen_mov_TN_preg(x, PR_CCS);
484 tcg_gen_mov_tl(c, x);
485
486 /* Propagate carry into d if X is set. Branch free. */
487 tcg_gen_andi_tl(c, c, C_FLAG);
488 tcg_gen_andi_tl(x, x, X_FLAG);
489 tcg_gen_shri_tl(x, x, 4);
490
491 tcg_gen_and_tl(x, x, c);
492 tcg_gen_sub_tl(d, d, x);
493 tcg_temp_free(x);
494 tcg_temp_free(c);
495 }
496 }
497
498 /* Swap the two bytes within each half word of the s operand.
499 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
500 static inline void t_gen_swapb(TCGv d, TCGv s)
501 {
502 TCGv t, org_s;
503
504 t = tcg_temp_new();
505 org_s = tcg_temp_new();
506
507 /* d and s may refer to the same object. */
508 tcg_gen_mov_tl(org_s, s);
509 tcg_gen_shli_tl(t, org_s, 8);
510 tcg_gen_andi_tl(d, t, 0xff00ff00);
511 tcg_gen_shri_tl(t, org_s, 8);
512 tcg_gen_andi_tl(t, t, 0x00ff00ff);
513 tcg_gen_or_tl(d, d, t);
514 tcg_temp_free(t);
515 tcg_temp_free(org_s);
516 }
517
518 /* Swap the halfwords of the s operand. */
519 static inline void t_gen_swapw(TCGv d, TCGv s)
520 {
521 TCGv t;
522 /* d and s refer the same object. */
523 t = tcg_temp_new();
524 tcg_gen_mov_tl(t, s);
525 tcg_gen_shli_tl(d, t, 16);
526 tcg_gen_shri_tl(t, t, 16);
527 tcg_gen_or_tl(d, d, t);
528 tcg_temp_free(t);
529 }
530
531 /* Reverse the within each byte.
532 T0 = (((T0 << 7) & 0x80808080) |
533 ((T0 << 5) & 0x40404040) |
534 ((T0 << 3) & 0x20202020) |
535 ((T0 << 1) & 0x10101010) |
536 ((T0 >> 1) & 0x08080808) |
537 ((T0 >> 3) & 0x04040404) |
538 ((T0 >> 5) & 0x02020202) |
539 ((T0 >> 7) & 0x01010101));
540 */
541 static inline void t_gen_swapr(TCGv d, TCGv s)
542 {
543 struct {
544 int shift; /* LSL when positive, LSR when negative. */
545 uint32_t mask;
546 } bitrev [] = {
547 {7, 0x80808080},
548 {5, 0x40404040},
549 {3, 0x20202020},
550 {1, 0x10101010},
551 {-1, 0x08080808},
552 {-3, 0x04040404},
553 {-5, 0x02020202},
554 {-7, 0x01010101}
555 };
556 int i;
557 TCGv t, org_s;
558
559 /* d and s refer the same object. */
560 t = tcg_temp_new();
561 org_s = tcg_temp_new();
562 tcg_gen_mov_tl(org_s, s);
563
564 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
565 tcg_gen_andi_tl(d, t, bitrev[0].mask);
566 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
567 if (bitrev[i].shift >= 0) {
568 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
569 } else {
570 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
571 }
572 tcg_gen_andi_tl(t, t, bitrev[i].mask);
573 tcg_gen_or_tl(d, d, t);
574 }
575 tcg_temp_free(t);
576 tcg_temp_free(org_s);
577 }
578
579 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
580 {
581 int l1;
582
583 l1 = gen_new_label();
584
585 /* Conditional jmp. */
586 tcg_gen_mov_tl(env_pc, pc_false);
587 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
588 tcg_gen_mov_tl(env_pc, pc_true);
589 gen_set_label(l1);
590 }
591
592 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
593 {
594 TranslationBlock *tb;
595 tb = dc->tb;
596 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
597 tcg_gen_goto_tb(n);
598 tcg_gen_movi_tl(env_pc, dest);
599 tcg_gen_exit_tb((long)tb + n);
600 } else {
601 tcg_gen_movi_tl(env_pc, dest);
602 tcg_gen_exit_tb(0);
603 }
604 }
605
606 static inline void cris_clear_x_flag(DisasContext *dc)
607 {
608 if (dc->flagx_known && dc->flags_x)
609 dc->flags_uptodate = 0;
610
611 dc->flagx_known = 1;
612 dc->flags_x = 0;
613 }
614
615 static void cris_flush_cc_state(DisasContext *dc)
616 {
617 if (dc->cc_size_uptodate != dc->cc_size) {
618 tcg_gen_movi_tl(cc_size, dc->cc_size);
619 dc->cc_size_uptodate = dc->cc_size;
620 }
621 tcg_gen_movi_tl(cc_op, dc->cc_op);
622 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
623 }
624
625 static void cris_evaluate_flags(DisasContext *dc)
626 {
627 if (dc->flags_uptodate)
628 return;
629
630 cris_flush_cc_state(dc);
631
632 switch (dc->cc_op)
633 {
634 case CC_OP_MCP:
635 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS],
636 cpu_PR[PR_CCS], cc_src,
637 cc_dest, cc_result);
638 break;
639 case CC_OP_MULS:
640 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS],
641 cpu_PR[PR_CCS], cc_result,
642 cpu_PR[PR_MOF]);
643 break;
644 case CC_OP_MULU:
645 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS],
646 cpu_PR[PR_CCS], cc_result,
647 cpu_PR[PR_MOF]);
648 break;
649 case CC_OP_MOVE:
650 case CC_OP_AND:
651 case CC_OP_OR:
652 case CC_OP_XOR:
653 case CC_OP_ASR:
654 case CC_OP_LSR:
655 case CC_OP_LSL:
656 switch (dc->cc_size)
657 {
658 case 4:
659 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
660 cpu_PR[PR_CCS], cc_result);
661 break;
662 case 2:
663 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
664 cpu_PR[PR_CCS], cc_result);
665 break;
666 default:
667 gen_helper_evaluate_flags();
668 break;
669 }
670 break;
671 case CC_OP_FLAGS:
672 /* live. */
673 break;
674 case CC_OP_SUB:
675 case CC_OP_CMP:
676 if (dc->cc_size == 4)
677 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS],
678 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
679 else
680 gen_helper_evaluate_flags();
681
682 break;
683 default:
684 switch (dc->cc_size)
685 {
686 case 4:
687 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS],
688 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
689 break;
690 default:
691 gen_helper_evaluate_flags();
692 break;
693 }
694 break;
695 }
696
697 if (dc->flagx_known) {
698 if (dc->flags_x)
699 tcg_gen_ori_tl(cpu_PR[PR_CCS],
700 cpu_PR[PR_CCS], X_FLAG);
701 else if (dc->cc_op == CC_OP_FLAGS)
702 tcg_gen_andi_tl(cpu_PR[PR_CCS],
703 cpu_PR[PR_CCS], ~X_FLAG);
704 }
705 dc->flags_uptodate = 1;
706 }
707
708 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
709 {
710 uint32_t ovl;
711
712 if (!mask) {
713 dc->update_cc = 0;
714 return;
715 }
716
717 /* Check if we need to evaluate the condition codes due to
718 CC overlaying. */
719 ovl = (dc->cc_mask ^ mask) & ~mask;
720 if (ovl) {
721 /* TODO: optimize this case. It trigs all the time. */
722 cris_evaluate_flags (dc);
723 }
724 dc->cc_mask = mask;
725 dc->update_cc = 1;
726 }
727
728 static void cris_update_cc_op(DisasContext *dc, int op, int size)
729 {
730 dc->cc_op = op;
731 dc->cc_size = size;
732 dc->flags_uptodate = 0;
733 }
734
735 static inline void cris_update_cc_x(DisasContext *dc)
736 {
737 /* Save the x flag state at the time of the cc snapshot. */
738 if (dc->flagx_known) {
739 if (dc->cc_x_uptodate == (2 | dc->flags_x))
740 return;
741 tcg_gen_movi_tl(cc_x, dc->flags_x);
742 dc->cc_x_uptodate = 2 | dc->flags_x;
743 }
744 else {
745 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
746 dc->cc_x_uptodate = 1;
747 }
748 }
749
750 /* Update cc prior to executing ALU op. Needs source operands untouched. */
751 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
752 TCGv dst, TCGv src, int size)
753 {
754 if (dc->update_cc) {
755 cris_update_cc_op(dc, op, size);
756 tcg_gen_mov_tl(cc_src, src);
757
758 if (op != CC_OP_MOVE
759 && op != CC_OP_AND
760 && op != CC_OP_OR
761 && op != CC_OP_XOR
762 && op != CC_OP_ASR
763 && op != CC_OP_LSR
764 && op != CC_OP_LSL)
765 tcg_gen_mov_tl(cc_dest, dst);
766
767 cris_update_cc_x(dc);
768 }
769 }
770
771 /* Update cc after executing ALU op. needs the result. */
772 static inline void cris_update_result(DisasContext *dc, TCGv res)
773 {
774 if (dc->update_cc)
775 tcg_gen_mov_tl(cc_result, res);
776 }
777
778 /* Returns one if the write back stage should execute. */
779 static void cris_alu_op_exec(DisasContext *dc, int op,
780 TCGv dst, TCGv a, TCGv b, int size)
781 {
782 /* Emit the ALU insns. */
783 switch (op)
784 {
785 case CC_OP_ADD:
786 tcg_gen_add_tl(dst, a, b);
787 /* Extended arithmetics. */
788 t_gen_addx_carry(dc, dst);
789 break;
790 case CC_OP_ADDC:
791 tcg_gen_add_tl(dst, a, b);
792 t_gen_add_flag(dst, 0); /* C_FLAG. */
793 break;
794 case CC_OP_MCP:
795 tcg_gen_add_tl(dst, a, b);
796 t_gen_add_flag(dst, 8); /* R_FLAG. */
797 break;
798 case CC_OP_SUB:
799 tcg_gen_sub_tl(dst, a, b);
800 /* Extended arithmetics. */
801 t_gen_subx_carry(dc, dst);
802 break;
803 case CC_OP_MOVE:
804 tcg_gen_mov_tl(dst, b);
805 break;
806 case CC_OP_OR:
807 tcg_gen_or_tl(dst, a, b);
808 break;
809 case CC_OP_AND:
810 tcg_gen_and_tl(dst, a, b);
811 break;
812 case CC_OP_XOR:
813 tcg_gen_xor_tl(dst, a, b);
814 break;
815 case CC_OP_LSL:
816 t_gen_lsl(dst, a, b);
817 break;
818 case CC_OP_LSR:
819 t_gen_lsr(dst, a, b);
820 break;
821 case CC_OP_ASR:
822 t_gen_asr(dst, a, b);
823 break;
824 case CC_OP_NEG:
825 tcg_gen_neg_tl(dst, b);
826 /* Extended arithmetics. */
827 t_gen_subx_carry(dc, dst);
828 break;
829 case CC_OP_LZ:
830 gen_helper_lz(dst, b);
831 break;
832 case CC_OP_MULS:
833 t_gen_muls(dst, cpu_PR[PR_MOF], a, b);
834 break;
835 case CC_OP_MULU:
836 t_gen_mulu(dst, cpu_PR[PR_MOF], a, b);
837 break;
838 case CC_OP_DSTEP:
839 t_gen_cris_dstep(dst, a, b);
840 break;
841 case CC_OP_MSTEP:
842 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
843 break;
844 case CC_OP_BOUND:
845 {
846 int l1;
847 l1 = gen_new_label();
848 tcg_gen_mov_tl(dst, a);
849 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
850 tcg_gen_mov_tl(dst, b);
851 gen_set_label(l1);
852 }
853 break;
854 case CC_OP_CMP:
855 tcg_gen_sub_tl(dst, a, b);
856 /* Extended arithmetics. */
857 t_gen_subx_carry(dc, dst);
858 break;
859 default:
860 qemu_log("illegal ALU op.\n");
861 BUG();
862 break;
863 }
864
865 if (size == 1)
866 tcg_gen_andi_tl(dst, dst, 0xff);
867 else if (size == 2)
868 tcg_gen_andi_tl(dst, dst, 0xffff);
869 }
870
871 static void cris_alu(DisasContext *dc, int op,
872 TCGv d, TCGv op_a, TCGv op_b, int size)
873 {
874 TCGv tmp;
875 int writeback;
876
877 writeback = 1;
878
879 if (op == CC_OP_CMP) {
880 tmp = tcg_temp_new();
881 writeback = 0;
882 } else if (size == 4) {
883 tmp = d;
884 writeback = 0;
885 } else
886 tmp = tcg_temp_new();
887
888
889 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
890 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
891 cris_update_result(dc, tmp);
892
893 /* Writeback. */
894 if (writeback) {
895 if (size == 1)
896 tcg_gen_andi_tl(d, d, ~0xff);
897 else
898 tcg_gen_andi_tl(d, d, ~0xffff);
899 tcg_gen_or_tl(d, d, tmp);
900 }
901 if (!TCGV_EQUAL(tmp, d))
902 tcg_temp_free(tmp);
903 }
904
905 static int arith_cc(DisasContext *dc)
906 {
907 if (dc->update_cc) {
908 switch (dc->cc_op) {
909 case CC_OP_ADDC: return 1;
910 case CC_OP_ADD: return 1;
911 case CC_OP_SUB: return 1;
912 case CC_OP_DSTEP: return 1;
913 case CC_OP_LSL: return 1;
914 case CC_OP_LSR: return 1;
915 case CC_OP_ASR: return 1;
916 case CC_OP_CMP: return 1;
917 case CC_OP_NEG: return 1;
918 case CC_OP_OR: return 1;
919 case CC_OP_AND: return 1;
920 case CC_OP_XOR: return 1;
921 case CC_OP_MULU: return 1;
922 case CC_OP_MULS: return 1;
923 default:
924 return 0;
925 }
926 }
927 return 0;
928 }
929
930 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
931 {
932 int arith_opt, move_opt;
933
934 /* TODO: optimize more condition codes. */
935
936 /*
937 * If the flags are live, we've gotta look into the bits of CCS.
938 * Otherwise, if we just did an arithmetic operation we try to
939 * evaluate the condition code faster.
940 *
941 * When this function is done, T0 should be non-zero if the condition
942 * code is true.
943 */
944 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
945 move_opt = (dc->cc_op == CC_OP_MOVE);
946 switch (cond) {
947 case CC_EQ:
948 if ((arith_opt || move_opt)
949 && dc->cc_x_uptodate != (2 | X_FLAG)) {
950 /* If cc_result is zero, T0 should be
951 non-zero otherwise T0 should be zero. */
952 int l1;
953 l1 = gen_new_label();
954 tcg_gen_movi_tl(cc, 0);
955 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
956 0, l1);
957 tcg_gen_movi_tl(cc, 1);
958 gen_set_label(l1);
959 }
960 else {
961 cris_evaluate_flags(dc);
962 tcg_gen_andi_tl(cc,
963 cpu_PR[PR_CCS], Z_FLAG);
964 }
965 break;
966 case CC_NE:
967 if ((arith_opt || move_opt)
968 && dc->cc_x_uptodate != (2 | X_FLAG)) {
969 tcg_gen_mov_tl(cc, cc_result);
970 } else {
971 cris_evaluate_flags(dc);
972 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
973 Z_FLAG);
974 tcg_gen_andi_tl(cc, cc, Z_FLAG);
975 }
976 break;
977 case CC_CS:
978 cris_evaluate_flags(dc);
979 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
980 break;
981 case CC_CC:
982 cris_evaluate_flags(dc);
983 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
984 tcg_gen_andi_tl(cc, cc, C_FLAG);
985 break;
986 case CC_VS:
987 cris_evaluate_flags(dc);
988 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
989 break;
990 case CC_VC:
991 cris_evaluate_flags(dc);
992 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
993 V_FLAG);
994 tcg_gen_andi_tl(cc, cc, V_FLAG);
995 break;
996 case CC_PL:
997 if (arith_opt || move_opt) {
998 int bits = 31;
999
1000 if (dc->cc_size == 1)
1001 bits = 7;
1002 else if (dc->cc_size == 2)
1003 bits = 15;
1004
1005 tcg_gen_shri_tl(cc, cc_result, bits);
1006 tcg_gen_xori_tl(cc, cc, 1);
1007 } else {
1008 cris_evaluate_flags(dc);
1009 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
1010 N_FLAG);
1011 tcg_gen_andi_tl(cc, cc, N_FLAG);
1012 }
1013 break;
1014 case CC_MI:
1015 if (arith_opt || move_opt) {
1016 int bits = 31;
1017
1018 if (dc->cc_size == 1)
1019 bits = 7;
1020 else if (dc->cc_size == 2)
1021 bits = 15;
1022
1023 tcg_gen_shri_tl(cc, cc_result, bits);
1024 tcg_gen_andi_tl(cc, cc, 1);
1025 }
1026 else {
1027 cris_evaluate_flags(dc);
1028 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1029 N_FLAG);
1030 }
1031 break;
1032 case CC_LS:
1033 cris_evaluate_flags(dc);
1034 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
1035 C_FLAG | Z_FLAG);
1036 break;
1037 case CC_HI:
1038 cris_evaluate_flags(dc);
1039 {
1040 TCGv tmp;
1041
1042 tmp = tcg_temp_new();
1043 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
1044 C_FLAG | Z_FLAG);
1045 /* Overlay the C flag on top of the Z. */
1046 tcg_gen_shli_tl(cc, tmp, 2);
1047 tcg_gen_and_tl(cc, tmp, cc);
1048 tcg_gen_andi_tl(cc, cc, Z_FLAG);
1049
1050 tcg_temp_free(tmp);
1051 }
1052 break;
1053 case CC_GE:
1054 cris_evaluate_flags(dc);
1055 /* Overlay the V flag on top of the N. */
1056 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1057 tcg_gen_xor_tl(cc,
1058 cpu_PR[PR_CCS], cc);
1059 tcg_gen_andi_tl(cc, cc, N_FLAG);
1060 tcg_gen_xori_tl(cc, cc, N_FLAG);
1061 break;
1062 case CC_LT:
1063 cris_evaluate_flags(dc);
1064 /* Overlay the V flag on top of the N. */
1065 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
1066 tcg_gen_xor_tl(cc,
1067 cpu_PR[PR_CCS], cc);
1068 tcg_gen_andi_tl(cc, cc, N_FLAG);
1069 break;
1070 case CC_GT:
1071 cris_evaluate_flags(dc);
1072 {
1073 TCGv n, z;
1074
1075 n = tcg_temp_new();
1076 z = tcg_temp_new();
1077
1078 /* To avoid a shift we overlay everything on
1079 the V flag. */
1080 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1081 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1082 /* invert Z. */
1083 tcg_gen_xori_tl(z, z, 2);
1084
1085 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1086 tcg_gen_xori_tl(n, n, 2);
1087 tcg_gen_and_tl(cc, z, n);
1088 tcg_gen_andi_tl(cc, cc, 2);
1089
1090 tcg_temp_free(n);
1091 tcg_temp_free(z);
1092 }
1093 break;
1094 case CC_LE:
1095 cris_evaluate_flags(dc);
1096 {
1097 TCGv n, z;
1098
1099 n = tcg_temp_new();
1100 z = tcg_temp_new();
1101
1102 /* To avoid a shift we overlay everything on
1103 the V flag. */
1104 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1105 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1106
1107 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1108 tcg_gen_or_tl(cc, z, n);
1109 tcg_gen_andi_tl(cc, cc, 2);
1110
1111 tcg_temp_free(n);
1112 tcg_temp_free(z);
1113 }
1114 break;
1115 case CC_P:
1116 cris_evaluate_flags(dc);
1117 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1118 break;
1119 case CC_A:
1120 tcg_gen_movi_tl(cc, 1);
1121 break;
1122 default:
1123 BUG();
1124 break;
1125 };
1126 }
1127
1128 static void cris_store_direct_jmp(DisasContext *dc)
1129 {
1130 /* Store the direct jmp state into the cpu-state. */
1131 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1132 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1133 dc->jmp = JMP_INDIRECT;
1134 }
1135 }
1136
1137 static void cris_prepare_cc_branch (DisasContext *dc,
1138 int offset, int cond)
1139 {
1140 /* This helps us re-schedule the micro-code to insns in delay-slots
1141 before the actual jump. */
1142 dc->delayed_branch = 2;
1143 dc->jmp = JMP_DIRECT_CC;
1144 dc->jmp_pc = dc->pc + offset;
1145
1146 gen_tst_cc (dc, env_btaken, cond);
1147 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1148 }
1149
1150
1151 /* jumps, when the dest is in a live reg for example. Direct should be set
1152 when the dest addr is constant to allow tb chaining. */
1153 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1154 {
1155 /* This helps us re-schedule the micro-code to insns in delay-slots
1156 before the actual jump. */
1157 dc->delayed_branch = 2;
1158 dc->jmp = type;
1159 if (type == JMP_INDIRECT) {
1160 tcg_gen_movi_tl(env_btaken, 1);
1161 }
1162 }
1163
1164 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1165 {
1166 int mem_index = cpu_mmu_index(dc->env);
1167
1168 /* If we get a fault on a delayslot we must keep the jmp state in
1169 the cpu-state to be able to re-execute the jmp. */
1170 if (dc->delayed_branch == 1)
1171 cris_store_direct_jmp(dc);
1172
1173 tcg_gen_qemu_ld64(dst, addr, mem_index);
1174 }
1175
1176 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1177 unsigned int size, int sign)
1178 {
1179 int mem_index = cpu_mmu_index(dc->env);
1180
1181 /* If we get a fault on a delayslot we must keep the jmp state in
1182 the cpu-state to be able to re-execute the jmp. */
1183 if (dc->delayed_branch == 1)
1184 cris_store_direct_jmp(dc);
1185
1186 if (size == 1) {
1187 if (sign)
1188 tcg_gen_qemu_ld8s(dst, addr, mem_index);
1189 else
1190 tcg_gen_qemu_ld8u(dst, addr, mem_index);
1191 }
1192 else if (size == 2) {
1193 if (sign)
1194 tcg_gen_qemu_ld16s(dst, addr, mem_index);
1195 else
1196 tcg_gen_qemu_ld16u(dst, addr, mem_index);
1197 }
1198 else if (size == 4) {
1199 tcg_gen_qemu_ld32u(dst, addr, mem_index);
1200 }
1201 else {
1202 abort();
1203 }
1204 }
1205
1206 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1207 unsigned int size)
1208 {
1209 int mem_index = cpu_mmu_index(dc->env);
1210
1211 /* If we get a fault on a delayslot we must keep the jmp state in
1212 the cpu-state to be able to re-execute the jmp. */
1213 if (dc->delayed_branch == 1)
1214 cris_store_direct_jmp(dc);
1215
1216
1217 /* Conditional writes. We only support the kind were X and P are known
1218 at translation time. */
1219 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1220 dc->postinc = 0;
1221 cris_evaluate_flags(dc);
1222 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1223 return;
1224 }
1225
1226 if (size == 1)
1227 tcg_gen_qemu_st8(val, addr, mem_index);
1228 else if (size == 2)
1229 tcg_gen_qemu_st16(val, addr, mem_index);
1230 else
1231 tcg_gen_qemu_st32(val, addr, mem_index);
1232
1233 if (dc->flagx_known && dc->flags_x) {
1234 cris_evaluate_flags(dc);
1235 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1236 }
1237 }
1238
1239 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1240 {
1241 if (size == 1)
1242 tcg_gen_ext8s_i32(d, s);
1243 else if (size == 2)
1244 tcg_gen_ext16s_i32(d, s);
1245 else if(!TCGV_EQUAL(d, s))
1246 tcg_gen_mov_tl(d, s);
1247 }
1248
1249 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1250 {
1251 if (size == 1)
1252 tcg_gen_ext8u_i32(d, s);
1253 else if (size == 2)
1254 tcg_gen_ext16u_i32(d, s);
1255 else if (!TCGV_EQUAL(d, s))
1256 tcg_gen_mov_tl(d, s);
1257 }
1258
1259 #if DISAS_CRIS
1260 static char memsize_char(int size)
1261 {
1262 switch (size)
1263 {
1264 case 1: return 'b'; break;
1265 case 2: return 'w'; break;
1266 case 4: return 'd'; break;
1267 default:
1268 return 'x';
1269 break;
1270 }
1271 }
1272 #endif
1273
1274 static inline unsigned int memsize_z(DisasContext *dc)
1275 {
1276 return dc->zsize + 1;
1277 }
1278
1279 static inline unsigned int memsize_zz(DisasContext *dc)
1280 {
1281 switch (dc->zzsize)
1282 {
1283 case 0: return 1;
1284 case 1: return 2;
1285 default:
1286 return 4;
1287 }
1288 }
1289
1290 static inline void do_postinc (DisasContext *dc, int size)
1291 {
1292 if (dc->postinc)
1293 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1294 }
1295
1296 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1297 int size, int s_ext, TCGv dst)
1298 {
1299 if (s_ext)
1300 t_gen_sext(dst, cpu_R[rs], size);
1301 else
1302 t_gen_zext(dst, cpu_R[rs], size);
1303 }
1304
1305 /* Prepare T0 and T1 for a register alu operation.
1306 s_ext decides if the operand1 should be sign-extended or zero-extended when
1307 needed. */
1308 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1309 int size, int s_ext, TCGv dst, TCGv src)
1310 {
1311 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1312
1313 if (s_ext)
1314 t_gen_sext(dst, cpu_R[rd], size);
1315 else
1316 t_gen_zext(dst, cpu_R[rd], size);
1317 }
1318
1319 static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize,
1320 TCGv dst)
1321 {
1322 unsigned int rs;
1323 uint32_t imm;
1324 int is_imm;
1325 int insn_len = 2;
1326
1327 rs = dc->op1;
1328 is_imm = rs == 15 && dc->postinc;
1329
1330 /* Load [$rs] onto T1. */
1331 if (is_imm) {
1332 insn_len = 2 + memsize;
1333 if (memsize == 1)
1334 insn_len++;
1335
1336 imm = cris_fetch(dc, dc->pc + 2, memsize, s_ext);
1337 tcg_gen_movi_tl(dst, imm);
1338 dc->postinc = 0;
1339 } else {
1340 cris_flush_cc_state(dc);
1341 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1342 if (s_ext)
1343 t_gen_sext(dst, dst, memsize);
1344 else
1345 t_gen_zext(dst, dst, memsize);
1346 }
1347 return insn_len;
1348 }
1349
1350 /* Prepare T0 and T1 for a memory + alu operation.
1351 s_ext decides if the operand1 should be sign-extended or zero-extended when
1352 needed. */
1353 static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize,
1354 TCGv dst, TCGv src)
1355 {
1356 int insn_len;
1357
1358 insn_len = dec_prep_move_m(dc, s_ext, memsize, src);
1359 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1360 return insn_len;
1361 }
1362
1363 #if DISAS_CRIS
1364 static const char *cc_name(int cc)
1365 {
1366 static const char *cc_names[16] = {
1367 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1368 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1369 };
1370 assert(cc < 16);
1371 return cc_names[cc];
1372 }
1373 #endif
1374
1375 /* Start of insn decoders. */
1376
1377 static int dec_bccq(DisasContext *dc)
1378 {
1379 int32_t offset;
1380 int sign;
1381 uint32_t cond = dc->op2;
1382
1383 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1384 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1385
1386 offset *= 2;
1387 offset |= sign << 8;
1388 offset = sign_extend(offset, 8);
1389
1390 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1391
1392 /* op2 holds the condition-code. */
1393 cris_cc_mask(dc, 0);
1394 cris_prepare_cc_branch (dc, offset, cond);
1395 return 2;
1396 }
1397 static int dec_addoq(DisasContext *dc)
1398 {
1399 int32_t imm;
1400
1401 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1402 imm = sign_extend(dc->op1, 7);
1403
1404 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1405 cris_cc_mask(dc, 0);
1406 /* Fetch register operand, */
1407 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1408
1409 return 2;
1410 }
1411 static int dec_addq(DisasContext *dc)
1412 {
1413 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1414
1415 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1416
1417 cris_cc_mask(dc, CC_MASK_NZVC);
1418
1419 cris_alu(dc, CC_OP_ADD,
1420 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1421 return 2;
1422 }
1423 static int dec_moveq(DisasContext *dc)
1424 {
1425 uint32_t imm;
1426
1427 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1428 imm = sign_extend(dc->op1, 5);
1429 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1430
1431 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1432 return 2;
1433 }
1434 static int dec_subq(DisasContext *dc)
1435 {
1436 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1437
1438 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1439
1440 cris_cc_mask(dc, CC_MASK_NZVC);
1441 cris_alu(dc, CC_OP_SUB,
1442 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1443 return 2;
1444 }
1445 static int dec_cmpq(DisasContext *dc)
1446 {
1447 uint32_t imm;
1448 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1449 imm = sign_extend(dc->op1, 5);
1450
1451 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1452 cris_cc_mask(dc, CC_MASK_NZVC);
1453
1454 cris_alu(dc, CC_OP_CMP,
1455 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1456 return 2;
1457 }
1458 static int dec_andq(DisasContext *dc)
1459 {
1460 uint32_t imm;
1461 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1462 imm = sign_extend(dc->op1, 5);
1463
1464 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1465 cris_cc_mask(dc, CC_MASK_NZ);
1466
1467 cris_alu(dc, CC_OP_AND,
1468 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1469 return 2;
1470 }
1471 static int dec_orq(DisasContext *dc)
1472 {
1473 uint32_t imm;
1474 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1475 imm = sign_extend(dc->op1, 5);
1476 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1477 cris_cc_mask(dc, CC_MASK_NZ);
1478
1479 cris_alu(dc, CC_OP_OR,
1480 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1481 return 2;
1482 }
1483 static int dec_btstq(DisasContext *dc)
1484 {
1485 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1486 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1487
1488 cris_cc_mask(dc, CC_MASK_NZ);
1489 cris_evaluate_flags(dc);
1490 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1491 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1492 cris_alu(dc, CC_OP_MOVE,
1493 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1494 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1495 dc->flags_uptodate = 1;
1496 return 2;
1497 }
1498 static int dec_asrq(DisasContext *dc)
1499 {
1500 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1501 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1502 cris_cc_mask(dc, CC_MASK_NZ);
1503
1504 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1505 cris_alu(dc, CC_OP_MOVE,
1506 cpu_R[dc->op2],
1507 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1508 return 2;
1509 }
1510 static int dec_lslq(DisasContext *dc)
1511 {
1512 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1513 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1514
1515 cris_cc_mask(dc, CC_MASK_NZ);
1516
1517 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1518
1519 cris_alu(dc, CC_OP_MOVE,
1520 cpu_R[dc->op2],
1521 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1522 return 2;
1523 }
1524 static int dec_lsrq(DisasContext *dc)
1525 {
1526 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1527 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1528
1529 cris_cc_mask(dc, CC_MASK_NZ);
1530
1531 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1532 cris_alu(dc, CC_OP_MOVE,
1533 cpu_R[dc->op2],
1534 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1535 return 2;
1536 }
1537
1538 static int dec_move_r(DisasContext *dc)
1539 {
1540 int size = memsize_zz(dc);
1541
1542 LOG_DIS("move.%c $r%u, $r%u\n",
1543 memsize_char(size), dc->op1, dc->op2);
1544
1545 cris_cc_mask(dc, CC_MASK_NZ);
1546 if (size == 4) {
1547 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1550 cris_update_cc_x(dc);
1551 cris_update_result(dc, cpu_R[dc->op2]);
1552 }
1553 else {
1554 TCGv t0;
1555
1556 t0 = tcg_temp_new();
1557 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1558 cris_alu(dc, CC_OP_MOVE,
1559 cpu_R[dc->op2],
1560 cpu_R[dc->op2], t0, size);
1561 tcg_temp_free(t0);
1562 }
1563 return 2;
1564 }
1565
1566 static int dec_scc_r(DisasContext *dc)
1567 {
1568 int cond = dc->op2;
1569
1570 LOG_DIS("s%s $r%u\n",
1571 cc_name(cond), dc->op1);
1572
1573 if (cond != CC_A)
1574 {
1575 int l1;
1576
1577 gen_tst_cc (dc, cpu_R[dc->op1], cond);
1578 l1 = gen_new_label();
1579 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1580 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1581 gen_set_label(l1);
1582 }
1583 else
1584 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1585
1586 cris_cc_mask(dc, 0);
1587 return 2;
1588 }
1589
1590 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1591 {
1592 if (size == 4) {
1593 t[0] = cpu_R[dc->op2];
1594 t[1] = cpu_R[dc->op1];
1595 } else {
1596 t[0] = tcg_temp_new();
1597 t[1] = tcg_temp_new();
1598 }
1599 }
1600
1601 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1602 {
1603 if (size != 4) {
1604 tcg_temp_free(t[0]);
1605 tcg_temp_free(t[1]);
1606 }
1607 }
1608
1609 static int dec_and_r(DisasContext *dc)
1610 {
1611 TCGv t[2];
1612 int size = memsize_zz(dc);
1613
1614 LOG_DIS("and.%c $r%u, $r%u\n",
1615 memsize_char(size), dc->op1, dc->op2);
1616
1617 cris_cc_mask(dc, CC_MASK_NZ);
1618
1619 cris_alu_alloc_temps(dc, size, t);
1620 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1621 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1622 cris_alu_free_temps(dc, size, t);
1623 return 2;
1624 }
1625
1626 static int dec_lz_r(DisasContext *dc)
1627 {
1628 TCGv t0;
1629 LOG_DIS("lz $r%u, $r%u\n",
1630 dc->op1, dc->op2);
1631 cris_cc_mask(dc, CC_MASK_NZ);
1632 t0 = tcg_temp_new();
1633 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1634 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1635 tcg_temp_free(t0);
1636 return 2;
1637 }
1638
1639 static int dec_lsl_r(DisasContext *dc)
1640 {
1641 TCGv t[2];
1642 int size = memsize_zz(dc);
1643
1644 LOG_DIS("lsl.%c $r%u, $r%u\n",
1645 memsize_char(size), dc->op1, dc->op2);
1646
1647 cris_cc_mask(dc, CC_MASK_NZ);
1648 cris_alu_alloc_temps(dc, size, t);
1649 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1650 tcg_gen_andi_tl(t[1], t[1], 63);
1651 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1652 cris_alu_alloc_temps(dc, size, t);
1653 return 2;
1654 }
1655
1656 static int dec_lsr_r(DisasContext *dc)
1657 {
1658 TCGv t[2];
1659 int size = memsize_zz(dc);
1660
1661 LOG_DIS("lsr.%c $r%u, $r%u\n",
1662 memsize_char(size), dc->op1, dc->op2);
1663
1664 cris_cc_mask(dc, CC_MASK_NZ);
1665 cris_alu_alloc_temps(dc, size, t);
1666 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1667 tcg_gen_andi_tl(t[1], t[1], 63);
1668 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1669 cris_alu_free_temps(dc, size, t);
1670 return 2;
1671 }
1672
1673 static int dec_asr_r(DisasContext *dc)
1674 {
1675 TCGv t[2];
1676 int size = memsize_zz(dc);
1677
1678 LOG_DIS("asr.%c $r%u, $r%u\n",
1679 memsize_char(size), dc->op1, dc->op2);
1680
1681 cris_cc_mask(dc, CC_MASK_NZ);
1682 cris_alu_alloc_temps(dc, size, t);
1683 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1684 tcg_gen_andi_tl(t[1], t[1], 63);
1685 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1686 cris_alu_free_temps(dc, size, t);
1687 return 2;
1688 }
1689
1690 static int dec_muls_r(DisasContext *dc)
1691 {
1692 TCGv t[2];
1693 int size = memsize_zz(dc);
1694
1695 LOG_DIS("muls.%c $r%u, $r%u\n",
1696 memsize_char(size), dc->op1, dc->op2);
1697 cris_cc_mask(dc, CC_MASK_NZV);
1698 cris_alu_alloc_temps(dc, size, t);
1699 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1700
1701 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1702 cris_alu_free_temps(dc, size, t);
1703 return 2;
1704 }
1705
1706 static int dec_mulu_r(DisasContext *dc)
1707 {
1708 TCGv t[2];
1709 int size = memsize_zz(dc);
1710
1711 LOG_DIS("mulu.%c $r%u, $r%u\n",
1712 memsize_char(size), dc->op1, dc->op2);
1713 cris_cc_mask(dc, CC_MASK_NZV);
1714 cris_alu_alloc_temps(dc, size, t);
1715 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1716
1717 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1718 cris_alu_alloc_temps(dc, size, t);
1719 return 2;
1720 }
1721
1722
1723 static int dec_dstep_r(DisasContext *dc)
1724 {
1725 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1726 cris_cc_mask(dc, CC_MASK_NZ);
1727 cris_alu(dc, CC_OP_DSTEP,
1728 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1729 return 2;
1730 }
1731
1732 static int dec_xor_r(DisasContext *dc)
1733 {
1734 TCGv t[2];
1735 int size = memsize_zz(dc);
1736 LOG_DIS("xor.%c $r%u, $r%u\n",
1737 memsize_char(size), dc->op1, dc->op2);
1738 BUG_ON(size != 4); /* xor is dword. */
1739 cris_cc_mask(dc, CC_MASK_NZ);
1740 cris_alu_alloc_temps(dc, size, t);
1741 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1742
1743 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1744 cris_alu_free_temps(dc, size, t);
1745 return 2;
1746 }
1747
1748 static int dec_bound_r(DisasContext *dc)
1749 {
1750 TCGv l0;
1751 int size = memsize_zz(dc);
1752 LOG_DIS("bound.%c $r%u, $r%u\n",
1753 memsize_char(size), dc->op1, dc->op2);
1754 cris_cc_mask(dc, CC_MASK_NZ);
1755 l0 = tcg_temp_local_new();
1756 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1757 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1758 tcg_temp_free(l0);
1759 return 2;
1760 }
1761
1762 static int dec_cmp_r(DisasContext *dc)
1763 {
1764 TCGv t[2];
1765 int size = memsize_zz(dc);
1766 LOG_DIS("cmp.%c $r%u, $r%u\n",
1767 memsize_char(size), dc->op1, dc->op2);
1768 cris_cc_mask(dc, CC_MASK_NZVC);
1769 cris_alu_alloc_temps(dc, size, t);
1770 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1771
1772 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1773 cris_alu_free_temps(dc, size, t);
1774 return 2;
1775 }
1776
1777 static int dec_abs_r(DisasContext *dc)
1778 {
1779 TCGv t0;
1780
1781 LOG_DIS("abs $r%u, $r%u\n",
1782 dc->op1, dc->op2);
1783 cris_cc_mask(dc, CC_MASK_NZ);
1784
1785 t0 = tcg_temp_new();
1786 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1787 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1788 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1789 tcg_temp_free(t0);
1790
1791 cris_alu(dc, CC_OP_MOVE,
1792 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1793 return 2;
1794 }
1795
1796 static int dec_add_r(DisasContext *dc)
1797 {
1798 TCGv t[2];
1799 int size = memsize_zz(dc);
1800 LOG_DIS("add.%c $r%u, $r%u\n",
1801 memsize_char(size), dc->op1, dc->op2);
1802 cris_cc_mask(dc, CC_MASK_NZVC);
1803 cris_alu_alloc_temps(dc, size, t);
1804 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1805
1806 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1807 cris_alu_free_temps(dc, size, t);
1808 return 2;
1809 }
1810
1811 static int dec_addc_r(DisasContext *dc)
1812 {
1813 LOG_DIS("addc $r%u, $r%u\n",
1814 dc->op1, dc->op2);
1815 cris_evaluate_flags(dc);
1816 /* Set for this insn. */
1817 dc->flagx_known = 1;
1818 dc->flags_x = X_FLAG;
1819
1820 cris_cc_mask(dc, CC_MASK_NZVC);
1821 cris_alu(dc, CC_OP_ADDC,
1822 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1823 return 2;
1824 }
1825
1826 static int dec_mcp_r(DisasContext *dc)
1827 {
1828 LOG_DIS("mcp $p%u, $r%u\n",
1829 dc->op2, dc->op1);
1830 cris_evaluate_flags(dc);
1831 cris_cc_mask(dc, CC_MASK_RNZV);
1832 cris_alu(dc, CC_OP_MCP,
1833 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1834 return 2;
1835 }
1836
1837 #if DISAS_CRIS
1838 static char * swapmode_name(int mode, char *modename) {
1839 int i = 0;
1840 if (mode & 8)
1841 modename[i++] = 'n';
1842 if (mode & 4)
1843 modename[i++] = 'w';
1844 if (mode & 2)
1845 modename[i++] = 'b';
1846 if (mode & 1)
1847 modename[i++] = 'r';
1848 modename[i++] = 0;
1849 return modename;
1850 }
1851 #endif
1852
1853 static int dec_swap_r(DisasContext *dc)
1854 {
1855 TCGv t0;
1856 #if DISAS_CRIS
1857 char modename[4];
1858 #endif
1859 LOG_DIS("swap%s $r%u\n",
1860 swapmode_name(dc->op2, modename), dc->op1);
1861
1862 cris_cc_mask(dc, CC_MASK_NZ);
1863 t0 = tcg_temp_new();
1864 t_gen_mov_TN_reg(t0, dc->op1);
1865 if (dc->op2 & 8)
1866 tcg_gen_not_tl(t0, t0);
1867 if (dc->op2 & 4)
1868 t_gen_swapw(t0, t0);
1869 if (dc->op2 & 2)
1870 t_gen_swapb(t0, t0);
1871 if (dc->op2 & 1)
1872 t_gen_swapr(t0, t0);
1873 cris_alu(dc, CC_OP_MOVE,
1874 cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1875 tcg_temp_free(t0);
1876 return 2;
1877 }
1878
1879 static int dec_or_r(DisasContext *dc)
1880 {
1881 TCGv t[2];
1882 int size = memsize_zz(dc);
1883 LOG_DIS("or.%c $r%u, $r%u\n",
1884 memsize_char(size), dc->op1, dc->op2);
1885 cris_cc_mask(dc, CC_MASK_NZ);
1886 cris_alu_alloc_temps(dc, size, t);
1887 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1888 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1889 cris_alu_free_temps(dc, size, t);
1890 return 2;
1891 }
1892
1893 static int dec_addi_r(DisasContext *dc)
1894 {
1895 TCGv t0;
1896 LOG_DIS("addi.%c $r%u, $r%u\n",
1897 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1898 cris_cc_mask(dc, 0);
1899 t0 = tcg_temp_new();
1900 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1901 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1902 tcg_temp_free(t0);
1903 return 2;
1904 }
1905
1906 static int dec_addi_acr(DisasContext *dc)
1907 {
1908 TCGv t0;
1909 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1910 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1911 cris_cc_mask(dc, 0);
1912 t0 = tcg_temp_new();
1913 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1914 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1915 tcg_temp_free(t0);
1916 return 2;
1917 }
1918
1919 static int dec_neg_r(DisasContext *dc)
1920 {
1921 TCGv t[2];
1922 int size = memsize_zz(dc);
1923 LOG_DIS("neg.%c $r%u, $r%u\n",
1924 memsize_char(size), dc->op1, dc->op2);
1925 cris_cc_mask(dc, CC_MASK_NZVC);
1926 cris_alu_alloc_temps(dc, size, t);
1927 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1928
1929 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1930 cris_alu_free_temps(dc, size, t);
1931 return 2;
1932 }
1933
1934 static int dec_btst_r(DisasContext *dc)
1935 {
1936 LOG_DIS("btst $r%u, $r%u\n",
1937 dc->op1, dc->op2);
1938 cris_cc_mask(dc, CC_MASK_NZ);
1939 cris_evaluate_flags(dc);
1940 gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
1941 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1942 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1943 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1944 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1945 dc->flags_uptodate = 1;
1946 return 2;
1947 }
1948
1949 static int dec_sub_r(DisasContext *dc)
1950 {
1951 TCGv t[2];
1952 int size = memsize_zz(dc);
1953 LOG_DIS("sub.%c $r%u, $r%u\n",
1954 memsize_char(size), dc->op1, dc->op2);
1955 cris_cc_mask(dc, CC_MASK_NZVC);
1956 cris_alu_alloc_temps(dc, size, t);
1957 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1958 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1959 cris_alu_free_temps(dc, size, t);
1960 return 2;
1961 }
1962
1963 /* Zero extension. From size to dword. */
1964 static int dec_movu_r(DisasContext *dc)
1965 {
1966 TCGv t0;
1967 int size = memsize_z(dc);
1968 LOG_DIS("movu.%c $r%u, $r%u\n",
1969 memsize_char(size),
1970 dc->op1, dc->op2);
1971
1972 cris_cc_mask(dc, CC_MASK_NZ);
1973 t0 = tcg_temp_new();
1974 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1975 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1976 tcg_temp_free(t0);
1977 return 2;
1978 }
1979
1980 /* Sign extension. From size to dword. */
1981 static int dec_movs_r(DisasContext *dc)
1982 {
1983 TCGv t0;
1984 int size = memsize_z(dc);
1985 LOG_DIS("movs.%c $r%u, $r%u\n",
1986 memsize_char(size),
1987 dc->op1, dc->op2);
1988
1989 cris_cc_mask(dc, CC_MASK_NZ);
1990 t0 = tcg_temp_new();
1991 /* Size can only be qi or hi. */
1992 t_gen_sext(t0, cpu_R[dc->op1], size);
1993 cris_alu(dc, CC_OP_MOVE,
1994 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1995 tcg_temp_free(t0);
1996 return 2;
1997 }
1998
1999 /* zero extension. From size to dword. */
2000 static int dec_addu_r(DisasContext *dc)
2001 {
2002 TCGv t0;
2003 int size = memsize_z(dc);
2004 LOG_DIS("addu.%c $r%u, $r%u\n",
2005 memsize_char(size),
2006 dc->op1, dc->op2);
2007
2008 cris_cc_mask(dc, CC_MASK_NZVC);
2009 t0 = tcg_temp_new();
2010 /* Size can only be qi or hi. */
2011 t_gen_zext(t0, cpu_R[dc->op1], size);
2012 cris_alu(dc, CC_OP_ADD,
2013 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2014 tcg_temp_free(t0);
2015 return 2;
2016 }
2017
2018 /* Sign extension. From size to dword. */
2019 static int dec_adds_r(DisasContext *dc)
2020 {
2021 TCGv t0;
2022 int size = memsize_z(dc);
2023 LOG_DIS("adds.%c $r%u, $r%u\n",
2024 memsize_char(size),
2025 dc->op1, dc->op2);
2026
2027 cris_cc_mask(dc, CC_MASK_NZVC);
2028 t0 = tcg_temp_new();
2029 /* Size can only be qi or hi. */
2030 t_gen_sext(t0, cpu_R[dc->op1], size);
2031 cris_alu(dc, CC_OP_ADD,
2032 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2033 tcg_temp_free(t0);
2034 return 2;
2035 }
2036
2037 /* Zero extension. From size to dword. */
2038 static int dec_subu_r(DisasContext *dc)
2039 {
2040 TCGv t0;
2041 int size = memsize_z(dc);
2042 LOG_DIS("subu.%c $r%u, $r%u\n",
2043 memsize_char(size),
2044 dc->op1, dc->op2);
2045
2046 cris_cc_mask(dc, CC_MASK_NZVC);
2047 t0 = tcg_temp_new();
2048 /* Size can only be qi or hi. */
2049 t_gen_zext(t0, cpu_R[dc->op1], size);
2050 cris_alu(dc, CC_OP_SUB,
2051 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2052 tcg_temp_free(t0);
2053 return 2;
2054 }
2055
2056 /* Sign extension. From size to dword. */
2057 static int dec_subs_r(DisasContext *dc)
2058 {
2059 TCGv t0;
2060 int size = memsize_z(dc);
2061 LOG_DIS("subs.%c $r%u, $r%u\n",
2062 memsize_char(size),
2063 dc->op1, dc->op2);
2064
2065 cris_cc_mask(dc, CC_MASK_NZVC);
2066 t0 = tcg_temp_new();
2067 /* Size can only be qi or hi. */
2068 t_gen_sext(t0, cpu_R[dc->op1], size);
2069 cris_alu(dc, CC_OP_SUB,
2070 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
2071 tcg_temp_free(t0);
2072 return 2;
2073 }
2074
2075 static int dec_setclrf(DisasContext *dc)
2076 {
2077 uint32_t flags;
2078 int set = (~dc->opcode >> 2) & 1;
2079
2080
2081 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2082 | EXTRACT_FIELD(dc->ir, 0, 3);
2083 if (set && flags == 0) {
2084 LOG_DIS("nop\n");
2085 return 2;
2086 } else if (!set && (flags & 0x20)) {
2087 LOG_DIS("di\n");
2088 }
2089 else {
2090 LOG_DIS("%sf %x\n",
2091 set ? "set" : "clr",
2092 flags);
2093 }
2094
2095 /* User space is not allowed to touch these. Silently ignore. */
2096 if (dc->tb_flags & U_FLAG) {
2097 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2098 }
2099
2100 if (flags & X_FLAG) {
2101 dc->flagx_known = 1;
2102 if (set)
2103 dc->flags_x = X_FLAG;
2104 else
2105 dc->flags_x = 0;
2106 }
2107
2108 /* Break the TB if any of the SPI flag changes. */
2109 if (flags & (P_FLAG | S_FLAG)) {
2110 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2111 dc->is_jmp = DISAS_UPDATE;
2112 dc->cpustate_changed = 1;
2113 }
2114
2115 /* For the I flag, only act on posedge. */
2116 if ((flags & I_FLAG)) {
2117 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2118 dc->is_jmp = DISAS_UPDATE;
2119 dc->cpustate_changed = 1;
2120 }
2121
2122
2123 /* Simply decode the flags. */
2124 cris_evaluate_flags (dc);
2125 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2126 cris_update_cc_x(dc);
2127 tcg_gen_movi_tl(cc_op, dc->cc_op);
2128
2129 if (set) {
2130 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2131 /* Enter user mode. */
2132 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2133 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2134 dc->cpustate_changed = 1;
2135 }
2136 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2137 }
2138 else
2139 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2140
2141 dc->flags_uptodate = 1;
2142 dc->clear_x = 0;
2143 return 2;
2144 }
2145
2146 static int dec_move_rs(DisasContext *dc)
2147 {
2148 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2149 cris_cc_mask(dc, 0);
2150 gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
2151 return 2;
2152 }
2153 static int dec_move_sr(DisasContext *dc)
2154 {
2155 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2156 cris_cc_mask(dc, 0);
2157 gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
2158 return 2;
2159 }
2160
2161 static int dec_move_rp(DisasContext *dc)
2162 {
2163 TCGv t[2];
2164 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2165 cris_cc_mask(dc, 0);
2166
2167 t[0] = tcg_temp_new();
2168 if (dc->op2 == PR_CCS) {
2169 cris_evaluate_flags(dc);
2170 t_gen_mov_TN_reg(t[0], dc->op1);
2171 if (dc->tb_flags & U_FLAG) {
2172 t[1] = tcg_temp_new();
2173 /* User space is not allowed to touch all flags. */
2174 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2175 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2176 tcg_gen_or_tl(t[0], t[1], t[0]);
2177 tcg_temp_free(t[1]);
2178 }
2179 }
2180 else
2181 t_gen_mov_TN_reg(t[0], dc->op1);
2182
2183 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2184 if (dc->op2 == PR_CCS) {
2185 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2186 dc->flags_uptodate = 1;
2187 }
2188 tcg_temp_free(t[0]);
2189 return 2;
2190 }
2191 static int dec_move_pr(DisasContext *dc)
2192 {
2193 TCGv t0;
2194 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2195 cris_cc_mask(dc, 0);
2196
2197 if (dc->op2 == PR_CCS)
2198 cris_evaluate_flags(dc);
2199
2200 if (dc->op2 == PR_DZ) {
2201 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2202 } else {
2203 t0 = tcg_temp_new();
2204 t_gen_mov_TN_preg(t0, dc->op2);
2205 cris_alu(dc, CC_OP_MOVE,
2206 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2207 preg_sizes[dc->op2]);
2208 tcg_temp_free(t0);
2209 }
2210 return 2;
2211 }
2212
2213 static int dec_move_mr(DisasContext *dc)
2214 {
2215 int memsize = memsize_zz(dc);
2216 int insn_len;
2217 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2218 memsize_char(memsize),
2219 dc->op1, dc->postinc ? "+]" : "]",
2220 dc->op2);
2221
2222 if (memsize == 4) {
2223 insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
2224 cris_cc_mask(dc, CC_MASK_NZ);
2225 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2226 cris_update_cc_x(dc);
2227 cris_update_result(dc, cpu_R[dc->op2]);
2228 }
2229 else {
2230 TCGv t0;
2231
2232 t0 = tcg_temp_new();
2233 insn_len = dec_prep_move_m(dc, 0, memsize, t0);
2234 cris_cc_mask(dc, CC_MASK_NZ);
2235 cris_alu(dc, CC_OP_MOVE,
2236 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2237 tcg_temp_free(t0);
2238 }
2239 do_postinc(dc, memsize);
2240 return insn_len;
2241 }
2242
2243 static inline void cris_alu_m_alloc_temps(TCGv *t)
2244 {
2245 t[0] = tcg_temp_new();
2246 t[1] = tcg_temp_new();
2247 }
2248
2249 static inline void cris_alu_m_free_temps(TCGv *t)
2250 {
2251 tcg_temp_free(t[0]);
2252 tcg_temp_free(t[1]);
2253 }
2254
2255 static int dec_movs_m(DisasContext *dc)
2256 {
2257 TCGv t[2];
2258 int memsize = memsize_z(dc);
2259 int insn_len;
2260 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2261 memsize_char(memsize),
2262 dc->op1, dc->postinc ? "+]" : "]",
2263 dc->op2);
2264
2265 cris_alu_m_alloc_temps(t);
2266 /* sign extend. */
2267 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2268 cris_cc_mask(dc, CC_MASK_NZ);
2269 cris_alu(dc, CC_OP_MOVE,
2270 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2271 do_postinc(dc, memsize);
2272 cris_alu_m_free_temps(t);
2273 return insn_len;
2274 }
2275
2276 static int dec_addu_m(DisasContext *dc)
2277 {
2278 TCGv t[2];
2279 int memsize = memsize_z(dc);
2280 int insn_len;
2281 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2282 memsize_char(memsize),
2283 dc->op1, dc->postinc ? "+]" : "]",
2284 dc->op2);
2285
2286 cris_alu_m_alloc_temps(t);
2287 /* sign extend. */
2288 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2289 cris_cc_mask(dc, CC_MASK_NZVC);
2290 cris_alu(dc, CC_OP_ADD,
2291 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2292 do_postinc(dc, memsize);
2293 cris_alu_m_free_temps(t);
2294 return insn_len;
2295 }
2296
2297 static int dec_adds_m(DisasContext *dc)
2298 {
2299 TCGv t[2];
2300 int memsize = memsize_z(dc);
2301 int insn_len;
2302 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2303 memsize_char(memsize),
2304 dc->op1, dc->postinc ? "+]" : "]",
2305 dc->op2);
2306
2307 cris_alu_m_alloc_temps(t);
2308 /* sign extend. */
2309 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2310 cris_cc_mask(dc, CC_MASK_NZVC);
2311 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2312 do_postinc(dc, memsize);
2313 cris_alu_m_free_temps(t);
2314 return insn_len;
2315 }
2316
2317 static int dec_subu_m(DisasContext *dc)
2318 {
2319 TCGv t[2];
2320 int memsize = memsize_z(dc);
2321 int insn_len;
2322 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2323 memsize_char(memsize),
2324 dc->op1, dc->postinc ? "+]" : "]",
2325 dc->op2);
2326
2327 cris_alu_m_alloc_temps(t);
2328 /* sign extend. */
2329 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2330 cris_cc_mask(dc, CC_MASK_NZVC);
2331 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2332 do_postinc(dc, memsize);
2333 cris_alu_m_free_temps(t);
2334 return insn_len;
2335 }
2336
2337 static int dec_subs_m(DisasContext *dc)
2338 {
2339 TCGv t[2];
2340 int memsize = memsize_z(dc);
2341 int insn_len;
2342 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2343 memsize_char(memsize),
2344 dc->op1, dc->postinc ? "+]" : "]",
2345 dc->op2);
2346
2347 cris_alu_m_alloc_temps(t);
2348 /* sign extend. */
2349 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2350 cris_cc_mask(dc, CC_MASK_NZVC);
2351 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2352 do_postinc(dc, memsize);
2353 cris_alu_m_free_temps(t);
2354 return insn_len;
2355 }
2356
2357 static int dec_movu_m(DisasContext *dc)
2358 {
2359 TCGv t[2];
2360 int memsize = memsize_z(dc);
2361 int insn_len;
2362
2363 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2364 memsize_char(memsize),
2365 dc->op1, dc->postinc ? "+]" : "]",
2366 dc->op2);
2367
2368 cris_alu_m_alloc_temps(t);
2369 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2370 cris_cc_mask(dc, CC_MASK_NZ);
2371 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2372 do_postinc(dc, memsize);
2373 cris_alu_m_free_temps(t);
2374 return insn_len;
2375 }
2376
2377 static int dec_cmpu_m(DisasContext *dc)
2378 {
2379 TCGv t[2];
2380 int memsize = memsize_z(dc);
2381 int insn_len;
2382 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2383 memsize_char(memsize),
2384 dc->op1, dc->postinc ? "+]" : "]",
2385 dc->op2);
2386
2387 cris_alu_m_alloc_temps(t);
2388 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2389 cris_cc_mask(dc, CC_MASK_NZVC);
2390 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2391 do_postinc(dc, memsize);
2392 cris_alu_m_free_temps(t);
2393 return insn_len;
2394 }
2395
2396 static int dec_cmps_m(DisasContext *dc)
2397 {
2398 TCGv t[2];
2399 int memsize = memsize_z(dc);
2400 int insn_len;
2401 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2402 memsize_char(memsize),
2403 dc->op1, dc->postinc ? "+]" : "]",
2404 dc->op2);
2405
2406 cris_alu_m_alloc_temps(t);
2407 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2408 cris_cc_mask(dc, CC_MASK_NZVC);
2409 cris_alu(dc, CC_OP_CMP,
2410 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2411 memsize_zz(dc));
2412 do_postinc(dc, memsize);
2413 cris_alu_m_free_temps(t);
2414 return insn_len;
2415 }
2416
2417 static int dec_cmp_m(DisasContext *dc)
2418 {
2419 TCGv t[2];
2420 int memsize = memsize_zz(dc);
2421 int insn_len;
2422 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2423 memsize_char(memsize),
2424 dc->op1, dc->postinc ? "+]" : "]",
2425 dc->op2);
2426
2427 cris_alu_m_alloc_temps(t);
2428 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2429 cris_cc_mask(dc, CC_MASK_NZVC);
2430 cris_alu(dc, CC_OP_CMP,
2431 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2432 memsize_zz(dc));
2433 do_postinc(dc, memsize);
2434 cris_alu_m_free_temps(t);
2435 return insn_len;
2436 }
2437
2438 static int dec_test_m(DisasContext *dc)
2439 {
2440 TCGv t[2];
2441 int memsize = memsize_zz(dc);
2442 int insn_len;
2443 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2444 memsize_char(memsize),
2445 dc->op1, dc->postinc ? "+]" : "]",
2446 dc->op2);
2447
2448 cris_evaluate_flags(dc);
2449
2450 cris_alu_m_alloc_temps(t);
2451 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2452 cris_cc_mask(dc, CC_MASK_NZ);
2453 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2454
2455 cris_alu(dc, CC_OP_CMP,
2456 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2457 do_postinc(dc, memsize);
2458 cris_alu_m_free_temps(t);
2459 return insn_len;
2460 }
2461
2462 static int dec_and_m(DisasContext *dc)
2463 {
2464 TCGv t[2];
2465 int memsize = memsize_zz(dc);
2466 int insn_len;
2467 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2468 memsize_char(memsize),
2469 dc->op1, dc->postinc ? "+]" : "]",
2470 dc->op2);
2471
2472 cris_alu_m_alloc_temps(t);
2473 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2474 cris_cc_mask(dc, CC_MASK_NZ);
2475 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2476 do_postinc(dc, memsize);
2477 cris_alu_m_free_temps(t);
2478 return insn_len;
2479 }
2480
2481 static int dec_add_m(DisasContext *dc)
2482 {
2483 TCGv t[2];
2484 int memsize = memsize_zz(dc);
2485 int insn_len;
2486 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2487 memsize_char(memsize),
2488 dc->op1, dc->postinc ? "+]" : "]",
2489 dc->op2);
2490
2491 cris_alu_m_alloc_temps(t);
2492 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2493 cris_cc_mask(dc, CC_MASK_NZVC);
2494 cris_alu(dc, CC_OP_ADD,
2495 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2496 do_postinc(dc, memsize);
2497 cris_alu_m_free_temps(t);
2498 return insn_len;
2499 }
2500
2501 static int dec_addo_m(DisasContext *dc)
2502 {
2503 TCGv t[2];
2504 int memsize = memsize_zz(dc);
2505 int insn_len;
2506 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2507 memsize_char(memsize),
2508 dc->op1, dc->postinc ? "+]" : "]",
2509 dc->op2);
2510
2511 cris_alu_m_alloc_temps(t);
2512 insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
2513 cris_cc_mask(dc, 0);
2514 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2515 do_postinc(dc, memsize);
2516 cris_alu_m_free_temps(t);
2517 return insn_len;
2518 }
2519
2520 static int dec_bound_m(DisasContext *dc)
2521 {
2522 TCGv l[2];
2523 int memsize = memsize_zz(dc);
2524 int insn_len;
2525 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2526 memsize_char(memsize),
2527 dc->op1, dc->postinc ? "+]" : "]",
2528 dc->op2);
2529
2530 l[0] = tcg_temp_local_new();
2531 l[1] = tcg_temp_local_new();
2532 insn_len = dec_prep_alu_m(dc, 0, memsize, l[0], l[1]);
2533 cris_cc_mask(dc, CC_MASK_NZ);
2534 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2535 do_postinc(dc, memsize);
2536 tcg_temp_free(l[0]);
2537 tcg_temp_free(l[1]);
2538 return insn_len;
2539 }
2540
2541 static int dec_addc_mr(DisasContext *dc)
2542 {
2543 TCGv t[2];
2544 int insn_len = 2;
2545 LOG_DIS("addc [$r%u%s, $r%u\n",
2546 dc->op1, dc->postinc ? "+]" : "]",
2547 dc->op2);
2548
2549 cris_evaluate_flags(dc);
2550
2551 /* Set for this insn. */
2552 dc->flagx_known = 1;
2553 dc->flags_x = X_FLAG;
2554
2555 cris_alu_m_alloc_temps(t);
2556 insn_len = dec_prep_alu_m(dc, 0, 4, t[0], t[1]);
2557 cris_cc_mask(dc, CC_MASK_NZVC);
2558 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2559 do_postinc(dc, 4);
2560 cris_alu_m_free_temps(t);
2561 return insn_len;
2562 }
2563
2564 static int dec_sub_m(DisasContext *dc)
2565 {
2566 TCGv t[2];
2567 int memsize = memsize_zz(dc);
2568 int insn_len;
2569 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2570 memsize_char(memsize),
2571 dc->op1, dc->postinc ? "+]" : "]",
2572 dc->op2, dc->ir, dc->zzsize);
2573
2574 cris_alu_m_alloc_temps(t);
2575 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2576 cris_cc_mask(dc, CC_MASK_NZVC);
2577 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2578 do_postinc(dc, memsize);
2579 cris_alu_m_free_temps(t);
2580 return insn_len;
2581 }
2582
2583 static int dec_or_m(DisasContext *dc)
2584 {
2585 TCGv t[2];
2586 int memsize = memsize_zz(dc);
2587 int insn_len;
2588 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2589 memsize_char(memsize),
2590 dc->op1, dc->postinc ? "+]" : "]",
2591 dc->op2, dc->pc);
2592
2593 cris_alu_m_alloc_temps(t);
2594 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2595 cris_cc_mask(dc, CC_MASK_NZ);
2596 cris_alu(dc, CC_OP_OR,
2597 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2598 do_postinc(dc, memsize);
2599 cris_alu_m_free_temps(t);
2600 return insn_len;
2601 }
2602
2603 static int dec_move_mp(DisasContext *dc)
2604 {
2605 TCGv t[2];
2606 int memsize = memsize_zz(dc);
2607 int insn_len = 2;
2608
2609 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2610 memsize_char(memsize),
2611 dc->op1,
2612 dc->postinc ? "+]" : "]",
2613 dc->op2);
2614
2615 cris_alu_m_alloc_temps(t);
2616 insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
2617 cris_cc_mask(dc, 0);
2618 if (dc->op2 == PR_CCS) {
2619 cris_evaluate_flags(dc);
2620 if (dc->tb_flags & U_FLAG) {
2621 /* User space is not allowed to touch all flags. */
2622 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2623 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2624 tcg_gen_or_tl(t[1], t[0], t[1]);
2625 }
2626 }
2627
2628 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2629
2630 do_postinc(dc, memsize);
2631 cris_alu_m_free_temps(t);
2632 return insn_len;
2633 }
2634
2635 static int dec_move_pm(DisasContext *dc)
2636 {
2637 TCGv t0;
2638 int memsize;
2639
2640 memsize = preg_sizes[dc->op2];
2641
2642 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2643 memsize_char(memsize),
2644 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2645
2646 /* prepare store. Address in T0, value in T1. */
2647 if (dc->op2 == PR_CCS)
2648 cris_evaluate_flags(dc);
2649 t0 = tcg_temp_new();
2650 t_gen_mov_TN_preg(t0, dc->op2);
2651 cris_flush_cc_state(dc);
2652 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2653 tcg_temp_free(t0);
2654
2655 cris_cc_mask(dc, 0);
2656 if (dc->postinc)
2657 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2658 return 2;
2659 }
2660
2661 static int dec_movem_mr(DisasContext *dc)
2662 {
2663 TCGv_i64 tmp[16];
2664 TCGv tmp32;
2665 TCGv addr;
2666 int i;
2667 int nr = dc->op2 + 1;
2668
2669 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2670 dc->postinc ? "+]" : "]", dc->op2);
2671
2672 addr = tcg_temp_new();
2673 /* There are probably better ways of doing this. */
2674 cris_flush_cc_state(dc);
2675 for (i = 0; i < (nr >> 1); i++) {
2676 tmp[i] = tcg_temp_new_i64();
2677 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2678 gen_load64(dc, tmp[i], addr);
2679 }
2680 if (nr & 1) {
2681 tmp32 = tcg_temp_new_i32();
2682 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2683 gen_load(dc, tmp32, addr, 4, 0);
2684 } else
2685 TCGV_UNUSED(tmp32);
2686 tcg_temp_free(addr);
2687
2688 for (i = 0; i < (nr >> 1); i++) {
2689 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2690 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2691 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2692 tcg_temp_free_i64(tmp[i]);
2693 }
2694 if (nr & 1) {
2695 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2696 tcg_temp_free(tmp32);
2697 }
2698
2699 /* writeback the updated pointer value. */
2700 if (dc->postinc)
2701 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2702
2703 /* gen_load might want to evaluate the previous insns flags. */
2704 cris_cc_mask(dc, 0);
2705 return 2;
2706 }
2707
2708 static int dec_movem_rm(DisasContext *dc)
2709 {
2710 TCGv tmp;
2711 TCGv addr;
2712 int i;
2713
2714 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2715 dc->postinc ? "+]" : "]");
2716
2717 cris_flush_cc_state(dc);
2718
2719 tmp = tcg_temp_new();
2720 addr = tcg_temp_new();
2721 tcg_gen_movi_tl(tmp, 4);
2722 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2723 for (i = 0; i <= dc->op2; i++) {
2724 /* Displace addr. */
2725 /* Perform the store. */
2726 gen_store(dc, addr, cpu_R[i], 4);
2727 tcg_gen_add_tl(addr, addr, tmp);
2728 }
2729 if (dc->postinc)
2730 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2731 cris_cc_mask(dc, 0);
2732 tcg_temp_free(tmp);
2733 tcg_temp_free(addr);
2734 return 2;
2735 }
2736
2737 static int dec_move_rm(DisasContext *dc)
2738 {
2739 int memsize;
2740
2741 memsize = memsize_zz(dc);
2742
2743 LOG_DIS("move.%c $r%u, [$r%u]\n",
2744 memsize_char(memsize), dc->op2, dc->op1);
2745
2746 /* prepare store. */
2747 cris_flush_cc_state(dc);
2748 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2749
2750 if (dc->postinc)
2751 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2752 cris_cc_mask(dc, 0);
2753 return 2;
2754 }
2755
2756 static int dec_lapcq(DisasContext *dc)
2757 {
2758 LOG_DIS("lapcq %x, $r%u\n",
2759 dc->pc + dc->op1*2, dc->op2);
2760 cris_cc_mask(dc, 0);
2761 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2762 return 2;
2763 }
2764
2765 static int dec_lapc_im(DisasContext *dc)
2766 {
2767 unsigned int rd;
2768 int32_t imm;
2769 int32_t pc;
2770
2771 rd = dc->op2;
2772
2773 cris_cc_mask(dc, 0);
2774 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2775 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2776
2777 pc = dc->pc;
2778 pc += imm;
2779 tcg_gen_movi_tl(cpu_R[rd], pc);
2780 return 6;
2781 }
2782
2783 /* Jump to special reg. */
2784 static int dec_jump_p(DisasContext *dc)
2785 {
2786 LOG_DIS("jump $p%u\n", dc->op2);
2787
2788 if (dc->op2 == PR_CCS)
2789 cris_evaluate_flags(dc);
2790 t_gen_mov_TN_preg(env_btarget, dc->op2);
2791 /* rete will often have low bit set to indicate delayslot. */
2792 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2793 cris_cc_mask(dc, 0);
2794 cris_prepare_jmp(dc, JMP_INDIRECT);
2795 return 2;
2796 }
2797
2798 /* Jump and save. */
2799 static int dec_jas_r(DisasContext *dc)
2800 {
2801 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2802 cris_cc_mask(dc, 0);
2803 /* Store the return address in Pd. */
2804 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2805 if (dc->op2 > 15)
2806 abort();
2807 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2808
2809 cris_prepare_jmp(dc, JMP_INDIRECT);
2810 return 2;
2811 }
2812
2813 static int dec_jas_im(DisasContext *dc)
2814 {
2815 uint32_t imm;
2816
2817 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2818
2819 LOG_DIS("jas 0x%x\n", imm);
2820 cris_cc_mask(dc, 0);
2821 /* Store the return address in Pd. */
2822 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2823
2824 dc->jmp_pc = imm;
2825 cris_prepare_jmp(dc, JMP_DIRECT);
2826 return 6;
2827 }
2828
2829 static int dec_jasc_im(DisasContext *dc)
2830 {
2831 uint32_t imm;
2832
2833 imm = cris_fetch(dc, dc->pc + 2, 4, 0);
2834
2835 LOG_DIS("jasc 0x%x\n", imm);
2836 cris_cc_mask(dc, 0);
2837 /* Store the return address in Pd. */
2838 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2839
2840 dc->jmp_pc = imm;
2841 cris_prepare_jmp(dc, JMP_DIRECT);
2842 return 6;
2843 }
2844
2845 static int dec_jasc_r(DisasContext *dc)
2846 {
2847 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2848 cris_cc_mask(dc, 0);
2849 /* Store the return address in Pd. */
2850 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2851 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2852 cris_prepare_jmp(dc, JMP_INDIRECT);
2853 return 2;
2854 }
2855
2856 static int dec_bcc_im(DisasContext *dc)
2857 {
2858 int32_t offset;
2859 uint32_t cond = dc->op2;
2860
2861 offset = cris_fetch(dc, dc->pc + 2, 2, 1);
2862
2863 LOG_DIS("b%s %d pc=%x dst=%x\n",
2864 cc_name(cond), offset,
2865 dc->pc, dc->pc + offset);
2866
2867 cris_cc_mask(dc, 0);
2868 /* op2 holds the condition-code. */
2869 cris_prepare_cc_branch (dc, offset, cond);
2870 return 4;
2871 }
2872
2873 static int dec_bas_im(DisasContext *dc)
2874 {
2875 int32_t simm;
2876
2877
2878 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2879
2880 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2881 cris_cc_mask(dc, 0);
2882 /* Store the return address in Pd. */
2883 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2884
2885 dc->jmp_pc = dc->pc + simm;
2886 cris_prepare_jmp(dc, JMP_DIRECT);
2887 return 6;
2888 }
2889
2890 static int dec_basc_im(DisasContext *dc)
2891 {
2892 int32_t simm;
2893 simm = cris_fetch(dc, dc->pc + 2, 4, 0);
2894
2895 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2896 cris_cc_mask(dc, 0);
2897 /* Store the return address in Pd. */
2898 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2899
2900 dc->jmp_pc = dc->pc + simm;
2901 cris_prepare_jmp(dc, JMP_DIRECT);
2902 return 6;
2903 }
2904
2905 static int dec_rfe_etc(DisasContext *dc)
2906 {
2907 cris_cc_mask(dc, 0);
2908
2909 if (dc->op2 == 15) {
2910 t_gen_mov_env_TN(halted, tcg_const_tl(1));
2911 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2912 t_gen_raise_exception(EXCP_HLT);
2913 return 2;
2914 }
2915
2916 switch (dc->op2 & 7) {
2917 case 2:
2918 /* rfe. */
2919 LOG_DIS("rfe\n");
2920 cris_evaluate_flags(dc);
2921 gen_helper_rfe();
2922 dc->is_jmp = DISAS_UPDATE;
2923 break;
2924 case 5:
2925 /* rfn. */
2926 LOG_DIS("rfn\n");
2927 cris_evaluate_flags(dc);
2928 gen_helper_rfn();
2929 dc->is_jmp = DISAS_UPDATE;
2930 break;
2931 case 6:
2932 LOG_DIS("break %d\n", dc->op1);
2933 cris_evaluate_flags (dc);
2934 /* break. */
2935 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2936
2937 /* Breaks start at 16 in the exception vector. */
2938 t_gen_mov_env_TN(trap_vector,
2939 tcg_const_tl(dc->op1 + 16));
2940 t_gen_raise_exception(EXCP_BREAK);
2941 dc->is_jmp = DISAS_UPDATE;
2942 break;
2943 default:
2944 printf ("op2=%x\n", dc->op2);
2945 BUG();
2946 break;
2947
2948 }
2949 return 2;
2950 }
2951
2952 static int dec_ftag_fidx_d_m(DisasContext *dc)
2953 {
2954 return 2;
2955 }
2956
2957 static int dec_ftag_fidx_i_m(DisasContext *dc)
2958 {
2959 return 2;
2960 }
2961
2962 static int dec_null(DisasContext *dc)
2963 {
2964 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2965 dc->pc, dc->opcode, dc->op1, dc->op2);
2966 fflush(NULL);
2967 BUG();
2968 return 2;
2969 }
2970
2971 static struct decoder_info {
2972 struct {
2973 uint32_t bits;
2974 uint32_t mask;
2975 };
2976 int (*dec)(DisasContext *dc);
2977 } decinfo[] = {
2978 /* Order matters here. */
2979 {DEC_MOVEQ, dec_moveq},
2980 {DEC_BTSTQ, dec_btstq},
2981 {DEC_CMPQ, dec_cmpq},
2982 {DEC_ADDOQ, dec_addoq},
2983 {DEC_ADDQ, dec_addq},
2984 {DEC_SUBQ, dec_subq},
2985 {DEC_ANDQ, dec_andq},
2986 {DEC_ORQ, dec_orq},
2987 {DEC_ASRQ, dec_asrq},
2988 {DEC_LSLQ, dec_lslq},
2989 {DEC_LSRQ, dec_lsrq},
2990 {DEC_BCCQ, dec_bccq},
2991
2992 {DEC_BCC_IM, dec_bcc_im},
2993 {DEC_JAS_IM, dec_jas_im},
2994 {DEC_JAS_R, dec_jas_r},
2995 {DEC_JASC_IM, dec_jasc_im},
2996 {DEC_JASC_R, dec_jasc_r},
2997 {DEC_BAS_IM, dec_bas_im},
2998 {DEC_BASC_IM, dec_basc_im},
2999 {DEC_JUMP_P, dec_jump_p},
3000 {DEC_LAPC_IM, dec_lapc_im},
3001 {DEC_LAPCQ, dec_lapcq},
3002
3003 {DEC_RFE_ETC, dec_rfe_etc},
3004 {DEC_ADDC_MR, dec_addc_mr},
3005
3006 {DEC_MOVE_MP, dec_move_mp},
3007 {DEC_MOVE_PM, dec_move_pm},
3008 {DEC_MOVEM_MR, dec_movem_mr},
3009 {DEC_MOVEM_RM, dec_movem_rm},
3010 {DEC_MOVE_PR, dec_move_pr},
3011 {DEC_SCC_R, dec_scc_r},
3012 {DEC_SETF, dec_setclrf},
3013 {DEC_CLEARF, dec_setclrf},
3014
3015 {DEC_MOVE_SR, dec_move_sr},
3016 {DEC_MOVE_RP, dec_move_rp},
3017 {DEC_SWAP_R, dec_swap_r},
3018 {DEC_ABS_R, dec_abs_r},
3019 {DEC_LZ_R, dec_lz_r},
3020 {DEC_MOVE_RS, dec_move_rs},
3021 {DEC_BTST_R, dec_btst_r},
3022 {DEC_ADDC_R, dec_addc_r},
3023
3024 {DEC_DSTEP_R, dec_dstep_r},
3025 {DEC_XOR_R, dec_xor_r},
3026 {DEC_MCP_R, dec_mcp_r},
3027 {DEC_CMP_R, dec_cmp_r},
3028
3029 {DEC_ADDI_R, dec_addi_r},
3030 {DEC_ADDI_ACR, dec_addi_acr},
3031
3032 {DEC_ADD_R, dec_add_r},
3033 {DEC_SUB_R, dec_sub_r},
3034
3035 {DEC_ADDU_R, dec_addu_r},
3036 {DEC_ADDS_R, dec_adds_r},
3037 {DEC_SUBU_R, dec_subu_r},
3038 {DEC_SUBS_R, dec_subs_r},
3039 {DEC_LSL_R, dec_lsl_r},
3040
3041 {DEC_AND_R, dec_and_r},
3042 {DEC_OR_R, dec_or_r},
3043 {DEC_BOUND_R, dec_bound_r},
3044 {DEC_ASR_R, dec_asr_r},
3045 {DEC_LSR_R, dec_lsr_r},
3046
3047 {DEC_MOVU_R, dec_movu_r},
3048 {DEC_MOVS_R, dec_movs_r},
3049 {DEC_NEG_R, dec_neg_r},
3050 {DEC_MOVE_R, dec_move_r},
3051
3052 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
3053 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
3054
3055 {DEC_MULS_R, dec_muls_r},
3056 {DEC_MULU_R, dec_mulu_r},
3057
3058 {DEC_ADDU_M, dec_addu_m},
3059 {DEC_ADDS_M, dec_adds_m},
3060 {DEC_SUBU_M, dec_subu_m},
3061 {DEC_SUBS_M, dec_subs_m},
3062
3063 {DEC_CMPU_M, dec_cmpu_m},
3064 {DEC_CMPS_M, dec_cmps_m},
3065 {DEC_MOVU_M, dec_movu_m},
3066 {DEC_MOVS_M, dec_movs_m},
3067
3068 {DEC_CMP_M, dec_cmp_m},
3069 {DEC_ADDO_M, dec_addo_m},
3070 {DEC_BOUND_M, dec_bound_m},
3071 {DEC_ADD_M, dec_add_m},
3072 {DEC_SUB_M, dec_sub_m},
3073 {DEC_AND_M, dec_and_m},
3074 {DEC_OR_M, dec_or_m},
3075 {DEC_MOVE_RM, dec_move_rm},
3076 {DEC_TEST_M, dec_test_m},
3077 {DEC_MOVE_MR, dec_move_mr},
3078
3079 {{0, 0}, dec_null}
3080 };
3081
3082 static unsigned int crisv32_decoder(DisasContext *dc)
3083 {
3084 int insn_len = 2;
3085 int i;
3086
3087 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
3088 tcg_gen_debug_insn_start(dc->pc);
3089
3090 /* Load a halfword onto the instruction register. */
3091 dc->ir = cris_fetch(dc, dc->pc, 2, 0);
3092
3093 /* Now decode it. */
3094 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3095 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3096 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3097 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3098 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3099 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3100
3101 /* Large switch for all insns. */
3102 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3103 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
3104 {
3105 insn_len = decinfo[i].dec(dc);
3106 break;
3107 }
3108 }
3109
3110 #if !defined(CONFIG_USER_ONLY)
3111 /* Single-stepping ? */
3112 if (dc->tb_flags & S_FLAG) {
3113 int l1;
3114
3115 l1 = gen_new_label();
3116 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3117 /* We treat SPC as a break with an odd trap vector. */
3118 cris_evaluate_flags (dc);
3119 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3120 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3121 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3122 t_gen_raise_exception(EXCP_BREAK);
3123 gen_set_label(l1);
3124 }
3125 #endif
3126 return insn_len;
3127 }
3128
3129 static void check_breakpoint(CPUState *env, DisasContext *dc)
3130 {
3131 CPUBreakpoint *bp;
3132
3133 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
3134 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
3135 if (bp->pc == dc->pc) {
3136 cris_evaluate_flags (dc);
3137 tcg_gen_movi_tl(env_pc, dc->pc);
3138 t_gen_raise_exception(EXCP_DEBUG);
3139 dc->is_jmp = DISAS_UPDATE;
3140 }
3141 }
3142 }
3143 }
3144
3145 #include "translate_v10.c"
3146
3147 /*
3148 * Delay slots on QEMU/CRIS.
3149 *
3150 * If an exception hits on a delayslot, the core will let ERP (the Exception
3151 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3152 * to give SW a hint that the exception actually hit on the dslot.
3153 *
3154 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3155 * the core and any jmp to an odd addresses will mask off that lsb. It is
3156 * simply there to let sw know there was an exception on a dslot.
3157 *
3158 * When the software returns from an exception, the branch will re-execute.
3159 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3160 * and the branch and delayslot dont share pages.
3161 *
3162 * The TB contaning the branch insn will set up env->btarget and evaluate
3163 * env->btaken. When the translation loop exits we will note that the branch
3164 * sequence is broken and let env->dslot be the size of the branch insn (those
3165 * vary in length).
3166 *
3167 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3168 * set). It will also expect to have env->dslot setup with the size of the
3169 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3170 * will execute the dslot and take the branch, either to btarget or just one
3171 * insn ahead.
3172 *
3173 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3174 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3175 * branch and set lsb). Then env->dslot gets cleared so that the exception
3176 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3177 * masked off and we will reexecute the branch insn.
3178 *
3179 */
3180
3181 /* generate intermediate code for basic block 'tb'. */
3182 static void
3183 gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
3184 int search_pc)
3185 {
3186 uint16_t *gen_opc_end;
3187 uint32_t pc_start;
3188 unsigned int insn_len;
3189 int j, lj;
3190 struct DisasContext ctx;
3191 struct DisasContext *dc = &ctx;
3192 uint32_t next_page_start;
3193 target_ulong npc;
3194 int num_insns;
3195 int max_insns;
3196
3197 qemu_log_try_set_file(stderr);
3198
3199 if (env->pregs[PR_VR] == 32) {
3200 dc->decoder = crisv32_decoder;
3201 dc->clear_locked_irq = 0;
3202 } else {
3203 dc->decoder = crisv10_decoder;
3204 dc->clear_locked_irq = 1;
3205 }
3206
3207 /* Odd PC indicates that branch is rexecuting due to exception in the
3208 * delayslot, like in real hw.
3209 */
3210 pc_start = tb->pc & ~1;
3211 dc->env = env;
3212 dc->tb = tb;
3213
3214 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
3215
3216 dc->is_jmp = DISAS_NEXT;
3217 dc->ppc = pc_start;
3218 dc->pc = pc_start;
3219 dc->singlestep_enabled = env->singlestep_enabled;
3220 dc->flags_uptodate = 1;
3221 dc->flagx_known = 1;
3222 dc->flags_x = tb->flags & X_FLAG;
3223 dc->cc_x_uptodate = 0;
3224 dc->cc_mask = 0;
3225 dc->update_cc = 0;
3226 dc->clear_prefix = 0;
3227
3228 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3229 dc->cc_size_uptodate = -1;
3230
3231 /* Decode TB flags. */
3232 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3233 | X_FLAG | PFIX_FLAG);
3234 dc->delayed_branch = !!(tb->flags & 7);
3235 if (dc->delayed_branch)
3236 dc->jmp = JMP_INDIRECT;
3237 else
3238 dc->jmp = JMP_NOJMP;
3239
3240 dc->cpustate_changed = 0;
3241
3242 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3243 qemu_log(
3244 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3245 "pid=%x usp=%x\n"
3246 "%x.%x.%x.%x\n"
3247 "%x.%x.%x.%x\n"
3248 "%x.%x.%x.%x\n"
3249 "%x.%x.%x.%x\n",
3250 search_pc, dc->pc, dc->ppc,
3251 (uint64_t)tb->flags,
3252 env->btarget, (unsigned)tb->flags & 7,
3253 env->pregs[PR_CCS],
3254 env->pregs[PR_PID], env->pregs[PR_USP],
3255 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3256 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3257 env->regs[8], env->regs[9],
3258 env->regs[10], env->regs[11],
3259 env->regs[12], env->regs[13],
3260 env->regs[14], env->regs[15]);
3261 qemu_log("--------------\n");
3262 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3263 }
3264
3265 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3266 lj = -1;
3267 num_insns = 0;
3268 max_insns = tb->cflags & CF_COUNT_MASK;
3269 if (max_insns == 0)
3270 max_insns = CF_COUNT_MASK;
3271
3272 gen_icount_start();
3273 do
3274 {
3275 check_breakpoint(env, dc);
3276
3277 if (search_pc) {
3278 j = gen_opc_ptr - gen_opc_buf;
3279 if (lj < j) {
3280 lj++;
3281 while (lj < j)
3282 gen_opc_instr_start[lj++] = 0;
3283 }
3284 if (dc->delayed_branch == 1)
3285 gen_opc_pc[lj] = dc->ppc | 1;
3286 else
3287 gen_opc_pc[lj] = dc->pc;
3288 gen_opc_instr_start[lj] = 1;
3289 gen_opc_icount[lj] = num_insns;
3290 }
3291
3292 /* Pretty disas. */
3293 LOG_DIS("%8.8x:\t", dc->pc);
3294
3295 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
3296 gen_io_start();
3297 dc->clear_x = 1;
3298
3299 insn_len = dc->decoder(dc);
3300 dc->ppc = dc->pc;
3301 dc->pc += insn_len;
3302 if (dc->clear_x)
3303 cris_clear_x_flag(dc);
3304
3305 num_insns++;
3306 /* Check for delayed branches here. If we do it before
3307 actually generating any host code, the simulator will just
3308 loop doing nothing for on this program location. */
3309 if (dc->delayed_branch) {
3310 dc->delayed_branch--;
3311 if (dc->delayed_branch == 0)
3312 {
3313 if (tb->flags & 7)
3314 t_gen_mov_env_TN(dslot,
3315 tcg_const_tl(0));
3316 if (dc->cpustate_changed || !dc->flagx_known
3317 || (dc->flags_x != (tb->flags & X_FLAG))) {
3318 cris_store_direct_jmp(dc);
3319 }
3320
3321 if (dc->clear_locked_irq) {
3322 dc->clear_locked_irq = 0;
3323 t_gen_mov_env_TN(locked_irq,
3324 tcg_const_tl(0));
3325 }
3326
3327 if (dc->jmp == JMP_DIRECT_CC) {
3328 int l1;
3329
3330 l1 = gen_new_label();
3331 cris_evaluate_flags(dc);
3332
3333 /* Conditional jmp. */
3334 tcg_gen_brcondi_tl(TCG_COND_EQ,
3335 env_btaken, 0, l1);
3336 gen_goto_tb(dc, 1, dc->jmp_pc);
3337 gen_set_label(l1);
3338 gen_goto_tb(dc, 0, dc->pc);
3339 dc->is_jmp = DISAS_TB_JUMP;
3340 dc->jmp = JMP_NOJMP;
3341 } else if (dc->jmp == JMP_DIRECT) {
3342 cris_evaluate_flags(dc);
3343 gen_goto_tb(dc, 0, dc->jmp_pc);
3344 dc->is_jmp = DISAS_TB_JUMP;
3345 dc->jmp = JMP_NOJMP;
3346 } else {
3347 t_gen_cc_jmp(env_btarget,
3348 tcg_const_tl(dc->pc));
3349 dc->is_jmp = DISAS_JUMP;
3350 }
3351 break;
3352 }
3353 }
3354
3355 /* If we are rexecuting a branch due to exceptions on
3356 delay slots dont break. */
3357 if (!(tb->pc & 1) && env->singlestep_enabled)
3358 break;
3359 } while (!dc->is_jmp && !dc->cpustate_changed
3360 && gen_opc_ptr < gen_opc_end
3361 && !singlestep
3362 && (dc->pc < next_page_start)
3363 && num_insns < max_insns);
3364
3365 if (dc->clear_locked_irq)
3366 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3367
3368 npc = dc->pc;
3369
3370 if (tb->cflags & CF_LAST_IO)
3371 gen_io_end();
3372 /* Force an update if the per-tb cpu state has changed. */
3373 if (dc->is_jmp == DISAS_NEXT
3374 && (dc->cpustate_changed || !dc->flagx_known
3375 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3376 dc->is_jmp = DISAS_UPDATE;
3377 tcg_gen_movi_tl(env_pc, npc);
3378 }
3379 /* Broken branch+delayslot sequence. */
3380 if (dc->delayed_branch == 1) {
3381 /* Set env->dslot to the size of the branch insn. */
3382 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3383 cris_store_direct_jmp(dc);
3384 }
3385
3386 cris_evaluate_flags (dc);
3387
3388 if (unlikely(env->singlestep_enabled)) {
3389 if (dc->is_jmp == DISAS_NEXT)
3390 tcg_gen_movi_tl(env_pc, npc);
3391 t_gen_raise_exception(EXCP_DEBUG);
3392 } else {
3393 switch(dc->is_jmp) {
3394 case DISAS_NEXT:
3395 gen_goto_tb(dc, 1, npc);
3396 break;
3397 default:
3398 case DISAS_JUMP:
3399 case DISAS_UPDATE:
3400 /* indicate that the hash table must be used
3401 to find the next TB */
3402 tcg_gen_exit_tb(0);
3403 break;
3404 case DISAS_SWI:
3405 case DISAS_TB_JUMP:
3406 /* nothing more to generate */
3407 break;
3408 }
3409 }
3410 gen_icount_end(tb, num_insns);
3411 *gen_opc_ptr = INDEX_op_end;
3412 if (search_pc) {
3413 j = gen_opc_ptr - gen_opc_buf;
3414 lj++;
3415 while (lj <= j)
3416 gen_opc_instr_start[lj++] = 0;
3417 } else {
3418 tb->size = dc->pc - pc_start;
3419 tb->icount = num_insns;
3420 }
3421
3422 #ifdef DEBUG_DISAS
3423 #if !DISAS_CRIS
3424 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3425 log_target_disas(pc_start, dc->pc - pc_start,
3426 dc->env->pregs[PR_VR]);
3427 qemu_log("\nisize=%d osize=%td\n",
3428 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
3429 }
3430 #endif
3431 #endif
3432 }
3433
3434 void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
3435 {
3436 gen_intermediate_code_internal(env, tb, 0);
3437 }
3438
3439 void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
3440 {
3441 gen_intermediate_code_internal(env, tb, 1);
3442 }
3443
3444 void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf,
3445 int flags)
3446 {
3447 int i;
3448 uint32_t srs;
3449
3450 if (!env || !f)
3451 return;
3452
3453 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3454 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3455 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3456 env->cc_op,
3457 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3458
3459
3460 for (i = 0; i < 16; i++) {
3461 cpu_fprintf(f, "%s=%8.8x ",regnames[i], env->regs[i]);
3462 if ((i + 1) % 4 == 0)
3463 cpu_fprintf(f, "\n");
3464 }
3465 cpu_fprintf(f, "\nspecial regs:\n");
3466 for (i = 0; i < 16; i++) {
3467 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3468 if ((i + 1) % 4 == 0)
3469 cpu_fprintf(f, "\n");
3470 }
3471 srs = env->pregs[PR_SRS];
3472 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3473 if (srs < 256) {
3474 for (i = 0; i < 16; i++) {
3475 cpu_fprintf(f, "s%2.2d=%8.8x ",
3476 i, env->sregs[srs][i]);
3477 if ((i + 1) % 4 == 0)
3478 cpu_fprintf(f, "\n");
3479 }
3480 }
3481 cpu_fprintf(f, "\n\n");
3482
3483 }
3484
3485 struct
3486 {
3487 uint32_t vr;
3488 const char *name;
3489 } cris_cores[] = {
3490 {8, "crisv8"},
3491 {9, "crisv9"},
3492 {10, "crisv10"},
3493 {11, "crisv11"},
3494 {32, "crisv32"},
3495 };
3496
3497 void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf)
3498 {
3499 unsigned int i;
3500
3501 (*cpu_fprintf)(f, "Available CPUs:\n");
3502 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3503 (*cpu_fprintf)(f, " %s\n", cris_cores[i].name);
3504 }
3505 }
3506
3507 static uint32_t vr_by_name(const char *name)
3508 {
3509 unsigned int i;
3510 for (i = 0; i < ARRAY_SIZE(cris_cores); i++) {
3511 if (strcmp(name, cris_cores[i].name) == 0) {
3512 return cris_cores[i].vr;
3513 }
3514 }
3515 return 32;
3516 }
3517
3518 CPUCRISState *cpu_cris_init (const char *cpu_model)
3519 {
3520 CPUCRISState *env;
3521 static int tcg_initialized = 0;
3522 int i;
3523
3524 env = qemu_mallocz(sizeof(CPUCRISState));
3525
3526 env->pregs[PR_VR] = vr_by_name(cpu_model);
3527 cpu_exec_init(env);
3528 cpu_reset(env);
3529 qemu_init_vcpu(env);
3530
3531 if (tcg_initialized)
3532 return env;
3533
3534 tcg_initialized = 1;
3535
3536 #define GEN_HELPER 2
3537 #include "helper.h"
3538
3539 if (env->pregs[PR_VR] < 32) {
3540 cpu_crisv10_init(env);
3541 return env;
3542 }
3543
3544
3545 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3546 cc_x = tcg_global_mem_new(TCG_AREG0,
3547 offsetof(CPUState, cc_x), "cc_x");
3548 cc_src = tcg_global_mem_new(TCG_AREG0,
3549 offsetof(CPUState, cc_src), "cc_src");
3550 cc_dest = tcg_global_mem_new(TCG_AREG0,
3551 offsetof(CPUState, cc_dest),
3552 "cc_dest");
3553 cc_result = tcg_global_mem_new(TCG_AREG0,
3554 offsetof(CPUState, cc_result),
3555 "cc_result");
3556 cc_op = tcg_global_mem_new(TCG_AREG0,
3557 offsetof(CPUState, cc_op), "cc_op");
3558 cc_size = tcg_global_mem_new(TCG_AREG0,
3559 offsetof(CPUState, cc_size),
3560 "cc_size");
3561 cc_mask = tcg_global_mem_new(TCG_AREG0,
3562 offsetof(CPUState, cc_mask),
3563 "cc_mask");
3564
3565 env_pc = tcg_global_mem_new(TCG_AREG0,
3566 offsetof(CPUState, pc),
3567 "pc");
3568 env_btarget = tcg_global_mem_new(TCG_AREG0,
3569 offsetof(CPUState, btarget),
3570 "btarget");
3571 env_btaken = tcg_global_mem_new(TCG_AREG0,
3572 offsetof(CPUState, btaken),
3573 "btaken");
3574 for (i = 0; i < 16; i++) {
3575 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3576 offsetof(CPUState, regs[i]),
3577 regnames[i]);
3578 }
3579 for (i = 0; i < 16; i++) {
3580 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3581 offsetof(CPUState, pregs[i]),
3582 pregnames[i]);
3583 }
3584
3585 return env;
3586 }
3587
3588 void cpu_reset (CPUCRISState *env)
3589 {
3590 uint32_t vr;
3591
3592 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
3593 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
3594 log_cpu_state(env, 0);
3595 }
3596
3597 vr = env->pregs[PR_VR];
3598 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3599 env->pregs[PR_VR] = vr;
3600 tlb_flush(env, 1);
3601
3602 #if defined(CONFIG_USER_ONLY)
3603 /* start in user mode with interrupts enabled. */
3604 env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG;
3605 #else
3606 cris_mmu_init(env);
3607 env->pregs[PR_CCS] = 0;
3608 #endif
3609 }
3610
3611 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3612 unsigned long searched_pc, int pc_pos, void *puc)
3613 {
3614 env->pc = gen_opc_pc[pc_pos];
3615 }
various patches