Merge branch 'master' of git://git.qemu.org/qemu
[qemu/mdroth.git] / hw / ioapic.c
blob6c26e820e05a463d4de04c1b7688f8c2fee2aa49
1 /*
2 * ioapic.c IOAPIC emulation logic
4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * Split the ioapic logic from apic.c
7 * Xiantao Zhang <xiantao.zhang@intel.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "hw.h"
24 #include "pc.h"
25 #include "apic.h"
26 #include "ioapic.h"
27 #include "qemu-timer.h"
28 #include "host-utils.h"
29 #include "sysbus.h"
31 //#define DEBUG_IOAPIC
33 #ifdef DEBUG_IOAPIC
34 #define DPRINTF(fmt, ...) \
35 do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
36 #else
37 #define DPRINTF(fmt, ...)
38 #endif
40 #define MAX_IOAPICS 1
42 #define IOAPIC_VERSION 0x11
44 #define IOAPIC_LVT_DEST_SHIFT 56
45 #define IOAPIC_LVT_MASKED_SHIFT 16
46 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT 15
47 #define IOAPIC_LVT_REMOTE_IRR_SHIFT 14
48 #define IOAPIC_LVT_POLARITY_SHIFT 13
49 #define IOAPIC_LVT_DELIV_STATUS_SHIFT 12
50 #define IOAPIC_LVT_DEST_MODE_SHIFT 11
51 #define IOAPIC_LVT_DELIV_MODE_SHIFT 8
53 #define IOAPIC_LVT_MASKED (1 << IOAPIC_LVT_MASKED_SHIFT)
54 #define IOAPIC_LVT_REMOTE_IRR (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
56 #define IOAPIC_TRIGGER_EDGE 0
57 #define IOAPIC_TRIGGER_LEVEL 1
59 /*io{apic,sapic} delivery mode*/
60 #define IOAPIC_DM_FIXED 0x0
61 #define IOAPIC_DM_LOWEST_PRIORITY 0x1
62 #define IOAPIC_DM_PMI 0x2
63 #define IOAPIC_DM_NMI 0x4
64 #define IOAPIC_DM_INIT 0x5
65 #define IOAPIC_DM_SIPI 0x6
66 #define IOAPIC_DM_EXTINT 0x7
67 #define IOAPIC_DM_MASK 0x7
69 #define IOAPIC_VECTOR_MASK 0xff
71 #define IOAPIC_IOREGSEL 0x00
72 #define IOAPIC_IOWIN 0x10
74 #define IOAPIC_REG_ID 0x00
75 #define IOAPIC_REG_VER 0x01
76 #define IOAPIC_REG_ARB 0x02
77 #define IOAPIC_REG_REDTBL_BASE 0x10
78 #define IOAPIC_ID 0x00
80 #define IOAPIC_ID_SHIFT 24
81 #define IOAPIC_ID_MASK 0xf
83 #define IOAPIC_VER_ENTRIES_SHIFT 16
85 typedef struct IOAPICState IOAPICState;
87 struct IOAPICState {
88 SysBusDevice busdev;
89 uint8_t id;
90 uint8_t ioregsel;
91 uint32_t irr;
92 uint64_t ioredtbl[IOAPIC_NUM_PINS];
95 static IOAPICState *ioapics[MAX_IOAPICS];
97 static void ioapic_service(IOAPICState *s)
99 uint8_t i;
100 uint8_t trig_mode;
101 uint8_t vector;
102 uint8_t delivery_mode;
103 uint32_t mask;
104 uint64_t entry;
105 uint8_t dest;
106 uint8_t dest_mode;
107 uint8_t polarity;
109 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
110 mask = 1 << i;
111 if (s->irr & mask) {
112 entry = s->ioredtbl[i];
113 if (!(entry & IOAPIC_LVT_MASKED)) {
114 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
115 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
116 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
117 delivery_mode =
118 (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
119 polarity = (entry >> IOAPIC_LVT_POLARITY_SHIFT) & 1;
120 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
121 s->irr &= ~mask;
122 } else {
123 s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
125 if (delivery_mode == IOAPIC_DM_EXTINT) {
126 vector = pic_read_irq(isa_pic);
127 } else {
128 vector = entry & IOAPIC_VECTOR_MASK;
130 apic_deliver_irq(dest, dest_mode, delivery_mode,
131 vector, polarity, trig_mode);
137 static void ioapic_set_irq(void *opaque, int vector, int level)
139 IOAPICState *s = opaque;
141 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
142 * to GSI 2. GSI maps to ioapic 1-1. This is not
143 * the cleanest way of doing it but it should work. */
145 DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
146 if (vector == 0) {
147 vector = 2;
149 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
150 uint32_t mask = 1 << vector;
151 uint64_t entry = s->ioredtbl[vector];
153 if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
154 IOAPIC_TRIGGER_LEVEL) {
155 /* level triggered */
156 if (level) {
157 s->irr |= mask;
158 ioapic_service(s);
159 } else {
160 s->irr &= ~mask;
162 } else {
163 /* According to the 82093AA manual, we must ignore edge requests
164 * if the input pin is masked. */
165 if (level && !(entry & IOAPIC_LVT_MASKED)) {
166 s->irr |= mask;
167 ioapic_service(s);
173 void ioapic_eoi_broadcast(int vector)
175 IOAPICState *s;
176 uint64_t entry;
177 int i, n;
179 for (i = 0; i < MAX_IOAPICS; i++) {
180 s = ioapics[i];
181 if (!s) {
182 continue;
184 for (n = 0; n < IOAPIC_NUM_PINS; n++) {
185 entry = s->ioredtbl[n];
186 if ((entry & IOAPIC_LVT_REMOTE_IRR)
187 && (entry & IOAPIC_VECTOR_MASK) == vector) {
188 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
189 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
190 ioapic_service(s);
197 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
199 IOAPICState *s = opaque;
200 int index;
201 uint32_t val = 0;
203 switch (addr & 0xff) {
204 case IOAPIC_IOREGSEL:
205 val = s->ioregsel;
206 break;
207 case IOAPIC_IOWIN:
208 switch (s->ioregsel) {
209 case IOAPIC_REG_ID:
210 val = s->id << IOAPIC_ID_SHIFT;
211 break;
212 case IOAPIC_REG_VER:
213 val = IOAPIC_VERSION |
214 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
215 break;
216 case IOAPIC_REG_ARB:
217 val = 0;
218 break;
219 default:
220 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
221 if (index >= 0 && index < IOAPIC_NUM_PINS) {
222 if (s->ioregsel & 1) {
223 val = s->ioredtbl[index] >> 32;
224 } else {
225 val = s->ioredtbl[index] & 0xffffffff;
229 DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
230 break;
232 return val;
235 static void
236 ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
238 IOAPICState *s = opaque;
239 int index;
241 switch (addr & 0xff) {
242 case IOAPIC_IOREGSEL:
243 s->ioregsel = val;
244 break;
245 case IOAPIC_IOWIN:
246 DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
247 switch (s->ioregsel) {
248 case IOAPIC_REG_ID:
249 s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
250 break;
251 case IOAPIC_REG_VER:
252 case IOAPIC_REG_ARB:
253 break;
254 default:
255 index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
256 if (index >= 0 && index < IOAPIC_NUM_PINS) {
257 if (s->ioregsel & 1) {
258 s->ioredtbl[index] &= 0xffffffff;
259 s->ioredtbl[index] |= (uint64_t)val << 32;
260 } else {
261 s->ioredtbl[index] &= ~0xffffffffULL;
262 s->ioredtbl[index] |= val;
264 ioapic_service(s);
267 break;
271 static int ioapic_post_load(void *opaque, int version_id)
273 IOAPICState *s = opaque;
275 if (version_id == 1) {
276 /* set sane value */
277 s->irr = 0;
279 return 0;
282 static const VMStateDescription vmstate_ioapic = {
283 .name = "ioapic",
284 .version_id = 3,
285 .post_load = ioapic_post_load,
286 .minimum_version_id = 1,
287 .minimum_version_id_old = 1,
288 .fields = (VMStateField[]) {
289 VMSTATE_UINT8(id, IOAPICState),
290 VMSTATE_UINT8(ioregsel, IOAPICState),
291 VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
292 VMSTATE_UINT32_V(irr, IOAPICState, 2),
293 VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
294 VMSTATE_END_OF_LIST()
298 static void ioapic_reset(DeviceState *d)
300 IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
301 int i;
303 s->id = 0;
304 s->ioregsel = 0;
305 s->irr = 0;
306 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
307 s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
311 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
312 ioapic_mem_readl,
313 ioapic_mem_readl,
314 ioapic_mem_readl,
317 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
318 ioapic_mem_writel,
319 ioapic_mem_writel,
320 ioapic_mem_writel,
323 static int ioapic_init1(SysBusDevice *dev)
325 IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
326 int io_memory;
327 static int ioapic_no;
329 if (ioapic_no >= MAX_IOAPICS) {
330 return -1;
333 io_memory = cpu_register_io_memory(ioapic_mem_read,
334 ioapic_mem_write, s,
335 DEVICE_NATIVE_ENDIAN);
336 sysbus_init_mmio(dev, 0x1000, io_memory);
338 qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
340 ioapics[ioapic_no++] = s;
342 return 0;
345 static SysBusDeviceInfo ioapic_info = {
346 .init = ioapic_init1,
347 .qdev.name = "ioapic",
348 .qdev.size = sizeof(IOAPICState),
349 .qdev.vmsd = &vmstate_ioapic,
350 .qdev.reset = ioapic_reset,
351 .qdev.no_user = 1,
354 static void ioapic_register_devices(void)
356 sysbus_register_withprop(&ioapic_info);
359 device_init(ioapic_register_devices)