hw/arm_sysctl.c

   1 /*
   2  * Status and system control registers for ARM RealView/Versatile boards.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "qemu-timer.h"
  12 #include "sysbus.h"
  13 #include "primecell.h"
  14 #include "sysemu.h"
  15
  16 #define LOCK_VALUE 0xa05f
  17
  18 typedef struct {
  19     SysBusDevice busdev;
  20     uint32_t sys_id;
  21     uint32_t leds;
  22     uint16_t lockval;
  23     uint32_t cfgdata1;
  24     uint32_t cfgdata2;
  25     uint32_t flags;
  26     uint32_t nvflags;
  27     uint32_t resetlevel;
  28     uint32_t proc_id;
  29     uint32_t sys_mci;
  30     uint32_t sys_cfgdata;
  31     uint32_t sys_cfgctrl;
  32     uint32_t sys_cfgstat;
  33 } arm_sysctl_state;
  34
  35 static const VMStateDescription vmstate_arm_sysctl = {
  36     .name = "realview_sysctl",
  37     .version_id = 2,
  38     .minimum_version_id = 1,
  39     .fields = (VMStateField[]) {
  40         VMSTATE_UINT32(leds, arm_sysctl_state),
  41         VMSTATE_UINT16(lockval, arm_sysctl_state),
  42         VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
  43         VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
  44         VMSTATE_UINT32(flags, arm_sysctl_state),
  45         VMSTATE_UINT32(nvflags, arm_sysctl_state),
  46         VMSTATE_UINT32(resetlevel, arm_sysctl_state),
  47         VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
  48         VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
  49         VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
  50         VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
  51         VMSTATE_END_OF_LIST()
  52     }
  53 };
  54
  55 /* The PB926 actually uses a different format for
  56  * its SYS_ID register. Fortunately the bits which are
  57  * board type on later boards are distinct.
  58  */
  59 #define BOARD_ID_PB926 0x100
  60 #define BOARD_ID_EB 0x140
  61 #define BOARD_ID_PBA8 0x178
  62 #define BOARD_ID_PBX 0x182
  63 #define BOARD_ID_VEXPRESS 0x190
  64
  65 static int board_id(arm_sysctl_state *s)
  66 {
  67     /* Extract the board ID field from the SYS_ID register value */
  68     return (s->sys_id >> 16) & 0xfff;
  69 }
  70
  71 static void arm_sysctl_reset(DeviceState *d)
  72 {
  73     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
  74
  75     s->leds = 0;
  76     s->lockval = 0;
  77     s->cfgdata1 = 0;
  78     s->cfgdata2 = 0;
  79     s->flags = 0;
  80     s->resetlevel = 0;
  81 }
  82
  83 static uint32_t arm_sysctl_read(void *opaque, target_phys_addr_t offset)
  84 {
  85     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
  86
  87     switch (offset) {
  88     case 0x00: /* ID */
  89         return s->sys_id;
  90     case 0x04: /* SW */
  91         /* General purpose hardware switches.
  92            We don't have a useful way of exposing these to the user.  */
  93         return 0;
  94     case 0x08: /* LED */
  95         return s->leds;
  96     case 0x20: /* LOCK */
  97         return s->lockval;
  98     case 0x0c: /* OSC0 */
  99     case 0x10: /* OSC1 */
 100     case 0x14: /* OSC2 */
 101     case 0x18: /* OSC3 */
 102     case 0x1c: /* OSC4 */
 103     case 0x24: /* 100HZ */
 104         /* ??? Implement these.  */
 105         return 0;
 106     case 0x28: /* CFGDATA1 */
 107         return s->cfgdata1;
 108     case 0x2c: /* CFGDATA2 */
 109         return s->cfgdata2;
 110     case 0x30: /* FLAGS */
 111         return s->flags;
 112     case 0x38: /* NVFLAGS */
 113         return s->nvflags;
 114     case 0x40: /* RESETCTL */
 115         if (board_id(s) == BOARD_ID_VEXPRESS) {
 116             /* reserved: RAZ/WI */
 117             return 0;
 118         }
 119         return s->resetlevel;
 120     case 0x44: /* PCICTL */
 121         return 1;
 122     case 0x48: /* MCI */
 123         return s->sys_mci;
 124     case 0x4c: /* FLASH */
 125         return 0;
 126     case 0x50: /* CLCD */
 127         return 0x1000;
 128     case 0x54: /* CLCDSER */
 129         return 0;
 130     case 0x58: /* BOOTCS */
 131         return 0;
 132     case 0x5c: /* 24MHz */
 133         return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
 134     case 0x60: /* MISC */
 135         return 0;
 136     case 0x84: /* PROCID0 */
 137         return s->proc_id;
 138     case 0x88: /* PROCID1 */
 139         return 0xff000000;
 140     case 0x64: /* DMAPSR0 */
 141     case 0x68: /* DMAPSR1 */
 142     case 0x6c: /* DMAPSR2 */
 143     case 0x70: /* IOSEL */
 144     case 0x74: /* PLDCTL */
 145     case 0x80: /* BUSID */
 146     case 0x8c: /* OSCRESET0 */
 147     case 0x90: /* OSCRESET1 */
 148     case 0x94: /* OSCRESET2 */
 149     case 0x98: /* OSCRESET3 */
 150     case 0x9c: /* OSCRESET4 */
 151     case 0xc0: /* SYS_TEST_OSC0 */
 152     case 0xc4: /* SYS_TEST_OSC1 */
 153     case 0xc8: /* SYS_TEST_OSC2 */
 154     case 0xcc: /* SYS_TEST_OSC3 */
 155     case 0xd0: /* SYS_TEST_OSC4 */
 156         return 0;
 157     case 0xa0: /* SYS_CFGDATA */
 158         if (board_id(s) != BOARD_ID_VEXPRESS) {
 159             goto bad_reg;
 160         }
 161         return s->sys_cfgdata;
 162     case 0xa4: /* SYS_CFGCTRL */
 163         if (board_id(s) != BOARD_ID_VEXPRESS) {
 164             goto bad_reg;
 165         }
 166         return s->sys_cfgctrl;
 167     case 0xa8: /* SYS_CFGSTAT */
 168         if (board_id(s) != BOARD_ID_VEXPRESS) {
 169             goto bad_reg;
 170         }
 171         return s->sys_cfgstat;
 172     default:
 173     bad_reg:
 174         printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset);
 175         return 0;
 176     }
 177 }
 178
 179 static void arm_sysctl_write(void *opaque, target_phys_addr_t offset,
 180                           uint32_t val)
 181 {
 182     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 183
 184     switch (offset) {
 185     case 0x08: /* LED */
 186         s->leds = val;
 187     case 0x0c: /* OSC0 */
 188     case 0x10: /* OSC1 */
 189     case 0x14: /* OSC2 */
 190     case 0x18: /* OSC3 */
 191     case 0x1c: /* OSC4 */
 192         /* ??? */
 193         break;
 194     case 0x20: /* LOCK */
 195         if (val == LOCK_VALUE)
 196             s->lockval = val;
 197         else
 198             s->lockval = val & 0x7fff;
 199         break;
 200     case 0x28: /* CFGDATA1 */
 201         /* ??? Need to implement this.  */
 202         s->cfgdata1 = val;
 203         break;
 204     case 0x2c: /* CFGDATA2 */
 205         /* ??? Need to implement this.  */
 206         s->cfgdata2 = val;
 207         break;
 208     case 0x30: /* FLAGSSET */
 209         s->flags |= val;
 210         break;
 211     case 0x34: /* FLAGSCLR */
 212         s->flags &= ~val;
 213         break;
 214     case 0x38: /* NVFLAGSSET */
 215         s->nvflags |= val;
 216         break;
 217     case 0x3c: /* NVFLAGSCLR */
 218         s->nvflags &= ~val;
 219         break;
 220     case 0x40: /* RESETCTL */
 221         if (board_id(s) == BOARD_ID_VEXPRESS) {
 222             /* reserved: RAZ/WI */
 223             break;
 224         }
 225         if (s->lockval == LOCK_VALUE) {
 226             s->resetlevel = val;
 227             if (val & 0x100)
 228                 qemu_system_reset_request ();
 229         }
 230         break;
 231     case 0x44: /* PCICTL */
 232         /* nothing to do.  */
 233         break;
 234     case 0x4c: /* FLASH */
 235     case 0x50: /* CLCD */
 236     case 0x54: /* CLCDSER */
 237     case 0x64: /* DMAPSR0 */
 238     case 0x68: /* DMAPSR1 */
 239     case 0x6c: /* DMAPSR2 */
 240     case 0x70: /* IOSEL */
 241     case 0x74: /* PLDCTL */
 242     case 0x80: /* BUSID */
 243     case 0x84: /* PROCID0 */
 244     case 0x88: /* PROCID1 */
 245     case 0x8c: /* OSCRESET0 */
 246     case 0x90: /* OSCRESET1 */
 247     case 0x94: /* OSCRESET2 */
 248     case 0x98: /* OSCRESET3 */
 249     case 0x9c: /* OSCRESET4 */
 250         break;
 251     case 0xa0: /* SYS_CFGDATA */
 252         if (board_id(s) != BOARD_ID_VEXPRESS) {
 253             goto bad_reg;
 254         }
 255         s->sys_cfgdata = val;
 256         return;
 257     case 0xa4: /* SYS_CFGCTRL */
 258         if (board_id(s) != BOARD_ID_VEXPRESS) {
 259             goto bad_reg;
 260         }
 261         s->sys_cfgctrl = val & ~(3 << 18);
 262         s->sys_cfgstat = 1;            /* complete */
 263         switch (s->sys_cfgctrl) {
 264         case 0xc0800000:            /* SYS_CFG_SHUTDOWN to motherboard */
 265             qemu_system_shutdown_request();
 266             break;
 267         case 0xc0900000:            /* SYS_CFG_REBOOT to motherboard */
 268             qemu_system_reset_request();
 269             break;
 270         default:
 271             s->sys_cfgstat |= 2;        /* error */
 272         }
 273         return;
 274     case 0xa8: /* SYS_CFGSTAT */
 275         if (board_id(s) != BOARD_ID_VEXPRESS) {
 276             goto bad_reg;
 277         }
 278         s->sys_cfgstat = val & 3;
 279         return;
 280     default:
 281     bad_reg:
 282         printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset);
 283         return;
 284     }
 285 }
 286
 287 static CPUReadMemoryFunc * const arm_sysctl_readfn[] = {
 288    arm_sysctl_read,
 289    arm_sysctl_read,
 290    arm_sysctl_read
 291 };
 292
 293 static CPUWriteMemoryFunc * const arm_sysctl_writefn[] = {
 294    arm_sysctl_write,
 295    arm_sysctl_write,
 296    arm_sysctl_write
 297 };
 298
 299 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
 300 {
 301     arm_sysctl_state *s = (arm_sysctl_state *)opaque;
 302     switch (line) {
 303     case ARM_SYSCTL_GPIO_MMC_WPROT:
 304     {
 305         /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
 306          * for all later boards it is bit 1.
 307          */
 308         int bit = 2;
 309         if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
 310             bit = 4;
 311         }
 312         s->sys_mci &= ~bit;
 313         if (level) {
 314             s->sys_mci |= bit;
 315         }
 316         break;
 317     }
 318     case ARM_SYSCTL_GPIO_MMC_CARDIN:
 319         s->sys_mci &= ~1;
 320         if (level) {
 321             s->sys_mci |= 1;
 322         }
 323         break;
 324     }
 325 }
 326
 327 static int arm_sysctl_init1(SysBusDevice *dev)
 328 {
 329     arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
 330     int iomemtype;
 331
 332     iomemtype = cpu_register_io_memory(arm_sysctl_readfn,
 333                                        arm_sysctl_writefn, s,
 334                                        DEVICE_NATIVE_ENDIAN);
 335     sysbus_init_mmio(dev, 0x1000, iomemtype);
 336     qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
 337     /* ??? Save/restore.  */
 338     return 0;
 339 }
 340
 341 /* Legacy helper function.  */
 342 void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
 343 {
 344     DeviceState *dev;
 345
 346     dev = qdev_create(NULL, "realview_sysctl");
 347     qdev_prop_set_uint32(dev, "sys_id", sys_id);
 348     qdev_init_nofail(dev);
 349     qdev_prop_set_uint32(dev, "proc_id", proc_id);
 350     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
 351 }
 352
 353 static SysBusDeviceInfo arm_sysctl_info = {
 354     .init = arm_sysctl_init1,
 355     .qdev.name  = "realview_sysctl",
 356     .qdev.size  = sizeof(arm_sysctl_state),
 357     .qdev.vmsd = &vmstate_arm_sysctl,
 358     .qdev.reset = arm_sysctl_reset,
 359     .qdev.props = (Property[]) {
 360         DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
 361         DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
 362         DEFINE_PROP_END_OF_LIST(),
 363     }
 364 };
 365
 366 static void arm_sysctl_register_devices(void)
 367 {
 368     sysbus_register_withprop(&arm_sysctl_info);
 369 }
 370
 371 device_init(arm_sysctl_register_devices)