?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
migration: use closesocket, not close
[qemu/opensuse.git] / hw / e1000.c
blobcb7e7e83661767a1a34bbb1f65601abbda7ffd61
1 /*
2 * QEMU e1000 emulation
3 *
4 * Software developer's manual:
5 * http://download.intel.com/design/network/manuals/8254x_GBe_SDM.pdf
6 *
7 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
8 * Copyright (c) 2008 Qumranet
9 * Based on work done by:
10 * Copyright (c) 2007 Dan Aloni
11 * Copyright (c) 2004 Antony T Curtis
12 *
13 * This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU Lesser General Public
15 * License as published by the Free Software Foundation; either
16 * version 2 of the License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * Lesser General Public License for more details.
22 *
23 * You should have received a copy of the GNU Lesser General Public
24 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
25 */
26
27
28 #include "hw.h"
29 #include "pci.h"
30 #include "net.h"
31 #include "net/checksum.h"
32 #include "loader.h"
33 #include "sysemu.h"
34 #include "dma.h"
35
36 #include "e1000_hw.h"
37
38 #define E1000_DEBUG
39
40 #ifdef E1000_DEBUG
41 enum {
42 DEBUG_GENERAL, DEBUG_IO, DEBUG_MMIO, DEBUG_INTERRUPT,
43 DEBUG_RX, DEBUG_TX, DEBUG_MDIC, DEBUG_EEPROM,
44 DEBUG_UNKNOWN, DEBUG_TXSUM, DEBUG_TXERR, DEBUG_RXERR,
45 DEBUG_RXFILTER, DEBUG_PHY, DEBUG_NOTYET,
46 };
47 #define DBGBIT(x) (1<<DEBUG_##x)
48 static int debugflags = DBGBIT(TXERR) | DBGBIT(GENERAL);
49
50 #define DBGOUT(what, fmt, ...) do { \
51 if (debugflags & DBGBIT(what)) \
52 fprintf(stderr, "e1000: " fmt, ## __VA_ARGS__); \
53 } while (0)
54 #else
55 #define DBGOUT(what, fmt, ...) do {} while (0)
56 #endif
57
58 #define IOPORT_SIZE 0x40
59 #define PNPMMIO_SIZE 0x20000
60 #define MIN_BUF_SIZE 60 /* Min. octets in an ethernet frame sans FCS */
61
62 /*
63 * HW models:
64 * E1000_DEV_ID_82540EM works with Windows and Linux
65 * E1000_DEV_ID_82573L OK with windoze and Linux 2.6.22,
66 * appears to perform better than 82540EM, but breaks with Linux 2.6.18
67 * E1000_DEV_ID_82544GC_COPPER appears to work; not well tested
68 * Others never tested
69 */
70 enum { E1000_DEVID = E1000_DEV_ID_82540EM };
71
72 /*
73 * May need to specify additional MAC-to-PHY entries --
74 * Intel's Windows driver refuses to initialize unless they match
75 */
76 enum {
77 PHY_ID2_INIT = E1000_DEVID == E1000_DEV_ID_82573L ? 0xcc2 :
78 E1000_DEVID == E1000_DEV_ID_82544GC_COPPER ? 0xc30 :
79 /* default to E1000_DEV_ID_82540EM */ 0xc20
80 };
81
82 typedef struct E1000State_st {
83 PCIDevice dev;
84 NICState *nic;
85 NICConf conf;
86 MemoryRegion mmio;
87 MemoryRegion io;
88
89 uint32_t mac_reg[0x8000];
90 uint16_t phy_reg[0x20];
91 uint16_t eeprom_data[64];
92
93 uint32_t rxbuf_size;
94 uint32_t rxbuf_min_shift;
95 struct e1000_tx {
96 unsigned char header[256];
97 unsigned char vlan_header[4];
98 /* Fields vlan and data must not be reordered or separated. */
99 unsigned char vlan[4];
100 unsigned char data[0x10000];
101 uint16_t size;
102 unsigned char sum_needed;
103 unsigned char vlan_needed;
104 uint8_t ipcss;
105 uint8_t ipcso;
106 uint16_t ipcse;
107 uint8_t tucss;
108 uint8_t tucso;
109 uint16_t tucse;
110 uint8_t hdr_len;
111 uint16_t mss;
112 uint32_t paylen;
113 uint16_t tso_frames;
114 char tse;
115 int8_t ip;
116 int8_t tcp;
117 char cptse; // current packet tse bit
118 } tx;
119
120 struct {
121 uint32_t val_in; // shifted in from guest driver
122 uint16_t bitnum_in;
123 uint16_t bitnum_out;
124 uint16_t reading;
125 uint32_t old_eecd;
126 } eecd_state;
127
128 QEMUTimer *autoneg_timer;
129 } E1000State;
130
131 #define defreg(x) x = (E1000_##x>>2)
132 enum {
133 defreg(CTRL), defreg(EECD), defreg(EERD), defreg(GPRC),
134 defreg(GPTC), defreg(ICR), defreg(ICS), defreg(IMC),
135 defreg(IMS), defreg(LEDCTL), defreg(MANC), defreg(MDIC),
136 defreg(MPC), defreg(PBA), defreg(RCTL), defreg(RDBAH),
137 defreg(RDBAL), defreg(RDH), defreg(RDLEN), defreg(RDT),
138 defreg(STATUS), defreg(SWSM), defreg(TCTL), defreg(TDBAH),
139 defreg(TDBAL), defreg(TDH), defreg(TDLEN), defreg(TDT),
140 defreg(TORH), defreg(TORL), defreg(TOTH), defreg(TOTL),
141 defreg(TPR), defreg(TPT), defreg(TXDCTL), defreg(WUFC),
142 defreg(RA), defreg(MTA), defreg(CRCERRS),defreg(VFTA),
143 defreg(VET),
144 };
145
146 static void
147 e1000_link_down(E1000State *s)
148 {
149 s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
150 s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
151 }
152
153 static void
154 e1000_link_up(E1000State *s)
155 {
156 s->mac_reg[STATUS] |= E1000_STATUS_LU;
157 s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
158 }
159
160 static void
161 set_phy_ctrl(E1000State *s, int index, uint16_t val)
162 {
163 if ((val & MII_CR_AUTO_NEG_EN) && (val & MII_CR_RESTART_AUTO_NEG)) {
164 s->nic->nc.link_down = true;
165 e1000_link_down(s);
166 s->phy_reg[PHY_STATUS] &= ~MII_SR_AUTONEG_COMPLETE;
167 DBGOUT(PHY, "Start link auto negotiation\n");
168 qemu_mod_timer(s->autoneg_timer, qemu_get_clock_ms(vm_clock) + 500);
169 }
170 }
171
172 static void
173 e1000_autoneg_timer(void *opaque)
174 {
175 E1000State *s = opaque;
176 s->nic->nc.link_down = false;
177 e1000_link_up(s);
178 s->phy_reg[PHY_STATUS] |= MII_SR_AUTONEG_COMPLETE;
179 DBGOUT(PHY, "Auto negotiation is completed\n");
180 }
181
182 static void (*phyreg_writeops[])(E1000State *, int, uint16_t) = {
183 [PHY_CTRL] = set_phy_ctrl,
184 };
185
186 enum { NPHYWRITEOPS = ARRAY_SIZE(phyreg_writeops) };
187
188 enum { PHY_R = 1, PHY_W = 2, PHY_RW = PHY_R | PHY_W };
189 static const char phy_regcap[0x20] = {
190 [PHY_STATUS] = PHY_R, [M88E1000_EXT_PHY_SPEC_CTRL] = PHY_RW,
191 [PHY_ID1] = PHY_R, [M88E1000_PHY_SPEC_CTRL] = PHY_RW,
192 [PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
193 [PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
194 [PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
195 [PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
196 };
197
198 static const uint16_t phy_reg_init[] = {
199 [PHY_CTRL] = 0x1140,
200 [PHY_STATUS] = 0x794d, /* link initially up with not completed autoneg */
201 [PHY_ID1] = 0x141, [PHY_ID2] = PHY_ID2_INIT,
202 [PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
203 [M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
204 [PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
205 [M88E1000_PHY_SPEC_STATUS] = 0xac00,
206 };
207
208 static const uint32_t mac_reg_init[] = {
209 [PBA] = 0x00100030,
210 [LEDCTL] = 0x602,
211 [CTRL] = E1000_CTRL_SWDPIN2 | E1000_CTRL_SWDPIN0 |
212 E1000_CTRL_SPD_1000 | E1000_CTRL_SLU,
213 [STATUS] = 0x80000000 | E1000_STATUS_GIO_MASTER_ENABLE |
214 E1000_STATUS_ASDV | E1000_STATUS_MTXCKOK |
215 E1000_STATUS_SPEED_1000 | E1000_STATUS_FD |
216 E1000_STATUS_LU,
217 [MANC] = E1000_MANC_EN_MNG2HOST | E1000_MANC_RCV_TCO_EN |
218 E1000_MANC_ARP_EN | E1000_MANC_0298_EN |
219 E1000_MANC_RMCP_EN,
220 };
221
222 static void
223 set_interrupt_cause(E1000State *s, int index, uint32_t val)
224 {
225 if (val && (E1000_DEVID >= E1000_DEV_ID_82547EI_MOBILE)) {
226 /* Only for 8257x */
227 val |= E1000_ICR_INT_ASSERTED;
228 }
229 s->mac_reg[ICR] = val;
230 s->mac_reg[ICS] = val;
231 qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
232 }
233
234 static void
235 set_ics(E1000State *s, int index, uint32_t val)
236 {
237 DBGOUT(INTERRUPT, "set_ics %x, ICR %x, IMR %x\n", val, s->mac_reg[ICR],
238 s->mac_reg[IMS]);
239 set_interrupt_cause(s, 0, val | s->mac_reg[ICR]);
240 }
241
242 static int
243 rxbufsize(uint32_t v)
244 {
245 v &= E1000_RCTL_BSEX | E1000_RCTL_SZ_16384 | E1000_RCTL_SZ_8192 |
246 E1000_RCTL_SZ_4096 | E1000_RCTL_SZ_2048 | E1000_RCTL_SZ_1024 |
247 E1000_RCTL_SZ_512 | E1000_RCTL_SZ_256;
248 switch (v) {
249 case E1000_RCTL_BSEX | E1000_RCTL_SZ_16384:
250 return 16384;
251 case E1000_RCTL_BSEX | E1000_RCTL_SZ_8192:
252 return 8192;
253 case E1000_RCTL_BSEX | E1000_RCTL_SZ_4096:
254 return 4096;
255 case E1000_RCTL_SZ_1024:
256 return 1024;
257 case E1000_RCTL_SZ_512:
258 return 512;
259 case E1000_RCTL_SZ_256:
260 return 256;
261 }
262 return 2048;
263 }
264
265 static void e1000_reset(void *opaque)
266 {
267 E1000State *d = opaque;
268 uint8_t *macaddr = d->conf.macaddr.a;
269 int i;
270
271 qemu_del_timer(d->autoneg_timer);
272 memset(d->phy_reg, 0, sizeof d->phy_reg);
273 memmove(d->phy_reg, phy_reg_init, sizeof phy_reg_init);
274 memset(d->mac_reg, 0, sizeof d->mac_reg);
275 memmove(d->mac_reg, mac_reg_init, sizeof mac_reg_init);
276 d->rxbuf_min_shift = 1;
277 memset(&d->tx, 0, sizeof d->tx);
278
279 if (d->nic->nc.link_down) {
280 e1000_link_down(d);
281 }
282
283 /* Some guests expect pre-initialized RAH/RAL (AddrValid flag + MACaddr) */
284 d->mac_reg[RA] = 0;
285 d->mac_reg[RA + 1] = E1000_RAH_AV;
286 for (i = 0; i < 4; i++) {
287 d->mac_reg[RA] |= macaddr[i] << (8 * i);
288 d->mac_reg[RA + 1] |= (i < 2) ? macaddr[i + 4] << (8 * i) : 0;
289 }
290 }
291
292 static void
293 set_ctrl(E1000State *s, int index, uint32_t val)
294 {
295 /* RST is self clearing */
296 s->mac_reg[CTRL] = val & ~E1000_CTRL_RST;
297 }
298
299 static void
300 set_rx_control(E1000State *s, int index, uint32_t val)
301 {
302 s->mac_reg[RCTL] = val;
303 s->rxbuf_size = rxbufsize(val);
304 s->rxbuf_min_shift = ((val / E1000_RCTL_RDMTS_QUAT) & 3) + 1;
305 DBGOUT(RX, "RCTL: %d, mac_reg[RCTL] = 0x%x\n", s->mac_reg[RDT],
306 s->mac_reg[RCTL]);
307 qemu_flush_queued_packets(&s->nic->nc);
308 }
309
310 static void
311 set_mdic(E1000State *s, int index, uint32_t val)
312 {
313 uint32_t data = val & E1000_MDIC_DATA_MASK;
314 uint32_t addr = ((val & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
315
316 if ((val & E1000_MDIC_PHY_MASK) >> E1000_MDIC_PHY_SHIFT != 1) // phy #
317 val = s->mac_reg[MDIC] | E1000_MDIC_ERROR;
318 else if (val & E1000_MDIC_OP_READ) {
319 DBGOUT(MDIC, "MDIC read reg 0x%x\n", addr);
320 if (!(phy_regcap[addr] & PHY_R)) {
321 DBGOUT(MDIC, "MDIC read reg %x unhandled\n", addr);
322 val |= E1000_MDIC_ERROR;
323 } else
324 val = (val ^ data) | s->phy_reg[addr];
325 } else if (val & E1000_MDIC_OP_WRITE) {
326 DBGOUT(MDIC, "MDIC write reg 0x%x, value 0x%x\n", addr, data);
327 if (!(phy_regcap[addr] & PHY_W)) {
328 DBGOUT(MDIC, "MDIC write reg %x unhandled\n", addr);
329 val |= E1000_MDIC_ERROR;
330 } else {
331 if (addr < NPHYWRITEOPS && phyreg_writeops[addr]) {
332 phyreg_writeops[addr](s, index, data);
333 }
334 s->phy_reg[addr] = data;
335 }
336 }
337 s->mac_reg[MDIC] = val | E1000_MDIC_READY;
338
339 if (val & E1000_MDIC_INT_EN) {
340 set_ics(s, 0, E1000_ICR_MDAC);
341 }
342 }
343
344 static uint32_t
345 get_eecd(E1000State *s, int index)
346 {
347 uint32_t ret = E1000_EECD_PRES|E1000_EECD_GNT | s->eecd_state.old_eecd;
348
349 DBGOUT(EEPROM, "reading eeprom bit %d (reading %d)\n",
350 s->eecd_state.bitnum_out, s->eecd_state.reading);
351 if (!s->eecd_state.reading ||
352 ((s->eeprom_data[(s->eecd_state.bitnum_out >> 4) & 0x3f] >>
353 ((s->eecd_state.bitnum_out & 0xf) ^ 0xf))) & 1)
354 ret |= E1000_EECD_DO;
355 return ret;
356 }
357
358 static void
359 set_eecd(E1000State *s, int index, uint32_t val)
360 {
361 uint32_t oldval = s->eecd_state.old_eecd;
362
363 s->eecd_state.old_eecd = val & (E1000_EECD_SK | E1000_EECD_CS |
364 E1000_EECD_DI|E1000_EECD_FWE_MASK|E1000_EECD_REQ);
365 if (!(E1000_EECD_CS & val)) // CS inactive; nothing to do
366 return;
367 if (E1000_EECD_CS & (val ^ oldval)) { // CS rise edge; reset state
368 s->eecd_state.val_in = 0;
369 s->eecd_state.bitnum_in = 0;
370 s->eecd_state.bitnum_out = 0;
371 s->eecd_state.reading = 0;
372 }
373 if (!(E1000_EECD_SK & (val ^ oldval))) // no clock edge
374 return;
375 if (!(E1000_EECD_SK & val)) { // falling edge
376 s->eecd_state.bitnum_out++;
377 return;
378 }
379 s->eecd_state.val_in <<= 1;
380 if (val & E1000_EECD_DI)
381 s->eecd_state.val_in |= 1;
382 if (++s->eecd_state.bitnum_in == 9 && !s->eecd_state.reading) {
383 s->eecd_state.bitnum_out = ((s->eecd_state.val_in & 0x3f)<<4)-1;
384 s->eecd_state.reading = (((s->eecd_state.val_in >> 6) & 7) ==
385 EEPROM_READ_OPCODE_MICROWIRE);
386 }
387 DBGOUT(EEPROM, "eeprom bitnum in %d out %d, reading %d\n",
388 s->eecd_state.bitnum_in, s->eecd_state.bitnum_out,
389 s->eecd_state.reading);
390 }
391
392 static uint32_t
393 flash_eerd_read(E1000State *s, int x)
394 {
395 unsigned int index, r = s->mac_reg[EERD] & ~E1000_EEPROM_RW_REG_START;
396
397 if ((s->mac_reg[EERD] & E1000_EEPROM_RW_REG_START) == 0)
398 return (s->mac_reg[EERD]);
399
400 if ((index = r >> E1000_EEPROM_RW_ADDR_SHIFT) > EEPROM_CHECKSUM_REG)
401 return (E1000_EEPROM_RW_REG_DONE | r);
402
403 return ((s->eeprom_data[index] << E1000_EEPROM_RW_REG_DATA) |
404 E1000_EEPROM_RW_REG_DONE | r);
405 }
406
407 static void
408 putsum(uint8_t *data, uint32_t n, uint32_t sloc, uint32_t css, uint32_t cse)
409 {
410 uint32_t sum;
411
412 if (cse && cse < n)
413 n = cse + 1;
414 if (sloc < n-1) {
415 sum = net_checksum_add(n-css, data+css);
416 cpu_to_be16wu((uint16_t *)(data + sloc),
417 net_checksum_finish(sum));
418 }
419 }
420
421 static inline int
422 vlan_enabled(E1000State *s)
423 {
424 return ((s->mac_reg[CTRL] & E1000_CTRL_VME) != 0);
425 }
426
427 static inline int
428 vlan_rx_filter_enabled(E1000State *s)
429 {
430 return ((s->mac_reg[RCTL] & E1000_RCTL_VFE) != 0);
431 }
432
433 static inline int
434 is_vlan_packet(E1000State *s, const uint8_t *buf)
435 {
436 return (be16_to_cpup((uint16_t *)(buf + 12)) ==
437 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
438 }
439
440 static inline int
441 is_vlan_txd(uint32_t txd_lower)
442 {
443 return ((txd_lower & E1000_TXD_CMD_VLE) != 0);
444 }
445
446 /* FCS aka Ethernet CRC-32. We don't get it from backends and can't
447 * fill it in, just pad descriptor length by 4 bytes unless guest
448 * told us to strip it off the packet. */
449 static inline int
450 fcs_len(E1000State *s)
451 {
452 return (s->mac_reg[RCTL] & E1000_RCTL_SECRC) ? 0 : 4;
453 }
454
455 static void
456 e1000_send_packet(E1000State *s, const uint8_t *buf, int size)
457 {
458 if (s->phy_reg[PHY_CTRL] & MII_CR_LOOPBACK) {
459 s->nic->nc.info->receive(&s->nic->nc, buf, size);
460 } else {
461 qemu_send_packet(&s->nic->nc, buf, size);
462 }
463 }
464
465 static void
466 xmit_seg(E1000State *s)
467 {
468 uint16_t len, *sp;
469 unsigned int frames = s->tx.tso_frames, css, sofar, n;
470 struct e1000_tx *tp = &s->tx;
471
472 if (tp->tse && tp->cptse) {
473 css = tp->ipcss;
474 DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
475 frames, tp->size, css);
476 if (tp->ip) { // IPv4
477 cpu_to_be16wu((uint16_t *)(tp->data+css+2),
478 tp->size - css);
479 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
480 be16_to_cpup((uint16_t *)(tp->data+css+4))+frames);
481 } else // IPv6
482 cpu_to_be16wu((uint16_t *)(tp->data+css+4),
483 tp->size - css);
484 css = tp->tucss;
485 len = tp->size - css;
486 DBGOUT(TXSUM, "tcp %d tucss %d len %d\n", tp->tcp, css, len);
487 if (tp->tcp) {
488 sofar = frames * tp->mss;
489 cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
490 be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
491 if (tp->paylen - sofar > tp->mss)
492 tp->data[css + 13] &= ~9; // PSH, FIN
493 } else // UDP
494 cpu_to_be16wu((uint16_t *)(tp->data+css+4), len);
495 if (tp->sum_needed & E1000_TXD_POPTS_TXSM) {
496 unsigned int phsum;
497 // add pseudo-header length before checksum calculation
498 sp = (uint16_t *)(tp->data + tp->tucso);
499 phsum = be16_to_cpup(sp) + len;
500 phsum = (phsum >> 16) + (phsum & 0xffff);
501 cpu_to_be16wu(sp, phsum);
502 }
503 tp->tso_frames++;
504 }
505
506 if (tp->sum_needed & E1000_TXD_POPTS_TXSM)
507 putsum(tp->data, tp->size, tp->tucso, tp->tucss, tp->tucse);
508 if (tp->sum_needed & E1000_TXD_POPTS_IXSM)
509 putsum(tp->data, tp->size, tp->ipcso, tp->ipcss, tp->ipcse);
510 if (tp->vlan_needed) {
511 memmove(tp->vlan, tp->data, 4);
512 memmove(tp->data, tp->data + 4, 8);
513 memcpy(tp->data + 8, tp->vlan_header, 4);
514 e1000_send_packet(s, tp->vlan, tp->size + 4);
515 } else
516 e1000_send_packet(s, tp->data, tp->size);
517 s->mac_reg[TPT]++;
518 s->mac_reg[GPTC]++;
519 n = s->mac_reg[TOTL];
520 if ((s->mac_reg[TOTL] += s->tx.size) < n)
521 s->mac_reg[TOTH]++;
522 }
523
524 static void
525 process_tx_desc(E1000State *s, struct e1000_tx_desc *dp)
526 {
527 uint32_t txd_lower = le32_to_cpu(dp->lower.data);
528 uint32_t dtype = txd_lower & (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D);
529 unsigned int split_size = txd_lower & 0xffff, bytes, sz, op;
530 unsigned int msh = 0xfffff, hdr = 0;
531 uint64_t addr;
532 struct e1000_context_desc *xp = (struct e1000_context_desc *)dp;
533 struct e1000_tx *tp = &s->tx;
534
535 if (dtype == E1000_TXD_CMD_DEXT) { // context descriptor
536 op = le32_to_cpu(xp->cmd_and_length);
537 tp->ipcss = xp->lower_setup.ip_fields.ipcss;
538 tp->ipcso = xp->lower_setup.ip_fields.ipcso;
539 tp->ipcse = le16_to_cpu(xp->lower_setup.ip_fields.ipcse);
540 tp->tucss = xp->upper_setup.tcp_fields.tucss;
541 tp->tucso = xp->upper_setup.tcp_fields.tucso;
542 tp->tucse = le16_to_cpu(xp->upper_setup.tcp_fields.tucse);
543 tp->paylen = op & 0xfffff;
544 tp->hdr_len = xp->tcp_seg_setup.fields.hdr_len;
545 tp->mss = le16_to_cpu(xp->tcp_seg_setup.fields.mss);
546 tp->ip = (op & E1000_TXD_CMD_IP) ? 1 : 0;
547 tp->tcp = (op & E1000_TXD_CMD_TCP) ? 1 : 0;
548 tp->tse = (op & E1000_TXD_CMD_TSE) ? 1 : 0;
549 tp->tso_frames = 0;
550 if (tp->tucso == 0) { // this is probably wrong
551 DBGOUT(TXSUM, "TCP/UDP: cso 0!\n");
552 tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
553 }
554 return;
555 } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
556 // data descriptor
557 if (tp->size == 0) {
558 tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
559 }
560 tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
561 } else {
562 // legacy descriptor
563 tp->cptse = 0;
564 }
565
566 if (vlan_enabled(s) && is_vlan_txd(txd_lower) &&
567 (tp->cptse || txd_lower & E1000_TXD_CMD_EOP)) {
568 tp->vlan_needed = 1;
569 cpu_to_be16wu((uint16_t *)(tp->vlan_header),
570 le16_to_cpup((uint16_t *)(s->mac_reg + VET)));
571 cpu_to_be16wu((uint16_t *)(tp->vlan_header + 2),
572 le16_to_cpu(dp->upper.fields.special));
573 }
574
575 addr = le64_to_cpu(dp->buffer_addr);
576 if (tp->tse && tp->cptse) {
577 hdr = tp->hdr_len;
578 msh = hdr + tp->mss;
579 do {
580 bytes = split_size;
581 if (tp->size + bytes > msh)
582 bytes = msh - tp->size;
583
584 bytes = MIN(sizeof(tp->data) - tp->size, bytes);
585 pci_dma_read(&s->dev, addr, tp->data + tp->size, bytes);
586 if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
587 memmove(tp->header, tp->data, hdr);
588 tp->size = sz;
589 addr += bytes;
590 if (sz == msh) {
591 xmit_seg(s);
592 memmove(tp->data, tp->header, hdr);
593 tp->size = hdr;
594 }
595 } while (split_size -= bytes);
596 } else if (!tp->tse && tp->cptse) {
597 // context descriptor TSE is not set, while data descriptor TSE is set
598 DBGOUT(TXERR, "TCP segmentation error\n");
599 } else {
600 split_size = MIN(sizeof(tp->data) - tp->size, split_size);
601 pci_dma_read(&s->dev, addr, tp->data + tp->size, split_size);
602 tp->size += split_size;
603 }
604
605 if (!(txd_lower & E1000_TXD_CMD_EOP))
606 return;
607 if (!(tp->tse && tp->cptse && tp->size < hdr))
608 xmit_seg(s);
609 tp->tso_frames = 0;
610 tp->sum_needed = 0;
611 tp->vlan_needed = 0;
612 tp->size = 0;
613 tp->cptse = 0;
614 }
615
616 static uint32_t
617 txdesc_writeback(E1000State *s, dma_addr_t base, struct e1000_tx_desc *dp)
618 {
619 uint32_t txd_upper, txd_lower = le32_to_cpu(dp->lower.data);
620
621 if (!(txd_lower & (E1000_TXD_CMD_RS|E1000_TXD_CMD_RPS)))
622 return 0;
623 txd_upper = (le32_to_cpu(dp->upper.data) | E1000_TXD_STAT_DD) &
624 ~(E1000_TXD_STAT_EC | E1000_TXD_STAT_LC | E1000_TXD_STAT_TU);
625 dp->upper.data = cpu_to_le32(txd_upper);
626 pci_dma_write(&s->dev, base + ((char *)&dp->upper - (char *)dp),
627 &dp->upper, sizeof(dp->upper));
628 return E1000_ICR_TXDW;
629 }
630
631 static uint64_t tx_desc_base(E1000State *s)
632 {
633 uint64_t bah = s->mac_reg[TDBAH];
634 uint64_t bal = s->mac_reg[TDBAL] & ~0xf;
635
636 return (bah << 32) + bal;
637 }
638
639 static void
640 start_xmit(E1000State *s)
641 {
642 dma_addr_t base;
643 struct e1000_tx_desc desc;
644 uint32_t tdh_start = s->mac_reg[TDH], cause = E1000_ICS_TXQE;
645
646 if (!(s->mac_reg[TCTL] & E1000_TCTL_EN)) {
647 DBGOUT(TX, "tx disabled\n");
648 return;
649 }
650
651 while (s->mac_reg[TDH] != s->mac_reg[TDT]) {
652 base = tx_desc_base(s) +
653 sizeof(struct e1000_tx_desc) * s->mac_reg[TDH];
654 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
655
656 DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
657 (void *)(intptr_t)desc.buffer_addr, desc.lower.data,
658 desc.upper.data);
659
660 process_tx_desc(s, &desc);
661 cause |= txdesc_writeback(s, base, &desc);
662
663 if (++s->mac_reg[TDH] * sizeof(desc) >= s->mac_reg[TDLEN])
664 s->mac_reg[TDH] = 0;
665 /*
666 * the following could happen only if guest sw assigns
667 * bogus values to TDT/TDLEN.
668 * there's nothing too intelligent we could do about this.
669 */
670 if (s->mac_reg[TDH] == tdh_start) {
671 DBGOUT(TXERR, "TDH wraparound @%x, TDT %x, TDLEN %x\n",
672 tdh_start, s->mac_reg[TDT], s->mac_reg[TDLEN]);
673 break;
674 }
675 }
676 set_ics(s, 0, cause);
677 }
678
679 static int
680 receive_filter(E1000State *s, const uint8_t *buf, int size)
681 {
682 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
683 static const int mta_shift[] = {4, 3, 2, 0};
684 uint32_t f, rctl = s->mac_reg[RCTL], ra[2], *rp;
685
686 if (is_vlan_packet(s, buf) && vlan_rx_filter_enabled(s)) {
687 uint16_t vid = be16_to_cpup((uint16_t *)(buf + 14));
688 uint32_t vfta = le32_to_cpup((uint32_t *)(s->mac_reg + VFTA) +
689 ((vid >> 5) & 0x7f));
690 if ((vfta & (1 << (vid & 0x1f))) == 0)
691 return 0;
692 }
693
694 if (rctl & E1000_RCTL_UPE) // promiscuous
695 return 1;
696
697 if ((buf[0] & 1) && (rctl & E1000_RCTL_MPE)) // promiscuous mcast
698 return 1;
699
700 if ((rctl & E1000_RCTL_BAM) && !memcmp(buf, bcast, sizeof bcast))
701 return 1;
702
703 for (rp = s->mac_reg + RA; rp < s->mac_reg + RA + 32; rp += 2) {
704 if (!(rp[1] & E1000_RAH_AV))
705 continue;
706 ra[0] = cpu_to_le32(rp[0]);
707 ra[1] = cpu_to_le32(rp[1]);
708 if (!memcmp(buf, (uint8_t *)ra, 6)) {
709 DBGOUT(RXFILTER,
710 "unicast match[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
711 (int)(rp - s->mac_reg - RA)/2,
712 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
713 return 1;
714 }
715 }
716 DBGOUT(RXFILTER, "unicast mismatch: %02x:%02x:%02x:%02x:%02x:%02x\n",
717 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
718
719 f = mta_shift[(rctl >> E1000_RCTL_MO_SHIFT) & 3];
720 f = (((buf[5] << 8) | buf[4]) >> f) & 0xfff;
721 if (s->mac_reg[MTA + (f >> 5)] & (1 << (f & 0x1f)))
722 return 1;
723 DBGOUT(RXFILTER,
724 "dropping, inexact filter mismatch: %02x:%02x:%02x:%02x:%02x:%02x MO %d MTA[%d] %x\n",
725 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
726 (rctl >> E1000_RCTL_MO_SHIFT) & 3, f >> 5,
727 s->mac_reg[MTA + (f >> 5)]);
728
729 return 0;
730 }
731
732 static void
733 e1000_set_link_status(NetClientState *nc)
734 {
735 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
736 uint32_t old_status = s->mac_reg[STATUS];
737
738 if (nc->link_down) {
739 e1000_link_down(s);
740 } else {
741 e1000_link_up(s);
742 }
743
744 if (s->mac_reg[STATUS] != old_status)
745 set_ics(s, 0, E1000_ICR_LSC);
746 }
747
748 static bool e1000_has_rxbufs(E1000State *s, size_t total_size)
749 {
750 int bufs;
751 /* Fast-path short packets */
752 if (total_size <= s->rxbuf_size) {
753 return s->mac_reg[RDH] != s->mac_reg[RDT];
754 }
755 if (s->mac_reg[RDH] < s->mac_reg[RDT]) {
756 bufs = s->mac_reg[RDT] - s->mac_reg[RDH];
757 } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) {
758 bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) +
759 s->mac_reg[RDT] - s->mac_reg[RDH];
760 } else {
761 return false;
762 }
763 return total_size <= bufs * s->rxbuf_size;
764 }
765
766 static int
767 e1000_can_receive(NetClientState *nc)
768 {
769 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
770
771 return (s->mac_reg[RCTL] & E1000_RCTL_EN) && e1000_has_rxbufs(s, 1);
772 }
773
774 static uint64_t rx_desc_base(E1000State *s)
775 {
776 uint64_t bah = s->mac_reg[RDBAH];
777 uint64_t bal = s->mac_reg[RDBAL] & ~0xf;
778
779 return (bah << 32) + bal;
780 }
781
782 static ssize_t
783 e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size)
784 {
785 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
786 struct e1000_rx_desc desc;
787 dma_addr_t base;
788 unsigned int n, rdt;
789 uint32_t rdh_start;
790 uint16_t vlan_special = 0;
791 uint8_t vlan_status = 0, vlan_offset = 0;
792 uint8_t min_buf[MIN_BUF_SIZE];
793 size_t desc_offset;
794 size_t desc_size;
795 size_t total_size;
796
797 if (!(s->mac_reg[RCTL] & E1000_RCTL_EN))
798 return -1;
799
800 /* Pad to minimum Ethernet frame length */
801 if (size < sizeof(min_buf)) {
802 memcpy(min_buf, buf, size);
803 memset(&min_buf[size], 0, sizeof(min_buf) - size);
804 buf = min_buf;
805 size = sizeof(min_buf);
806 }
807
808 if (!receive_filter(s, buf, size))
809 return size;
810
811 if (vlan_enabled(s) && is_vlan_packet(s, buf)) {
812 vlan_special = cpu_to_le16(be16_to_cpup((uint16_t *)(buf + 14)));
813 memmove((uint8_t *)buf + 4, buf, 12);
814 vlan_status = E1000_RXD_STAT_VP;
815 vlan_offset = 4;
816 size -= 4;
817 }
818
819 rdh_start = s->mac_reg[RDH];
820 desc_offset = 0;
821 total_size = size + fcs_len(s);
822 if (!e1000_has_rxbufs(s, total_size)) {
823 set_ics(s, 0, E1000_ICS_RXO);
824 return -1;
825 }
826 do {
827 desc_size = total_size - desc_offset;
828 if (desc_size > s->rxbuf_size) {
829 desc_size = s->rxbuf_size;
830 }
831 base = rx_desc_base(s) + sizeof(desc) * s->mac_reg[RDH];
832 pci_dma_read(&s->dev, base, &desc, sizeof(desc));
833 desc.special = vlan_special;
834 desc.status |= (vlan_status | E1000_RXD_STAT_DD);
835 if (desc.buffer_addr) {
836 if (desc_offset < size) {
837 size_t copy_size = size - desc_offset;
838 if (copy_size > s->rxbuf_size) {
839 copy_size = s->rxbuf_size;
840 }
841 pci_dma_write(&s->dev, le64_to_cpu(desc.buffer_addr),
842 buf + desc_offset + vlan_offset, copy_size);
843 }
844 desc_offset += desc_size;
845 desc.length = cpu_to_le16(desc_size);
846 if (desc_offset >= total_size) {
847 desc.status |= E1000_RXD_STAT_EOP | E1000_RXD_STAT_IXSM;
848 } else {
849 /* Guest zeroing out status is not a hardware requirement.
850 Clear EOP in case guest didn't do it. */
851 desc.status &= ~E1000_RXD_STAT_EOP;
852 }
853 } else { // as per intel docs; skip descriptors with null buf addr
854 DBGOUT(RX, "Null RX descriptor!!\n");
855 }
856 pci_dma_write(&s->dev, base, &desc, sizeof(desc));
857
858 if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN])
859 s->mac_reg[RDH] = 0;
860 /* see comment in start_xmit; same here */
861 if (s->mac_reg[RDH] == rdh_start) {
862 DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n",
863 rdh_start, s->mac_reg[RDT], s->mac_reg[RDLEN]);
864 set_ics(s, 0, E1000_ICS_RXO);
865 return -1;
866 }
867 } while (desc_offset < total_size);
868
869 s->mac_reg[GPRC]++;
870 s->mac_reg[TPR]++;
871 /* TOR - Total Octets Received:
872 * This register includes bytes received in a packet from the <Destination
873 * Address> field through the <CRC> field, inclusively.
874 */
875 n = s->mac_reg[TORL] + size + /* Always include FCS length. */ 4;
876 if (n < s->mac_reg[TORL])
877 s->mac_reg[TORH]++;
878 s->mac_reg[TORL] = n;
879
880 n = E1000_ICS_RXT0;
881 if ((rdt = s->mac_reg[RDT]) < s->mac_reg[RDH])
882 rdt += s->mac_reg[RDLEN] / sizeof(desc);
883 if (((rdt - s->mac_reg[RDH]) * sizeof(desc)) <= s->mac_reg[RDLEN] >>
884 s->rxbuf_min_shift)
885 n |= E1000_ICS_RXDMT0;
886
887 set_ics(s, 0, n);
888
889 return size;
890 }
891
892 static uint32_t
893 mac_readreg(E1000State *s, int index)
894 {
895 return s->mac_reg[index];
896 }
897
898 static uint32_t
899 mac_icr_read(E1000State *s, int index)
900 {
901 uint32_t ret = s->mac_reg[ICR];
902
903 DBGOUT(INTERRUPT, "ICR read: %x\n", ret);
904 set_interrupt_cause(s, 0, 0);
905 return ret;
906 }
907
908 static uint32_t
909 mac_read_clr4(E1000State *s, int index)
910 {
911 uint32_t ret = s->mac_reg[index];
912
913 s->mac_reg[index] = 0;
914 return ret;
915 }
916
917 static uint32_t
918 mac_read_clr8(E1000State *s, int index)
919 {
920 uint32_t ret = s->mac_reg[index];
921
922 s->mac_reg[index] = 0;
923 s->mac_reg[index-1] = 0;
924 return ret;
925 }
926
927 static void
928 mac_writereg(E1000State *s, int index, uint32_t val)
929 {
930 s->mac_reg[index] = val;
931 }
932
933 static void
934 set_rdt(E1000State *s, int index, uint32_t val)
935 {
936 s->mac_reg[index] = val & 0xffff;
937 if (e1000_has_rxbufs(s, 1)) {
938 qemu_flush_queued_packets(&s->nic->nc);
939 }
940 }
941
942 static void
943 set_16bit(E1000State *s, int index, uint32_t val)
944 {
945 s->mac_reg[index] = val & 0xffff;
946 }
947
948 static void
949 set_dlen(E1000State *s, int index, uint32_t val)
950 {
951 s->mac_reg[index] = val & 0xfff80;
952 }
953
954 static void
955 set_tctl(E1000State *s, int index, uint32_t val)
956 {
957 s->mac_reg[index] = val;
958 s->mac_reg[TDT] &= 0xffff;
959 start_xmit(s);
960 }
961
962 static void
963 set_icr(E1000State *s, int index, uint32_t val)
964 {
965 DBGOUT(INTERRUPT, "set_icr %x\n", val);
966 set_interrupt_cause(s, 0, s->mac_reg[ICR] & ~val);
967 }
968
969 static void
970 set_imc(E1000State *s, int index, uint32_t val)
971 {
972 s->mac_reg[IMS] &= ~val;
973 set_ics(s, 0, 0);
974 }
975
976 static void
977 set_ims(E1000State *s, int index, uint32_t val)
978 {
979 s->mac_reg[IMS] |= val;
980 set_ics(s, 0, 0);
981 }
982
983 #define getreg(x) [x] = mac_readreg
984 static uint32_t (*macreg_readops[])(E1000State *, int) = {
985 getreg(PBA), getreg(RCTL), getreg(TDH), getreg(TXDCTL),
986 getreg(WUFC), getreg(TDT), getreg(CTRL), getreg(LEDCTL),
987 getreg(MANC), getreg(MDIC), getreg(SWSM), getreg(STATUS),
988 getreg(TORL), getreg(TOTL), getreg(IMS), getreg(TCTL),
989 getreg(RDH), getreg(RDT), getreg(VET), getreg(ICS),
990 getreg(TDBAL), getreg(TDBAH), getreg(RDBAH), getreg(RDBAL),
991 getreg(TDLEN), getreg(RDLEN),
992
993 [TOTH] = mac_read_clr8, [TORH] = mac_read_clr8, [GPRC] = mac_read_clr4,
994 [GPTC] = mac_read_clr4, [TPR] = mac_read_clr4, [TPT] = mac_read_clr4,
995 [ICR] = mac_icr_read, [EECD] = get_eecd, [EERD] = flash_eerd_read,
996 [CRCERRS ... MPC] = &mac_readreg,
997 [RA ... RA+31] = &mac_readreg,
998 [MTA ... MTA+127] = &mac_readreg,
999 [VFTA ... VFTA+127] = &mac_readreg,
1000 };
1001 enum { NREADOPS = ARRAY_SIZE(macreg_readops) };
1002
1003 #define putreg(x) [x] = mac_writereg
1004 static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {
1005 putreg(PBA), putreg(EERD), putreg(SWSM), putreg(WUFC),
1006 putreg(TDBAL), putreg(TDBAH), putreg(TXDCTL), putreg(RDBAH),
1007 putreg(RDBAL), putreg(LEDCTL), putreg(VET),
1008 [TDLEN] = set_dlen, [RDLEN] = set_dlen, [TCTL] = set_tctl,
1009 [TDT] = set_tctl, [MDIC] = set_mdic, [ICS] = set_ics,
1010 [TDH] = set_16bit, [RDH] = set_16bit, [RDT] = set_rdt,
1011 [IMC] = set_imc, [IMS] = set_ims, [ICR] = set_icr,
1012 [EECD] = set_eecd, [RCTL] = set_rx_control, [CTRL] = set_ctrl,
1013 [RA ... RA+31] = &mac_writereg,
1014 [MTA ... MTA+127] = &mac_writereg,
1015 [VFTA ... VFTA+127] = &mac_writereg,
1016 };
1017
1018 enum { NWRITEOPS = ARRAY_SIZE(macreg_writeops) };
1019
1020 static void
1021 e1000_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1022 unsigned size)
1023 {
1024 E1000State *s = opaque;
1025 unsigned int index = (addr & 0x1ffff) >> 2;
1026
1027 if (index < NWRITEOPS && macreg_writeops[index]) {
1028 macreg_writeops[index](s, index, val);
1029 } else if (index < NREADOPS && macreg_readops[index]) {
1030 DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04"PRIx64"\n", index<<2, val);
1031 } else {
1032 DBGOUT(UNKNOWN, "MMIO unknown write addr=0x%08x,val=0x%08"PRIx64"\n",
1033 index<<2, val);
1034 }
1035 }
1036
1037 static uint64_t
1038 e1000_mmio_read(void *opaque, hwaddr addr, unsigned size)
1039 {
1040 E1000State *s = opaque;
1041 unsigned int index = (addr & 0x1ffff) >> 2;
1042
1043 if (index < NREADOPS && macreg_readops[index])
1044 {
1045 return macreg_readops[index](s, index);
1046 }
1047 DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
1048 return 0;
1049 }
1050
1051 static const MemoryRegionOps e1000_mmio_ops = {
1052 .read = e1000_mmio_read,
1053 .write = e1000_mmio_write,
1054 .endianness = DEVICE_LITTLE_ENDIAN,
1055 .impl = {
1056 .min_access_size = 4,
1057 .max_access_size = 4,
1058 },
1059 };
1060
1061 static uint64_t e1000_io_read(void *opaque, hwaddr addr,
1062 unsigned size)
1063 {
1064 E1000State *s = opaque;
1065
1066 (void)s;
1067 return 0;
1068 }
1069
1070 static void e1000_io_write(void *opaque, hwaddr addr,
1071 uint64_t val, unsigned size)
1072 {
1073 E1000State *s = opaque;
1074
1075 (void)s;
1076 }
1077
1078 static const MemoryRegionOps e1000_io_ops = {
1079 .read = e1000_io_read,
1080 .write = e1000_io_write,
1081 .endianness = DEVICE_LITTLE_ENDIAN,
1082 };
1083
1084 static bool is_version_1(void *opaque, int version_id)
1085 {
1086 return version_id == 1;
1087 }
1088
1089 static int e1000_post_load(void *opaque, int version_id)
1090 {
1091 E1000State *s = opaque;
1092
1093 /* nc.link_down can't be migrated, so infer link_down according
1094 * to link status bit in mac_reg[STATUS] */
1095 s->nic->nc.link_down = (s->mac_reg[STATUS] & E1000_STATUS_LU) == 0;
1096
1097 return 0;
1098 }
1099
1100 static const VMStateDescription vmstate_e1000 = {
1101 .name = "e1000",
1102 .version_id = 2,
1103 .minimum_version_id = 1,
1104 .minimum_version_id_old = 1,
1105 .post_load = e1000_post_load,
1106 .fields = (VMStateField []) {
1107 VMSTATE_PCI_DEVICE(dev, E1000State),
1108 VMSTATE_UNUSED_TEST(is_version_1, 4), /* was instance id */
1109 VMSTATE_UNUSED(4), /* Was mmio_base. */
1110 VMSTATE_UINT32(rxbuf_size, E1000State),
1111 VMSTATE_UINT32(rxbuf_min_shift, E1000State),
1112 VMSTATE_UINT32(eecd_state.val_in, E1000State),
1113 VMSTATE_UINT16(eecd_state.bitnum_in, E1000State),
1114 VMSTATE_UINT16(eecd_state.bitnum_out, E1000State),
1115 VMSTATE_UINT16(eecd_state.reading, E1000State),
1116 VMSTATE_UINT32(eecd_state.old_eecd, E1000State),
1117 VMSTATE_UINT8(tx.ipcss, E1000State),
1118 VMSTATE_UINT8(tx.ipcso, E1000State),
1119 VMSTATE_UINT16(tx.ipcse, E1000State),
1120 VMSTATE_UINT8(tx.tucss, E1000State),
1121 VMSTATE_UINT8(tx.tucso, E1000State),
1122 VMSTATE_UINT16(tx.tucse, E1000State),
1123 VMSTATE_UINT32(tx.paylen, E1000State),
1124 VMSTATE_UINT8(tx.hdr_len, E1000State),
1125 VMSTATE_UINT16(tx.mss, E1000State),
1126 VMSTATE_UINT16(tx.size, E1000State),
1127 VMSTATE_UINT16(tx.tso_frames, E1000State),
1128 VMSTATE_UINT8(tx.sum_needed, E1000State),
1129 VMSTATE_INT8(tx.ip, E1000State),
1130 VMSTATE_INT8(tx.tcp, E1000State),
1131 VMSTATE_BUFFER(tx.header, E1000State),
1132 VMSTATE_BUFFER(tx.data, E1000State),
1133 VMSTATE_UINT16_ARRAY(eeprom_data, E1000State, 64),
1134 VMSTATE_UINT16_ARRAY(phy_reg, E1000State, 0x20),
1135 VMSTATE_UINT32(mac_reg[CTRL], E1000State),
1136 VMSTATE_UINT32(mac_reg[EECD], E1000State),
1137 VMSTATE_UINT32(mac_reg[EERD], E1000State),
1138 VMSTATE_UINT32(mac_reg[GPRC], E1000State),
1139 VMSTATE_UINT32(mac_reg[GPTC], E1000State),
1140 VMSTATE_UINT32(mac_reg[ICR], E1000State),
1141 VMSTATE_UINT32(mac_reg[ICS], E1000State),
1142 VMSTATE_UINT32(mac_reg[IMC], E1000State),
1143 VMSTATE_UINT32(mac_reg[IMS], E1000State),
1144 VMSTATE_UINT32(mac_reg[LEDCTL], E1000State),
1145 VMSTATE_UINT32(mac_reg[MANC], E1000State),
1146 VMSTATE_UINT32(mac_reg[MDIC], E1000State),
1147 VMSTATE_UINT32(mac_reg[MPC], E1000State),
1148 VMSTATE_UINT32(mac_reg[PBA], E1000State),
1149 VMSTATE_UINT32(mac_reg[RCTL], E1000State),
1150 VMSTATE_UINT32(mac_reg[RDBAH], E1000State),
1151 VMSTATE_UINT32(mac_reg[RDBAL], E1000State),
1152 VMSTATE_UINT32(mac_reg[RDH], E1000State),
1153 VMSTATE_UINT32(mac_reg[RDLEN], E1000State),
1154 VMSTATE_UINT32(mac_reg[RDT], E1000State),
1155 VMSTATE_UINT32(mac_reg[STATUS], E1000State),
1156 VMSTATE_UINT32(mac_reg[SWSM], E1000State),
1157 VMSTATE_UINT32(mac_reg[TCTL], E1000State),
1158 VMSTATE_UINT32(mac_reg[TDBAH], E1000State),
1159 VMSTATE_UINT32(mac_reg[TDBAL], E1000State),
1160 VMSTATE_UINT32(mac_reg[TDH], E1000State),
1161 VMSTATE_UINT32(mac_reg[TDLEN], E1000State),
1162 VMSTATE_UINT32(mac_reg[TDT], E1000State),
1163 VMSTATE_UINT32(mac_reg[TORH], E1000State),
1164 VMSTATE_UINT32(mac_reg[TORL], E1000State),
1165 VMSTATE_UINT32(mac_reg[TOTH], E1000State),
1166 VMSTATE_UINT32(mac_reg[TOTL], E1000State),
1167 VMSTATE_UINT32(mac_reg[TPR], E1000State),
1168 VMSTATE_UINT32(mac_reg[TPT], E1000State),
1169 VMSTATE_UINT32(mac_reg[TXDCTL], E1000State),
1170 VMSTATE_UINT32(mac_reg[WUFC], E1000State),
1171 VMSTATE_UINT32(mac_reg[VET], E1000State),
1172 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
1173 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, MTA, 128),
1174 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, VFTA, 128),
1175 VMSTATE_END_OF_LIST()
1176 }
1177 };
1178
1179 static const uint16_t e1000_eeprom_template[64] = {
1180 0x0000, 0x0000, 0x0000, 0x0000, 0xffff, 0x0000, 0x0000, 0x0000,
1181 0x3000, 0x1000, 0x6403, E1000_DEVID, 0x8086, E1000_DEVID, 0x8086, 0x3040,
1182 0x0008, 0x2000, 0x7e14, 0x0048, 0x1000, 0x00d8, 0x0000, 0x2700,
1183 0x6cc9, 0x3150, 0x0722, 0x040b, 0x0984, 0x0000, 0xc000, 0x0706,
1184 0x1008, 0x0000, 0x0f04, 0x7fff, 0x4d01, 0xffff, 0xffff, 0xffff,
1185 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1186 0x0100, 0x4000, 0x121c, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
1187 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0x0000,
1188 };
1189
1190 /* PCI interface */
1191
1192 static void
1193 e1000_mmio_setup(E1000State *d)
1194 {
1195 int i;
1196 const uint32_t excluded_regs[] = {
1197 E1000_MDIC, E1000_ICR, E1000_ICS, E1000_IMS,
1198 E1000_IMC, E1000_TCTL, E1000_TDT, PNPMMIO_SIZE
1199 };
1200
1201 memory_region_init_io(&d->mmio, &e1000_mmio_ops, d, "e1000-mmio",
1202 PNPMMIO_SIZE);
1203 memory_region_add_coalescing(&d->mmio, 0, excluded_regs[0]);
1204 for (i = 0; excluded_regs[i] != PNPMMIO_SIZE; i++)
1205 memory_region_add_coalescing(&d->mmio, excluded_regs[i] + 4,
1206 excluded_regs[i+1] - excluded_regs[i] - 4);
1207 memory_region_init_io(&d->io, &e1000_io_ops, d, "e1000-io", IOPORT_SIZE);
1208 }
1209
1210 static void
1211 e1000_cleanup(NetClientState *nc)
1212 {
1213 E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
1214
1215 s->nic = NULL;
1216 }
1217
1218 static void
1219 pci_e1000_uninit(PCIDevice *dev)
1220 {
1221 E1000State *d = DO_UPCAST(E1000State, dev, dev);
1222
1223 qemu_del_timer(d->autoneg_timer);
1224 qemu_free_timer(d->autoneg_timer);
1225 memory_region_destroy(&d->mmio);
1226 memory_region_destroy(&d->io);
1227 qemu_del_net_client(&d->nic->nc);
1228 }
1229
1230 static NetClientInfo net_e1000_info = {
1231 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1232 .size = sizeof(NICState),
1233 .can_receive = e1000_can_receive,
1234 .receive = e1000_receive,
1235 .cleanup = e1000_cleanup,
1236 .link_status_changed = e1000_set_link_status,
1237 };
1238
1239 static int pci_e1000_init(PCIDevice *pci_dev)
1240 {
1241 E1000State *d = DO_UPCAST(E1000State, dev, pci_dev);
1242 uint8_t *pci_conf;
1243 uint16_t checksum = 0;
1244 int i;
1245 uint8_t *macaddr;
1246
1247 pci_conf = d->dev.config;
1248
1249 /* TODO: RST# value should be 0, PCI spec 6.2.4 */
1250 pci_conf[PCI_CACHE_LINE_SIZE] = 0x10;
1251
1252 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
1253
1254 e1000_mmio_setup(d);
1255
1256 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
1257
1258 pci_register_bar(&d->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->io);
1259
1260 memmove(d->eeprom_data, e1000_eeprom_template,
1261 sizeof e1000_eeprom_template);
1262 qemu_macaddr_default_if_unset(&d->conf.macaddr);
1263 macaddr = d->conf.macaddr.a;
1264 for (i = 0; i < 3; i++)
1265 d->eeprom_data[i] = (macaddr[2*i+1]<<8) | macaddr[2*i];
1266 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
1267 checksum += d->eeprom_data[i];
1268 checksum = (uint16_t) EEPROM_SUM - checksum;
1269 d->eeprom_data[EEPROM_CHECKSUM_REG] = checksum;
1270
1271 d->nic = qemu_new_nic(&net_e1000_info, &d->conf,
1272 object_get_typename(OBJECT(d)), d->dev.qdev.id, d);
1273
1274 qemu_format_nic_info_str(&d->nic->nc, macaddr);
1275
1276 add_boot_device_path(d->conf.bootindex, &pci_dev->qdev, "/ethernet-phy@0");
1277
1278 d->autoneg_timer = qemu_new_timer_ms(vm_clock, e1000_autoneg_timer, d);
1279
1280 return 0;
1281 }
1282
1283 static void qdev_e1000_reset(DeviceState *dev)
1284 {
1285 E1000State *d = DO_UPCAST(E1000State, dev.qdev, dev);
1286 e1000_reset(d);
1287 }
1288
1289 static Property e1000_properties[] = {
1290 DEFINE_NIC_PROPERTIES(E1000State, conf),
1291 DEFINE_PROP_END_OF_LIST(),
1292 };
1293
1294 static void e1000_class_init(ObjectClass *klass, void *data)
1295 {
1296 DeviceClass *dc = DEVICE_CLASS(klass);
1297 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1298
1299 k->init = pci_e1000_init;
1300 k->exit = pci_e1000_uninit;
1301 k->romfile = "pxe-e1000.rom";
1302 k->vendor_id = PCI_VENDOR_ID_INTEL;
1303 k->device_id = E1000_DEVID;
1304 k->revision = 0x03;
1305 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
1306 dc->desc = "Intel Gigabit Ethernet";
1307 dc->reset = qdev_e1000_reset;
1308 dc->vmsd = &vmstate_e1000;
1309 dc->props = e1000_properties;
1310 }
1311
1312 static TypeInfo e1000_info = {
1313 .name = "e1000",
1314 .parent = TYPE_PCI_DEVICE,
1315 .instance_size = sizeof(E1000State),
1316 .class_init = e1000_class_init,
1317 };
1318
1319 static void e1000_register_types(void)
1320 {
1321 type_register_static(&e1000_info);
1322 }
1323
1324 type_init(e1000_register_types)
Patch queue for openSUSE QEMU