grackle_pci: QOM'ify Grackle PCI host bridge
[qemu/opensuse.git] / target-mips / cpu-qom.h
blob6e2237123aa1160fae0ba569c83c15c411f202f1
1 /*
2 * QEMU MIPS CPU
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 #ifndef QEMU_MIPS_CPU_QOM_H
21 #define QEMU_MIPS_CPU_QOM_H
23 #include "qemu/cpu.h"
25 #ifdef TARGET_MIPS64
26 #define TYPE_MIPS_CPU "mips64-cpu"
27 #else
28 #define TYPE_MIPS_CPU "mips-cpu"
29 #endif
31 #define MIPS_CPU_CLASS(klass) \
32 OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
33 #define MIPS_CPU(obj) \
34 OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
35 #define MIPS_CPU_GET_CLASS(obj) \
36 OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
38 /**
39 * MIPSCPUClass:
40 * @parent_reset: The parent class' reset handler.
42 * A MIPS CPU model.
44 typedef struct MIPSCPUClass {
45 /*< private >*/
46 CPUClass parent_class;
47 /*< public >*/
49 void (*parent_reset)(CPUState *cpu);
50 } MIPSCPUClass;
52 /**
53 * MIPSCPU:
54 * @env: #CPUMIPSState
56 * A MIPS CPU.
58 typedef struct MIPSCPU {
59 /*< private >*/
60 CPUState parent_obj;
61 /*< public >*/
63 CPUMIPSState env;
64 } MIPSCPU;
66 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
68 return MIPS_CPU(container_of(env, MIPSCPU, env));
71 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
74 #endif