cocoa: Provide central qemu_main() prototype
[qemu/opensuse.git] / target-alpha / exec.h
blob7a325e7a759cd6db5a18fb81ca507eafc3bb4fd5
1 /*
2 * Alpha emulation cpu run-time definitions for qemu.
4 * Copyright (c) 2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #if !defined (__ALPHA_EXEC_H__)
21 #define __ALPHA_EXEC_H__
23 #include "config.h"
25 #include "dyngen-exec.h"
27 #define TARGET_LONG_BITS 64
29 register struct CPUAlphaState *env asm(AREG0);
31 #define FP_STATUS (env->fp_status)
33 #include "cpu.h"
34 #include "exec-all.h"
36 #if !defined(CONFIG_USER_ONLY)
37 #include "softmmu_exec.h"
38 #endif /* !defined(CONFIG_USER_ONLY) */
40 static inline int cpu_has_work(CPUState *env)
42 /* Here we are checking to see if the CPU should wake up from HALT.
43 We will have gotten into this state only for WTINT from PALmode. */
44 /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
45 asleep even if (some) interrupts have been asserted. For now,
46 assume that if a CPU really wants to stay asleep, it will mask
47 interrupts at the chipset level, which will prevent these bits
48 from being set in the first place. */
49 return env->interrupt_request & (CPU_INTERRUPT_HARD
50 | CPU_INTERRUPT_TIMER
51 | CPU_INTERRUPT_SMP
52 | CPU_INTERRUPT_MCHK);
55 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
57 env->pc = tb->pc;
60 #endif /* !defined (__ALPHA_EXEC_H__) */