hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7 #include "memory.h"
   8 #include "dma.h"
   9
  10 /* PCI includes legacy ISA access.  */
  11 #include "isa.h"
  12
  13 #include "pcie.h"
  14
  15 /* PCI bus */
  16
  17 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  18 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  19 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  20 #define PCI_SLOT_MAX            32
  21 #define PCI_FUNC_MAX            8
  22
  23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  24 #include "pci_ids.h"
  25
  26 /* QEMU-specific Vendor and Device ID definitions */
  27
  28 /* IBM (0x1014) */
  29 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  30 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  31
  32 /* Hitachi (0x1054) */
  33 #define PCI_VENDOR_ID_HITACHI            0x1054
  34 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  35
  36 /* Apple (0x106b) */
  37 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  41 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  42
  43 /* Realtek (0x10ec) */
  44 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  45
  46 /* Xilinx (0x10ee) */
  47 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  48
  49 /* Marvell (0x11ab) */
  50 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  51
  52 /* QEMU/Bochs VGA (0x1234) */
  53 #define PCI_VENDOR_ID_QEMU               0x1234
  54 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  55
  56 /* VMWare (0x15ad) */
  57 #define PCI_VENDOR_ID_VMWARE             0x15ad
  58 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  59 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  60 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  61 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  62 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  63
  64 /* Intel (0x8086) */
  65 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  66 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  67 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  68
  69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  70 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  72 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  73
  74 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  75 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  76 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  78 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  79
  80 #define FMT_PCIBUS                      PRIx64
  81
  82 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  83                                 uint32_t address, uint32_t data, int len);
  84 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  85                                    uint32_t address, int len);
  86 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  87                                 pcibus_t addr, pcibus_t size, int type);
  88 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  89
  90 typedef struct PCIIORegion {
  91     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  92 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  93     pcibus_t size;
  94     uint8_t type;
  95     MemoryRegion *memory;
  96     MemoryRegion *address_space;
  97 } PCIIORegion;
  98
  99 #define PCI_ROM_SLOT 6
 100 #define PCI_NUM_REGIONS 7
 101
 102 #include "pci_regs.h"
 103
 104 /* PCI HEADER_TYPE */
 105 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 106
 107 /* Size of the standard PCI config header */
 108 #define PCI_CONFIG_HEADER_SIZE 0x40
 109 /* Size of the standard PCI config space */
 110 #define PCI_CONFIG_SPACE_SIZE 0x100
 111 /* Size of the standart PCIe config space: 4KB */
 112 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 113
 114 #define PCI_NUM_PINS 4 /* A-D */
 115
 116 /* Bits in cap_present field. */
 117 enum {
 118     QEMU_PCI_CAP_MSI = 0x1,
 119     QEMU_PCI_CAP_MSIX = 0x2,
 120     QEMU_PCI_CAP_EXPRESS = 0x4,
 121
 122     /* multifunction capable device */
 123 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 124     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 125
 126     /* command register SERR bit enabled */
 127 #define QEMU_PCI_CAP_SERR_BITNR 4
 128     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 129     /* Standard hot plug controller. */
 130 #define QEMU_PCI_SHPC_BITNR 5
 131     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 132 #define QEMU_PCI_SLOTID_BITNR 6
 133     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 134 };
 135
 136 #define TYPE_PCI_DEVICE "pci-device"
 137 #define PCI_DEVICE(obj) \
 138      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 139 #define PCI_DEVICE_CLASS(klass) \
 140      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 141 #define PCI_DEVICE_GET_CLASS(obj) \
 142      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 143
 144 typedef struct PCIDeviceClass {
 145     DeviceClass parent_class;
 146
 147     int (*init)(PCIDevice *dev);
 148     PCIUnregisterFunc *exit;
 149     PCIConfigReadFunc *config_read;
 150     PCIConfigWriteFunc *config_write;
 151
 152     uint16_t vendor_id;
 153     uint16_t device_id;
 154     uint8_t revision;
 155     uint16_t class_id;
 156     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 157     uint16_t subsystem_id;              /* only for header type = 0 */
 158
 159     /*
 160      * pci-to-pci bridge or normal device.
 161      * This doesn't mean pci host switch.
 162      * When card bus bridge is supported, this would be enhanced.
 163      */
 164     int is_bridge;
 165
 166     /* pcie stuff */
 167     int is_express;   /* is this device pci express? */
 168
 169     /* device isn't hot-pluggable */
 170     int no_hotplug;
 171
 172     /* rom bar */
 173     const char *romfile;
 174 } PCIDeviceClass;
 175
 176 struct PCIDevice {
 177     DeviceState qdev;
 178     /* PCI config space */
 179     uint8_t *config;
 180
 181     /* Used to enable config checks on load. Note that writable bits are
 182      * never checked even if set in cmask. */
 183     uint8_t *cmask;
 184
 185     /* Used to implement R/W bytes */
 186     uint8_t *wmask;
 187
 188     /* Used to implement RW1C(Write 1 to Clear) bytes */
 189     uint8_t *w1cmask;
 190
 191     /* Used to allocate config space for capabilities. */
 192     uint8_t *used;
 193
 194     /* the following fields are read only */
 195     PCIBus *bus;
 196     uint32_t devfn;
 197     char name[64];
 198     PCIIORegion io_regions[PCI_NUM_REGIONS];
 199
 200     /* do not access the following fields */
 201     PCIConfigReadFunc *config_read;
 202     PCIConfigWriteFunc *config_write;
 203
 204     /* IRQ objects for the INTA-INTD pins.  */
 205     qemu_irq *irq;
 206
 207     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 208     uint8_t irq_state;
 209
 210     /* Capability bits */
 211     uint32_t cap_present;
 212
 213     /* Offset of MSI-X capability in config space */
 214     uint8_t msix_cap;
 215
 216     /* MSI-X entries */
 217     int msix_entries_nr;
 218
 219     /* Space to store MSIX table */
 220     uint8_t *msix_table_page;
 221     /* MMIO index used to map MSIX table and pending bit entries. */
 222     MemoryRegion msix_mmio;
 223     /* Reference-count for entries actually in use by driver. */
 224     unsigned *msix_entry_used;
 225     /* Region including the MSI-X table */
 226     uint32_t msix_bar_size;
 227     /* MSIX function mask set or MSIX disabled */
 228     bool msix_function_masked;
 229     /* Version id needed for VMState */
 230     int32_t version_id;
 231
 232     /* Offset of MSI capability in config space */
 233     uint8_t msi_cap;
 234
 235     /* PCI Express */
 236     PCIExpressDevice exp;
 237
 238     /* SHPC */
 239     SHPCDevice *shpc;
 240
 241     /* Location of option rom */
 242     char *romfile;
 243     bool has_rom;
 244     MemoryRegion rom;
 245     uint32_t rom_bar;
 246 };
 247
 248 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 249                       uint8_t attr, MemoryRegion *memory);
 250 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 251
 252 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 253                        uint8_t offset, uint8_t size);
 254
 255 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 256
 257 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 258
 259
 260 uint32_t pci_default_read_config(PCIDevice *d,
 261                                  uint32_t address, int len);
 262 void pci_default_write_config(PCIDevice *d,
 263                               uint32_t address, uint32_t val, int len);
 264 void pci_device_save(PCIDevice *s, QEMUFile *f);
 265 int pci_device_load(PCIDevice *s, QEMUFile *f);
 266 MemoryRegion *pci_address_space(PCIDevice *dev);
 267 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 268
 269 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 270 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 271
 272 typedef enum {
 273     PCI_HOTPLUG_DISABLED,
 274     PCI_HOTPLUG_ENABLED,
 275     PCI_COLDPLUG_ENABLED,
 276 } PCIHotplugState;
 277
 278 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
 279                               PCIHotplugState state);
 280 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 281                          const char *name,
 282                          MemoryRegion *address_space_mem,
 283                          MemoryRegion *address_space_io,
 284                          uint8_t devfn_min);
 285 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 286                     MemoryRegion *address_space_mem,
 287                     MemoryRegion *address_space_io,
 288                     uint8_t devfn_min);
 289 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 290                   void *irq_opaque, int nirq);
 291 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 292 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
 293 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 294                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 295                          void *irq_opaque,
 296                          MemoryRegion *address_space_mem,
 297                          MemoryRegion *address_space_io,
 298                          uint8_t devfn_min, int nirq);
 299 void pci_device_reset(PCIDevice *dev);
 300 void pci_bus_reset(PCIBus *bus);
 301
 302 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 303                         const char *default_devaddr);
 304 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 305                                const char *default_devaddr);
 306 int pci_bus_num(PCIBus *s);
 307 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 308 PCIBus *pci_find_root_bus(int domain);
 309 int pci_find_domain(const PCIBus *bus);
 310 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 311 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 312 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 313
 314 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 315                      unsigned *slotp);
 316
 317 void pci_device_deassert_intx(PCIDevice *dev);
 318
 319 static inline void
 320 pci_set_byte(uint8_t *config, uint8_t val)
 321 {
 322     *config = val;
 323 }
 324
 325 static inline uint8_t
 326 pci_get_byte(const uint8_t *config)
 327 {
 328     return *config;
 329 }
 330
 331 static inline void
 332 pci_set_word(uint8_t *config, uint16_t val)
 333 {
 334     cpu_to_le16wu((uint16_t *)config, val);
 335 }
 336
 337 static inline uint16_t
 338 pci_get_word(const uint8_t *config)
 339 {
 340     return le16_to_cpupu((const uint16_t *)config);
 341 }
 342
 343 static inline void
 344 pci_set_long(uint8_t *config, uint32_t val)
 345 {
 346     cpu_to_le32wu((uint32_t *)config, val);
 347 }
 348
 349 static inline uint32_t
 350 pci_get_long(const uint8_t *config)
 351 {
 352     return le32_to_cpupu((const uint32_t *)config);
 353 }
 354
 355 static inline void
 356 pci_set_quad(uint8_t *config, uint64_t val)
 357 {
 358     cpu_to_le64w((uint64_t *)config, val);
 359 }
 360
 361 static inline uint64_t
 362 pci_get_quad(const uint8_t *config)
 363 {
 364     return le64_to_cpup((const uint64_t *)config);
 365 }
 366
 367 static inline void
 368 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 369 {
 370     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 371 }
 372
 373 static inline void
 374 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 375 {
 376     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 377 }
 378
 379 static inline void
 380 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 381 {
 382     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 383 }
 384
 385 static inline void
 386 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 387 {
 388     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 389 }
 390
 391 static inline void
 392 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 393 {
 394     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 395 }
 396
 397 static inline void
 398 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 399 {
 400     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 401 }
 402
 403 /*
 404  * helper functions to do bit mask operation on configuration space.
 405  * Just to set bit, use test-and-set and discard returned value.
 406  * Just to clear bit, use test-and-clear and discard returned value.
 407  * NOTE: They aren't atomic.
 408  */
 409 static inline uint8_t
 410 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 411 {
 412     uint8_t val = pci_get_byte(config);
 413     pci_set_byte(config, val & ~mask);
 414     return val & mask;
 415 }
 416
 417 static inline uint8_t
 418 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 419 {
 420     uint8_t val = pci_get_byte(config);
 421     pci_set_byte(config, val | mask);
 422     return val & mask;
 423 }
 424
 425 static inline uint16_t
 426 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 427 {
 428     uint16_t val = pci_get_word(config);
 429     pci_set_word(config, val & ~mask);
 430     return val & mask;
 431 }
 432
 433 static inline uint16_t
 434 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 435 {
 436     uint16_t val = pci_get_word(config);
 437     pci_set_word(config, val | mask);
 438     return val & mask;
 439 }
 440
 441 static inline uint32_t
 442 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 443 {
 444     uint32_t val = pci_get_long(config);
 445     pci_set_long(config, val & ~mask);
 446     return val & mask;
 447 }
 448
 449 static inline uint32_t
 450 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 451 {
 452     uint32_t val = pci_get_long(config);
 453     pci_set_long(config, val | mask);
 454     return val & mask;
 455 }
 456
 457 static inline uint64_t
 458 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 459 {
 460     uint64_t val = pci_get_quad(config);
 461     pci_set_quad(config, val & ~mask);
 462     return val & mask;
 463 }
 464
 465 static inline uint64_t
 466 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 467 {
 468     uint64_t val = pci_get_quad(config);
 469     pci_set_quad(config, val | mask);
 470     return val & mask;
 471 }
 472
 473 /* Access a register specified by a mask */
 474 static inline void
 475 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 476 {
 477     uint8_t val = pci_get_byte(config);
 478     uint8_t rval = reg << (ffs(mask) - 1);
 479     pci_set_byte(config, (~mask & val) | (mask & rval));
 480 }
 481
 482 static inline uint8_t
 483 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 484 {
 485     uint8_t val = pci_get_byte(config);
 486     return (val & mask) >> (ffs(mask) - 1);
 487 }
 488
 489 static inline void
 490 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 491 {
 492     uint16_t val = pci_get_word(config);
 493     uint16_t rval = reg << (ffs(mask) - 1);
 494     pci_set_word(config, (~mask & val) | (mask & rval));
 495 }
 496
 497 static inline uint16_t
 498 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 499 {
 500     uint16_t val = pci_get_word(config);
 501     return (val & mask) >> (ffs(mask) - 1);
 502 }
 503
 504 static inline void
 505 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 506 {
 507     uint32_t val = pci_get_long(config);
 508     uint32_t rval = reg << (ffs(mask) - 1);
 509     pci_set_long(config, (~mask & val) | (mask & rval));
 510 }
 511
 512 static inline uint32_t
 513 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 514 {
 515     uint32_t val = pci_get_long(config);
 516     return (val & mask) >> (ffs(mask) - 1);
 517 }
 518
 519 static inline void
 520 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 521 {
 522     uint64_t val = pci_get_quad(config);
 523     uint64_t rval = reg << (ffs(mask) - 1);
 524     pci_set_quad(config, (~mask & val) | (mask & rval));
 525 }
 526
 527 static inline uint64_t
 528 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 529 {
 530     uint64_t val = pci_get_quad(config);
 531     return (val & mask) >> (ffs(mask) - 1);
 532 }
 533
 534 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 535                                     const char *name);
 536 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 537                                            bool multifunction,
 538                                            const char *name);
 539 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 540 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 541
 542 static inline int pci_is_express(const PCIDevice *d)
 543 {
 544     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 545 }
 546
 547 static inline uint32_t pci_config_size(const PCIDevice *d)
 548 {
 549     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 550 }
 551
 552 /* DMA access functions */
 553 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 554                              void *buf, dma_addr_t len, DMADirection dir)
 555 {
 556     cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
 557     return 0;
 558 }
 559
 560 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 561                                void *buf, dma_addr_t len)
 562 {
 563     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 564 }
 565
 566 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 567                                 const void *buf, dma_addr_t len)
 568 {
 569     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 570 }
 571
 572 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 573     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 574                                                    dma_addr_t addr)     \
 575     {                                                                   \
 576         return ld##_l##_phys(addr);                                     \
 577     }                                                                   \
 578     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 579                           dma_addr_t addr, uint##_bits##_t val)         \
 580     {                                                                   \
 581         st##_s##_phys(addr, val);                                       \
 582     }
 583
 584 PCI_DMA_DEFINE_LDST(ub, b, 8);
 585 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 586 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 587 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 588 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 589 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 590 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 591
 592 #undef PCI_DMA_DEFINE_LDST
 593
 594 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 595                                 dma_addr_t *plen, DMADirection dir)
 596 {
 597     target_phys_addr_t len = *plen;
 598     void *buf;
 599
 600     buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
 601     *plen = len;
 602     return buf;
 603 }
 604
 605 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 606                                  DMADirection dir, dma_addr_t access_len)
 607 {
 608     cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
 609                               access_len);
 610 }
 611
 612 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 613                                        int alloc_hint)
 614 {
 615     qemu_sglist_init(qsg, alloc_hint);
 616 }
 617
 618 extern const VMStateDescription vmstate_pci_device;
 619
 620 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 621     .name       = (stringify(_field)),                               \
 622     .size       = sizeof(PCIDevice),                                 \
 623     .vmsd       = &vmstate_pci_device,                               \
 624     .flags      = VMS_STRUCT,                                        \
 625     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 626 }
 627
 628 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 629     .name       = (stringify(_field)),                               \
 630     .size       = sizeof(PCIDevice),                                 \
 631     .vmsd       = &vmstate_pci_device,                               \
 632     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 633     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 634 }
 635
 636 #endif