2 * UniCore32 translation
4 * Copyright (C) 2010-2012 Guan Xuetao
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
26 /* internal defines */
27 typedef struct DisasContext
{
30 /* Nonzero if this instruction has been conditionally skipped. */
32 /* The label that will be jumped to when the instruction is skipped. */
34 struct TranslationBlock
*tb
;
35 int singlestep_enabled
;
36 #ifndef CONFIG_USER_ONLY
41 #ifndef CONFIG_USER_ONLY
42 #define IS_USER(s) (s->user)
47 /* These instructions trap after executing, so defer them until after the
48 conditional executions state has been updated. */
49 #define DISAS_SYSCALL 5
51 static TCGv_ptr cpu_env
;
52 static TCGv_i32 cpu_R
[32];
54 /* FIXME: These should be removed. */
55 static TCGv cpu_F0s
, cpu_F1s
;
56 static TCGv_i64 cpu_F0d
, cpu_F1d
;
58 #include "gen-icount.h"
60 static const char *regnames
[] = {
61 "r00", "r01", "r02", "r03", "r04", "r05", "r06", "r07",
62 "r08", "r09", "r10", "r11", "r12", "r13", "r14", "r15",
63 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
64 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "pc" };
66 /* initialize TCG globals. */
67 void uc32_translate_init(void)
71 cpu_env
= tcg_global_reg_new_ptr(TCG_AREG0
, "env");
73 for (i
= 0; i
< 32; i
++) {
74 cpu_R
[i
] = tcg_global_mem_new_i32(TCG_AREG0
,
75 offsetof(CPUUniCore32State
, regs
[i
]), regnames
[i
]);
84 /* Allocate a temporary variable. */
85 static TCGv_i32
new_tmp(void)
88 return tcg_temp_new_i32();
91 /* Release a temporary variable. */
92 static void dead_tmp(TCGv tmp
)
98 static inline TCGv
load_cpu_offset(int offset
)
100 TCGv tmp
= new_tmp();
101 tcg_gen_ld_i32(tmp
, cpu_env
, offset
);
105 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUUniCore32State, name))
107 static inline void store_cpu_offset(TCGv var
, int offset
)
109 tcg_gen_st_i32(var
, cpu_env
, offset
);
113 #define store_cpu_field(var, name) \
114 store_cpu_offset(var, offsetof(CPUUniCore32State, name))
116 /* Set a variable to the value of a CPU register. */
117 static void load_reg_var(DisasContext
*s
, TCGv var
, int reg
)
121 /* normaly, since we updated PC */
123 tcg_gen_movi_i32(var
, addr
);
125 tcg_gen_mov_i32(var
, cpu_R
[reg
]);
129 /* Create a new temporary and set it to the value of a CPU register. */
130 static inline TCGv
load_reg(DisasContext
*s
, int reg
)
132 TCGv tmp
= new_tmp();
133 load_reg_var(s
, tmp
, reg
);
137 /* Set a CPU register. The source must be a temporary and will be
139 static void store_reg(DisasContext
*s
, int reg
, TCGv var
)
142 tcg_gen_andi_i32(var
, var
, ~3);
143 s
->is_jmp
= DISAS_JUMP
;
145 tcg_gen_mov_i32(cpu_R
[reg
], var
);
149 /* Value extensions. */
150 #define gen_uxtb(var) tcg_gen_ext8u_i32(var, var)
151 #define gen_uxth(var) tcg_gen_ext16u_i32(var, var)
152 #define gen_sxtb(var) tcg_gen_ext8s_i32(var, var)
153 #define gen_sxth(var) tcg_gen_ext16s_i32(var, var)
155 #define UCOP_REG_M (((insn) >> 0) & 0x1f)
156 #define UCOP_REG_N (((insn) >> 19) & 0x1f)
157 #define UCOP_REG_D (((insn) >> 14) & 0x1f)
158 #define UCOP_REG_S (((insn) >> 9) & 0x1f)
159 #define UCOP_REG_LO (((insn) >> 14) & 0x1f)
160 #define UCOP_REG_HI (((insn) >> 9) & 0x1f)
161 #define UCOP_SH_OP (((insn) >> 6) & 0x03)
162 #define UCOP_SH_IM (((insn) >> 9) & 0x1f)
163 #define UCOP_OPCODES (((insn) >> 25) & 0x0f)
164 #define UCOP_IMM_9 (((insn) >> 0) & 0x1ff)
165 #define UCOP_IMM10 (((insn) >> 0) & 0x3ff)
166 #define UCOP_IMM14 (((insn) >> 0) & 0x3fff)
167 #define UCOP_COND (((insn) >> 25) & 0x0f)
168 #define UCOP_CMOV_COND (((insn) >> 19) & 0x0f)
169 #define UCOP_CPNUM (((insn) >> 10) & 0x0f)
170 #define UCOP_UCF64_FMT (((insn) >> 24) & 0x03)
171 #define UCOP_UCF64_FUNC (((insn) >> 6) & 0x0f)
172 #define UCOP_UCF64_COND (((insn) >> 6) & 0x0f)
174 #define UCOP_SET(i) ((insn) & (1 << (i)))
175 #define UCOP_SET_P UCOP_SET(28)
176 #define UCOP_SET_U UCOP_SET(27)
177 #define UCOP_SET_B UCOP_SET(26)
178 #define UCOP_SET_W UCOP_SET(25)
179 #define UCOP_SET_L UCOP_SET(24)
180 #define UCOP_SET_S UCOP_SET(24)
182 #define ILLEGAL cpu_abort(env, \
183 "Illegal UniCore32 instruction %x at line %d!", \
186 #ifndef CONFIG_USER_ONLY
187 static void disas_cp0_insn(CPUUniCore32State
*env
, DisasContext
*s
,
190 TCGv tmp
, tmp2
, tmp3
;
191 if ((insn
& 0xfe000000) == 0xe0000000) {
194 tcg_gen_movi_i32(tmp2
, UCOP_REG_N
);
195 tcg_gen_movi_i32(tmp3
, UCOP_IMM10
);
198 gen_helper_cp0_get(tmp
, cpu_env
, tmp2
, tmp3
);
199 store_reg(s
, UCOP_REG_D
, tmp
);
201 tmp
= load_reg(s
, UCOP_REG_D
);
202 gen_helper_cp0_set(cpu_env
, tmp
, tmp2
, tmp3
);
212 static void disas_ocd_insn(CPUUniCore32State
*env
, DisasContext
*s
,
217 if ((insn
& 0xff003fff) == 0xe1000400) {
219 * movc rd, pp.nn, #imm9
221 * nn: UCOP_REG_N (must be 0)
224 if (UCOP_REG_N
== 0) {
226 tcg_gen_movi_i32(tmp
, 0);
227 store_reg(s
, UCOP_REG_D
, tmp
);
233 if ((insn
& 0xff003fff) == 0xe0000401) {
235 * movc pp.nn, rn, #imm9
237 * nn: UCOP_REG_N (must be 1)
240 if (UCOP_REG_N
== 1) {
241 tmp
= load_reg(s
, UCOP_REG_D
);
242 gen_helper_cp1_putc(tmp
);
253 static inline void gen_set_asr(TCGv var
, uint32_t mask
)
255 TCGv tmp_mask
= tcg_const_i32(mask
);
256 gen_helper_asr_write(cpu_env
, var
, tmp_mask
);
257 tcg_temp_free_i32(tmp_mask
);
259 /* Set NZCV flags from the high 4 bits of var. */
260 #define gen_set_nzcv(var) gen_set_asr(var, ASR_NZCV)
262 static void gen_exception(int excp
)
264 TCGv tmp
= new_tmp();
265 tcg_gen_movi_i32(tmp
, excp
);
266 gen_helper_exception(cpu_env
, tmp
);
270 /* FIXME: Most targets have native widening multiplication.
271 It would be good to use that instead of a full wide multiply. */
272 /* 32x32->64 multiply. Marks inputs as dead. */
273 static TCGv_i64
gen_mulu_i64_i32(TCGv a
, TCGv b
)
275 TCGv_i64 tmp1
= tcg_temp_new_i64();
276 TCGv_i64 tmp2
= tcg_temp_new_i64();
278 tcg_gen_extu_i32_i64(tmp1
, a
);
280 tcg_gen_extu_i32_i64(tmp2
, b
);
282 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
283 tcg_temp_free_i64(tmp2
);
287 static TCGv_i64
gen_muls_i64_i32(TCGv a
, TCGv b
)
289 TCGv_i64 tmp1
= tcg_temp_new_i64();
290 TCGv_i64 tmp2
= tcg_temp_new_i64();
292 tcg_gen_ext_i32_i64(tmp1
, a
);
294 tcg_gen_ext_i32_i64(tmp2
, b
);
296 tcg_gen_mul_i64(tmp1
, tmp1
, tmp2
);
297 tcg_temp_free_i64(tmp2
);
301 #define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUUniCore32State, CF))
303 /* Set CF to the top bit of var. */
304 static void gen_set_CF_bit31(TCGv var
)
306 TCGv tmp
= new_tmp();
307 tcg_gen_shri_i32(tmp
, var
, 31);
312 /* Set N and Z flags from var. */
313 static inline void gen_logic_CC(TCGv var
)
315 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, NF
));
316 tcg_gen_st_i32(var
, cpu_env
, offsetof(CPUUniCore32State
, ZF
));
319 /* dest = T0 + T1 + CF. */
320 static void gen_add_carry(TCGv dest
, TCGv t0
, TCGv t1
)
323 tcg_gen_add_i32(dest
, t0
, t1
);
324 tmp
= load_cpu_field(CF
);
325 tcg_gen_add_i32(dest
, dest
, tmp
);
329 /* dest = T0 - T1 + CF - 1. */
330 static void gen_sub_carry(TCGv dest
, TCGv t0
, TCGv t1
)
333 tcg_gen_sub_i32(dest
, t0
, t1
);
334 tmp
= load_cpu_field(CF
);
335 tcg_gen_add_i32(dest
, dest
, tmp
);
336 tcg_gen_subi_i32(dest
, dest
, 1);
340 static void shifter_out_im(TCGv var
, int shift
)
342 TCGv tmp
= new_tmp();
344 tcg_gen_andi_i32(tmp
, var
, 1);
346 tcg_gen_shri_i32(tmp
, var
, shift
);
348 tcg_gen_andi_i32(tmp
, tmp
, 1);
355 /* Shift by immediate. Includes special handling for shift == 0. */
356 static inline void gen_uc32_shift_im(TCGv var
, int shiftop
, int shift
,
363 shifter_out_im(var
, 32 - shift
);
365 tcg_gen_shli_i32(var
, var
, shift
);
371 tcg_gen_shri_i32(var
, var
, 31);
374 tcg_gen_movi_i32(var
, 0);
377 shifter_out_im(var
, shift
- 1);
379 tcg_gen_shri_i32(var
, var
, shift
);
387 shifter_out_im(var
, shift
- 1);
392 tcg_gen_sari_i32(var
, var
, shift
);
394 case 3: /* ROR/RRX */
397 shifter_out_im(var
, shift
- 1);
399 tcg_gen_rotri_i32(var
, var
, shift
); break;
401 TCGv tmp
= load_cpu_field(CF
);
403 shifter_out_im(var
, 0);
405 tcg_gen_shri_i32(var
, var
, 1);
406 tcg_gen_shli_i32(tmp
, tmp
, 31);
407 tcg_gen_or_i32(var
, var
, tmp
);
413 static inline void gen_uc32_shift_reg(TCGv var
, int shiftop
,
414 TCGv shift
, int flags
)
419 gen_helper_shl_cc(var
, cpu_env
, var
, shift
);
422 gen_helper_shr_cc(var
, cpu_env
, var
, shift
);
425 gen_helper_sar_cc(var
, cpu_env
, var
, shift
);
428 gen_helper_ror_cc(var
, cpu_env
, var
, shift
);
434 gen_helper_shl(var
, var
, shift
);
437 gen_helper_shr(var
, var
, shift
);
440 gen_helper_sar(var
, var
, shift
);
443 tcg_gen_andi_i32(shift
, shift
, 0x1f);
444 tcg_gen_rotr_i32(var
, var
, shift
);
451 static void gen_test_cc(int cc
, int label
)
459 tmp
= load_cpu_field(ZF
);
460 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
463 tmp
= load_cpu_field(ZF
);
464 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
467 tmp
= load_cpu_field(CF
);
468 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
471 tmp
= load_cpu_field(CF
);
472 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
475 tmp
= load_cpu_field(NF
);
476 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
479 tmp
= load_cpu_field(NF
);
480 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
483 tmp
= load_cpu_field(VF
);
484 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
487 tmp
= load_cpu_field(VF
);
488 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
490 case 8: /* hi: C && !Z */
491 inv
= gen_new_label();
492 tmp
= load_cpu_field(CF
);
493 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
495 tmp
= load_cpu_field(ZF
);
496 tcg_gen_brcondi_i32(TCG_COND_NE
, tmp
, 0, label
);
499 case 9: /* ls: !C || Z */
500 tmp
= load_cpu_field(CF
);
501 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
503 tmp
= load_cpu_field(ZF
);
504 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
506 case 10: /* ge: N == V -> N ^ V == 0 */
507 tmp
= load_cpu_field(VF
);
508 tmp2
= load_cpu_field(NF
);
509 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
511 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
513 case 11: /* lt: N != V -> N ^ V != 0 */
514 tmp
= load_cpu_field(VF
);
515 tmp2
= load_cpu_field(NF
);
516 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
518 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
520 case 12: /* gt: !Z && N == V */
521 inv
= gen_new_label();
522 tmp
= load_cpu_field(ZF
);
523 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, inv
);
525 tmp
= load_cpu_field(VF
);
526 tmp2
= load_cpu_field(NF
);
527 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
529 tcg_gen_brcondi_i32(TCG_COND_GE
, tmp
, 0, label
);
532 case 13: /* le: Z || N != V */
533 tmp
= load_cpu_field(ZF
);
534 tcg_gen_brcondi_i32(TCG_COND_EQ
, tmp
, 0, label
);
536 tmp
= load_cpu_field(VF
);
537 tmp2
= load_cpu_field(NF
);
538 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
540 tcg_gen_brcondi_i32(TCG_COND_LT
, tmp
, 0, label
);
543 fprintf(stderr
, "Bad condition code 0x%x\n", cc
);
549 static const uint8_t table_logic_cc
[16] = {
550 1, /* and */ 1, /* xor */ 0, /* sub */ 0, /* rsb */
551 0, /* add */ 0, /* adc */ 0, /* sbc */ 0, /* rsc */
552 1, /* andl */ 1, /* xorl */ 0, /* cmp */ 0, /* cmn */
553 1, /* orr */ 1, /* mov */ 1, /* bic */ 1, /* mvn */
556 /* Set PC state from an immediate address. */
557 static inline void gen_bx_im(DisasContext
*s
, uint32_t addr
)
559 s
->is_jmp
= DISAS_UPDATE
;
560 tcg_gen_movi_i32(cpu_R
[31], addr
& ~3);
563 /* Set PC state from var. var is marked as dead. */
564 static inline void gen_bx(DisasContext
*s
, TCGv var
)
566 s
->is_jmp
= DISAS_UPDATE
;
567 tcg_gen_andi_i32(cpu_R
[31], var
, ~3);
571 static inline void store_reg_bx(DisasContext
*s
, int reg
, TCGv var
)
573 store_reg(s
, reg
, var
);
576 static inline TCGv
gen_ld8s(TCGv addr
, int index
)
578 TCGv tmp
= new_tmp();
579 tcg_gen_qemu_ld8s(tmp
, addr
, index
);
583 static inline TCGv
gen_ld8u(TCGv addr
, int index
)
585 TCGv tmp
= new_tmp();
586 tcg_gen_qemu_ld8u(tmp
, addr
, index
);
590 static inline TCGv
gen_ld16s(TCGv addr
, int index
)
592 TCGv tmp
= new_tmp();
593 tcg_gen_qemu_ld16s(tmp
, addr
, index
);
597 static inline TCGv
gen_ld16u(TCGv addr
, int index
)
599 TCGv tmp
= new_tmp();
600 tcg_gen_qemu_ld16u(tmp
, addr
, index
);
604 static inline TCGv
gen_ld32(TCGv addr
, int index
)
606 TCGv tmp
= new_tmp();
607 tcg_gen_qemu_ld32u(tmp
, addr
, index
);
611 static inline TCGv_i64
gen_ld64(TCGv addr
, int index
)
613 TCGv_i64 tmp
= tcg_temp_new_i64();
614 tcg_gen_qemu_ld64(tmp
, addr
, index
);
618 static inline void gen_st8(TCGv val
, TCGv addr
, int index
)
620 tcg_gen_qemu_st8(val
, addr
, index
);
624 static inline void gen_st16(TCGv val
, TCGv addr
, int index
)
626 tcg_gen_qemu_st16(val
, addr
, index
);
630 static inline void gen_st32(TCGv val
, TCGv addr
, int index
)
632 tcg_gen_qemu_st32(val
, addr
, index
);
636 static inline void gen_st64(TCGv_i64 val
, TCGv addr
, int index
)
638 tcg_gen_qemu_st64(val
, addr
, index
);
639 tcg_temp_free_i64(val
);
642 static inline void gen_set_pc_im(uint32_t val
)
644 tcg_gen_movi_i32(cpu_R
[31], val
);
647 /* Force a TB lookup after an instruction that changes the CPU state. */
648 static inline void gen_lookup_tb(DisasContext
*s
)
650 tcg_gen_movi_i32(cpu_R
[31], s
->pc
& ~1);
651 s
->is_jmp
= DISAS_UPDATE
;
654 static inline void gen_add_data_offset(DisasContext
*s
, unsigned int insn
,
667 tcg_gen_addi_i32(var
, var
, val
);
671 offset
= load_reg(s
, UCOP_REG_M
);
672 gen_uc32_shift_im(offset
, UCOP_SH_OP
, UCOP_SH_IM
, 0);
674 tcg_gen_sub_i32(var
, var
, offset
);
676 tcg_gen_add_i32(var
, var
, offset
);
682 static inline void gen_add_datah_offset(DisasContext
*s
, unsigned int insn
,
690 val
= (insn
& 0x1f) | ((insn
>> 4) & 0x3e0);
695 tcg_gen_addi_i32(var
, var
, val
);
699 offset
= load_reg(s
, UCOP_REG_M
);
701 tcg_gen_sub_i32(var
, var
, offset
);
703 tcg_gen_add_i32(var
, var
, offset
);
709 static inline long ucf64_reg_offset(int reg
)
712 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
713 + offsetof(CPU_DoubleU
, l
.upper
);
715 return offsetof(CPUUniCore32State
, ucf64
.regs
[reg
>> 1])
716 + offsetof(CPU_DoubleU
, l
.lower
);
720 #define ucf64_gen_ld32(reg) load_cpu_offset(ucf64_reg_offset(reg))
721 #define ucf64_gen_st32(var, reg) store_cpu_offset(var, ucf64_reg_offset(reg))
723 /* UniCore-F64 single load/store I_offset */
724 static void do_ucf64_ldst_i(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
730 addr
= load_reg(s
, UCOP_REG_N
);
731 if (!UCOP_SET_P
&& !UCOP_SET_W
) {
736 offset
= UCOP_IMM10
<< 2;
741 tcg_gen_addi_i32(addr
, addr
, offset
);
745 if (UCOP_SET_L
) { /* load */
746 tmp
= gen_ld32(addr
, IS_USER(s
));
747 ucf64_gen_st32(tmp
, UCOP_REG_D
);
749 tmp
= ucf64_gen_ld32(UCOP_REG_D
);
750 gen_st32(tmp
, addr
, IS_USER(s
));
754 offset
= UCOP_IMM10
<< 2;
759 tcg_gen_addi_i32(addr
, addr
, offset
);
763 store_reg(s
, UCOP_REG_N
, addr
);
769 /* UniCore-F64 load/store multiple words */
770 static void do_ucf64_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
777 if (UCOP_REG_D
!= 0) {
780 if (UCOP_REG_N
== 31) {
783 if ((insn
<< 24) == 0) {
787 addr
= load_reg(s
, UCOP_REG_N
);
790 for (i
= 0; i
< 8; i
++) {
797 if (UCOP_SET_P
) { /* pre increment */
798 tcg_gen_addi_i32(addr
, addr
, 4);
799 } /* unnecessary to do anything when post increment */
801 if (UCOP_SET_P
) { /* pre decrement */
802 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
803 } else { /* post decrement */
805 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
810 freg
= ((insn
>> 8) & 3) << 3; /* freg should be 0, 8, 16, 24 */
812 for (i
= 0, j
= 0; i
< 8; i
++, freg
++) {
817 if (UCOP_SET_L
) { /* load */
818 tmp
= gen_ld32(addr
, IS_USER(s
));
819 ucf64_gen_st32(tmp
, freg
);
821 tmp
= ucf64_gen_ld32(freg
);
822 gen_st32(tmp
, addr
, IS_USER(s
));
826 /* unnecessary to add after the last transfer */
828 tcg_gen_addi_i32(addr
, addr
, 4);
832 if (UCOP_SET_W
) { /* write back */
834 if (!UCOP_SET_P
) { /* post increment */
835 tcg_gen_addi_i32(addr
, addr
, 4);
836 } /* unnecessary to do anything when pre increment */
841 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
845 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
848 store_reg(s
, UCOP_REG_N
, addr
);
854 /* UniCore-F64 mrc/mcr */
855 static void do_ucf64_trans(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
859 if ((insn
& 0xfe0003ff) == 0xe2000000) {
860 /* control register */
861 if ((UCOP_REG_N
!= UC32_UCF64_FPSCR
) || (UCOP_REG_D
== 31)) {
867 gen_helper_ucf64_get_fpscr(tmp
, cpu_env
);
868 store_reg(s
, UCOP_REG_D
, tmp
);
871 tmp
= load_reg(s
, UCOP_REG_D
);
872 gen_helper_ucf64_set_fpscr(cpu_env
, tmp
);
878 if ((insn
& 0xfe0003ff) == 0xe0000000) {
879 /* general register */
880 if (UCOP_REG_D
== 31) {
883 if (UCOP_SET(24)) { /* MFF */
884 tmp
= ucf64_gen_ld32(UCOP_REG_N
);
885 store_reg(s
, UCOP_REG_D
, tmp
);
887 tmp
= load_reg(s
, UCOP_REG_D
);
888 ucf64_gen_st32(tmp
, UCOP_REG_N
);
892 if ((insn
& 0xfb000000) == 0xe9000000) {
894 if (UCOP_REG_D
!= 31) {
897 if (UCOP_UCF64_COND
& 0x8) {
902 tcg_gen_movi_i32(tmp
, UCOP_UCF64_COND
);
904 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
905 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
906 gen_helper_ucf64_cmpd(cpu_F0d
, cpu_F1d
, tmp
, cpu_env
);
908 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
909 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
910 gen_helper_ucf64_cmps(cpu_F0s
, cpu_F1s
, tmp
, cpu_env
);
918 /* UniCore-F64 convert instructions */
919 static void do_ucf64_fcvt(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
921 if (UCOP_UCF64_FMT
== 3) {
924 if (UCOP_REG_N
!= 0) {
927 switch (UCOP_UCF64_FUNC
) {
929 switch (UCOP_UCF64_FMT
) {
931 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
932 gen_helper_ucf64_df2sf(cpu_F0s
, cpu_F0d
, cpu_env
);
933 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
936 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
937 gen_helper_ucf64_si2sf(cpu_F0s
, cpu_F0s
, cpu_env
);
938 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
946 switch (UCOP_UCF64_FMT
) {
948 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
949 gen_helper_ucf64_sf2df(cpu_F0d
, cpu_F0s
, cpu_env
);
950 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
953 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
954 gen_helper_ucf64_si2df(cpu_F0d
, cpu_F0s
, cpu_env
);
955 tcg_gen_st_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
963 switch (UCOP_UCF64_FMT
) {
965 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
966 gen_helper_ucf64_sf2si(cpu_F0s
, cpu_F0s
, cpu_env
);
967 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
970 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
971 gen_helper_ucf64_df2si(cpu_F0s
, cpu_F0d
, cpu_env
);
972 tcg_gen_st_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_D
));
984 /* UniCore-F64 compare instructions */
985 static void do_ucf64_fcmp(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
990 if (UCOP_REG_D
!= 0) {
996 tcg_gen_ld_i64(cpu_F0d
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
997 tcg_gen_ld_i64(cpu_F1d
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
998 /* gen_helper_ucf64_cmpd(cpu_F0d, cpu_F1d, cpu_env); */
1000 tcg_gen_ld_i32(cpu_F0s
, cpu_env
, ucf64_reg_offset(UCOP_REG_N
));
1001 tcg_gen_ld_i32(cpu_F1s
, cpu_env
, ucf64_reg_offset(UCOP_REG_M
));
1002 /* gen_helper_ucf64_cmps(cpu_F0s, cpu_F1s, cpu_env); */
1006 #define gen_helper_ucf64_movs(x, y) do { } while (0)
1007 #define gen_helper_ucf64_movd(x, y) do { } while (0)
1009 #define UCF64_OP1(name) do { \
1010 if (UCOP_REG_N != 0) { \
1013 switch (UCOP_UCF64_FMT) { \
1015 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1016 ucf64_reg_offset(UCOP_REG_M)); \
1017 gen_helper_ucf64_##name##s(cpu_F0s, cpu_F0s); \
1018 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1019 ucf64_reg_offset(UCOP_REG_D)); \
1022 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1023 ucf64_reg_offset(UCOP_REG_M)); \
1024 gen_helper_ucf64_##name##d(cpu_F0d, cpu_F0d); \
1025 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1026 ucf64_reg_offset(UCOP_REG_D)); \
1034 #define UCF64_OP2(name) do { \
1035 switch (UCOP_UCF64_FMT) { \
1037 tcg_gen_ld_i32(cpu_F0s, cpu_env, \
1038 ucf64_reg_offset(UCOP_REG_N)); \
1039 tcg_gen_ld_i32(cpu_F1s, cpu_env, \
1040 ucf64_reg_offset(UCOP_REG_M)); \
1041 gen_helper_ucf64_##name##s(cpu_F0s, \
1042 cpu_F0s, cpu_F1s, cpu_env); \
1043 tcg_gen_st_i32(cpu_F0s, cpu_env, \
1044 ucf64_reg_offset(UCOP_REG_D)); \
1047 tcg_gen_ld_i64(cpu_F0d, cpu_env, \
1048 ucf64_reg_offset(UCOP_REG_N)); \
1049 tcg_gen_ld_i64(cpu_F1d, cpu_env, \
1050 ucf64_reg_offset(UCOP_REG_M)); \
1051 gen_helper_ucf64_##name##d(cpu_F0d, \
1052 cpu_F0d, cpu_F1d, cpu_env); \
1053 tcg_gen_st_i64(cpu_F0d, cpu_env, \
1054 ucf64_reg_offset(UCOP_REG_D)); \
1062 /* UniCore-F64 data processing */
1063 static void do_ucf64_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1065 if (UCOP_UCF64_FMT
== 3) {
1068 switch (UCOP_UCF64_FUNC
) {
1095 /* Disassemble an F64 instruction */
1096 static void disas_ucf64_insn(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1098 if (!UCOP_SET(29)) {
1100 do_ucf64_ldst_m(env
, s
, insn
);
1102 do_ucf64_ldst_i(env
, s
, insn
);
1106 switch ((insn
>> 26) & 0x3) {
1108 do_ucf64_datap(env
, s
, insn
);
1114 do_ucf64_fcvt(env
, s
, insn
);
1117 do_ucf64_fcmp(env
, s
, insn
);
1121 do_ucf64_trans(env
, s
, insn
);
1126 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint32_t dest
)
1128 TranslationBlock
*tb
;
1131 if ((tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
)) {
1133 gen_set_pc_im(dest
);
1134 tcg_gen_exit_tb((tcg_target_long
)tb
+ n
);
1136 gen_set_pc_im(dest
);
1141 static inline void gen_jmp(DisasContext
*s
, uint32_t dest
)
1143 if (unlikely(s
->singlestep_enabled
)) {
1144 /* An indirect jump so that we still trigger the debug exception. */
1147 gen_goto_tb(s
, 0, dest
);
1148 s
->is_jmp
= DISAS_TB_JUMP
;
1152 static inline void gen_mulxy(TCGv t0
, TCGv t1
, int x
, int y
)
1155 tcg_gen_sari_i32(t0
, t0
, 16);
1160 tcg_gen_sari_i32(t1
, t1
, 16);
1164 tcg_gen_mul_i32(t0
, t0
, t1
);
1167 /* Returns nonzero if access to the PSR is not permitted. Marks t0 as dead. */
1168 static int gen_set_psr(DisasContext
*s
, uint32_t mask
, int bsr
, TCGv t0
)
1172 /* ??? This is also undefined in system mode. */
1177 tmp
= load_cpu_field(bsr
);
1178 tcg_gen_andi_i32(tmp
, tmp
, ~mask
);
1179 tcg_gen_andi_i32(t0
, t0
, mask
);
1180 tcg_gen_or_i32(tmp
, tmp
, t0
);
1181 store_cpu_field(tmp
, bsr
);
1183 gen_set_asr(t0
, mask
);
1190 /* Generate an old-style exception return. Marks pc as dead. */
1191 static void gen_exception_return(DisasContext
*s
, TCGv pc
)
1194 store_reg(s
, 31, pc
);
1195 tmp
= load_cpu_field(bsr
);
1196 gen_set_asr(tmp
, 0xffffffff);
1198 s
->is_jmp
= DISAS_UPDATE
;
1201 static void disas_coproc_insn(CPUUniCore32State
*env
, DisasContext
*s
,
1204 switch (UCOP_CPNUM
) {
1205 #ifndef CONFIG_USER_ONLY
1207 disas_cp0_insn(env
, s
, insn
);
1210 disas_ocd_insn(env
, s
, insn
);
1214 disas_ucf64_insn(env
, s
, insn
);
1217 /* Unknown coprocessor. */
1218 cpu_abort(env
, "Unknown coprocessor!");
1223 /* Store a 64-bit value to a register pair. Clobbers val. */
1224 static void gen_storeq_reg(DisasContext
*s
, int rlow
, int rhigh
, TCGv_i64 val
)
1228 tcg_gen_trunc_i64_i32(tmp
, val
);
1229 store_reg(s
, rlow
, tmp
);
1231 tcg_gen_shri_i64(val
, val
, 32);
1232 tcg_gen_trunc_i64_i32(tmp
, val
);
1233 store_reg(s
, rhigh
, tmp
);
1236 /* load and add a 64-bit value from a register pair. */
1237 static void gen_addq(DisasContext
*s
, TCGv_i64 val
, int rlow
, int rhigh
)
1243 /* Load 64-bit value rd:rn. */
1244 tmpl
= load_reg(s
, rlow
);
1245 tmph
= load_reg(s
, rhigh
);
1246 tmp
= tcg_temp_new_i64();
1247 tcg_gen_concat_i32_i64(tmp
, tmpl
, tmph
);
1250 tcg_gen_add_i64(val
, val
, tmp
);
1251 tcg_temp_free_i64(tmp
);
1254 /* data processing instructions */
1255 static void do_datap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1261 if (UCOP_OPCODES
== 0x0f || UCOP_OPCODES
== 0x0d) {
1262 if (UCOP_SET(23)) { /* CMOV instructions */
1263 if ((UCOP_CMOV_COND
== 0xe) || (UCOP_CMOV_COND
== 0xf)) {
1266 /* if not always execute, we generate a conditional jump to
1268 s
->condlabel
= gen_new_label();
1269 gen_test_cc(UCOP_CMOV_COND
^ 1, s
->condlabel
);
1274 logic_cc
= table_logic_cc
[UCOP_OPCODES
] & (UCOP_SET_S
>> 24);
1278 /* immediate operand */
1281 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1284 tcg_gen_movi_i32(tmp2
, val
);
1285 if (logic_cc
&& UCOP_SH_IM
) {
1286 gen_set_CF_bit31(tmp2
);
1290 tmp2
= load_reg(s
, UCOP_REG_M
);
1292 tmp
= load_reg(s
, UCOP_REG_S
);
1293 gen_uc32_shift_reg(tmp2
, UCOP_SH_OP
, tmp
, logic_cc
);
1295 gen_uc32_shift_im(tmp2
, UCOP_SH_OP
, UCOP_SH_IM
, logic_cc
);
1299 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1300 tmp
= load_reg(s
, UCOP_REG_N
);
1305 switch (UCOP_OPCODES
) {
1307 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1311 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1314 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1318 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1321 if (UCOP_SET_S
&& UCOP_REG_D
== 31) {
1322 /* SUBS r31, ... is used for exception return. */
1326 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1327 gen_exception_return(s
, tmp
);
1330 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1332 tcg_gen_sub_i32(tmp
, tmp
, tmp2
);
1334 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1339 gen_helper_sub_cc(tmp
, cpu_env
, tmp2
, tmp
);
1341 tcg_gen_sub_i32(tmp
, tmp2
, tmp
);
1343 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1347 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1349 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1351 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1355 gen_helper_adc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1357 gen_add_carry(tmp
, tmp
, tmp2
);
1359 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1363 gen_helper_sbc_cc(tmp
, cpu_env
, tmp
, tmp2
);
1365 gen_sub_carry(tmp
, tmp
, tmp2
);
1367 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1371 gen_helper_sbc_cc(tmp
, cpu_env
, tmp2
, tmp
);
1373 gen_sub_carry(tmp
, tmp2
, tmp
);
1375 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1379 tcg_gen_and_i32(tmp
, tmp
, tmp2
);
1386 tcg_gen_xor_i32(tmp
, tmp
, tmp2
);
1393 gen_helper_sub_cc(tmp
, cpu_env
, tmp
, tmp2
);
1399 gen_helper_add_cc(tmp
, cpu_env
, tmp
, tmp2
);
1404 tcg_gen_or_i32(tmp
, tmp
, tmp2
);
1408 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1411 if (logic_cc
&& UCOP_REG_D
== 31) {
1412 /* MOVS r31, ... is used for exception return. */
1416 gen_exception_return(s
, tmp2
);
1421 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1425 tcg_gen_andc_i32(tmp
, tmp
, tmp2
);
1429 store_reg_bx(s
, UCOP_REG_D
, tmp
);
1433 tcg_gen_not_i32(tmp2
, tmp2
);
1437 store_reg_bx(s
, UCOP_REG_D
, tmp2
);
1440 if (UCOP_OPCODES
!= 0x0f && UCOP_OPCODES
!= 0x0d) {
1446 static void do_mult(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1454 tmp
= load_reg(s
, UCOP_REG_M
);
1455 tmp2
= load_reg(s
, UCOP_REG_N
);
1457 tmp64
= gen_muls_i64_i32(tmp
, tmp2
);
1459 tmp64
= gen_mulu_i64_i32(tmp
, tmp2
);
1461 if (UCOP_SET(25)) { /* mult accumulate */
1462 gen_addq(s
, tmp64
, UCOP_REG_LO
, UCOP_REG_HI
);
1464 gen_storeq_reg(s
, UCOP_REG_LO
, UCOP_REG_HI
, tmp64
);
1465 tcg_temp_free_i64(tmp64
);
1468 tmp
= load_reg(s
, UCOP_REG_M
);
1469 tmp2
= load_reg(s
, UCOP_REG_N
);
1470 tcg_gen_mul_i32(tmp
, tmp
, tmp2
);
1474 tmp2
= load_reg(s
, UCOP_REG_S
);
1475 tcg_gen_add_i32(tmp
, tmp
, tmp2
);
1481 store_reg(s
, UCOP_REG_D
, tmp
);
1485 /* miscellaneous instructions */
1486 static void do_misc(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1491 if ((insn
& 0xffffffe0) == 0x10ffc120) {
1492 /* Trivial implementation equivalent to bx. */
1493 tmp
= load_reg(s
, UCOP_REG_M
);
1498 if ((insn
& 0xfbffc000) == 0x30ffc000) {
1499 /* PSR = immediate */
1502 val
= (val
>> UCOP_SH_IM
) | (val
<< (32 - UCOP_SH_IM
));
1505 tcg_gen_movi_i32(tmp
, val
);
1506 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1512 if ((insn
& 0xfbffffe0) == 0x12ffc020) {
1513 /* PSR.flag = reg */
1514 tmp
= load_reg(s
, UCOP_REG_M
);
1515 if (gen_set_psr(s
, ASR_NZCV
, UCOP_SET_B
, tmp
)) {
1521 if ((insn
& 0xfbffffe0) == 0x10ffc020) {
1523 tmp
= load_reg(s
, UCOP_REG_M
);
1524 if (gen_set_psr(s
, ~ASR_RESERVED
, UCOP_SET_B
, tmp
)) {
1530 if ((insn
& 0xfbf83fff) == 0x10f80000) {
1536 tmp
= load_cpu_field(bsr
);
1539 gen_helper_asr_read(tmp
, cpu_env
);
1541 store_reg(s
, UCOP_REG_D
, tmp
);
1545 if ((insn
& 0xfbf83fe0) == 0x12f80120) {
1547 tmp
= load_reg(s
, UCOP_REG_M
);
1549 gen_helper_clo(tmp
, tmp
);
1551 gen_helper_clz(tmp
, tmp
);
1553 store_reg(s
, UCOP_REG_D
, tmp
);
1561 /* load/store I_offset and R_offset */
1562 static void do_ldst_ir(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1564 unsigned int mmu_idx
;
1568 tmp2
= load_reg(s
, UCOP_REG_N
);
1569 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1573 gen_add_data_offset(s
, insn
, tmp2
);
1579 tmp
= gen_ld8u(tmp2
, mmu_idx
);
1581 tmp
= gen_ld32(tmp2
, mmu_idx
);
1585 tmp
= load_reg(s
, UCOP_REG_D
);
1587 gen_st8(tmp
, tmp2
, mmu_idx
);
1589 gen_st32(tmp
, tmp2
, mmu_idx
);
1593 gen_add_data_offset(s
, insn
, tmp2
);
1594 store_reg(s
, UCOP_REG_N
, tmp2
);
1595 } else if (UCOP_SET_W
) {
1596 store_reg(s
, UCOP_REG_N
, tmp2
);
1601 /* Complete the load. */
1602 if (UCOP_REG_D
== 31) {
1605 store_reg(s
, UCOP_REG_D
, tmp
);
1610 /* SWP instruction */
1611 static void do_swap(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1617 if ((insn
& 0xff003fe0) != 0x40000120) {
1621 /* ??? This is not really atomic. However we know
1622 we never have multiple CPUs running in parallel,
1623 so it is good enough. */
1624 addr
= load_reg(s
, UCOP_REG_N
);
1625 tmp
= load_reg(s
, UCOP_REG_M
);
1627 tmp2
= gen_ld8u(addr
, IS_USER(s
));
1628 gen_st8(tmp
, addr
, IS_USER(s
));
1630 tmp2
= gen_ld32(addr
, IS_USER(s
));
1631 gen_st32(tmp
, addr
, IS_USER(s
));
1634 store_reg(s
, UCOP_REG_D
, tmp2
);
1637 /* load/store hw/sb */
1638 static void do_ldst_hwsb(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1643 if (UCOP_SH_OP
== 0) {
1644 do_swap(env
, s
, insn
);
1648 addr
= load_reg(s
, UCOP_REG_N
);
1650 gen_add_datah_offset(s
, insn
, addr
);
1653 if (UCOP_SET_L
) { /* load */
1654 switch (UCOP_SH_OP
) {
1656 tmp
= gen_ld16u(addr
, IS_USER(s
));
1659 tmp
= gen_ld8s(addr
, IS_USER(s
));
1661 default: /* see do_swap */
1663 tmp
= gen_ld16s(addr
, IS_USER(s
));
1666 } else { /* store */
1667 if (UCOP_SH_OP
!= 1) {
1670 tmp
= load_reg(s
, UCOP_REG_D
);
1671 gen_st16(tmp
, addr
, IS_USER(s
));
1673 /* Perform base writeback before the loaded value to
1674 ensure correct behavior with overlapping index registers. */
1676 gen_add_datah_offset(s
, insn
, addr
);
1677 store_reg(s
, UCOP_REG_N
, addr
);
1678 } else if (UCOP_SET_W
) {
1679 store_reg(s
, UCOP_REG_N
, addr
);
1684 /* Complete the load. */
1685 store_reg(s
, UCOP_REG_D
, tmp
);
1689 /* load/store multiple words */
1690 static void do_ldst_m(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1692 unsigned int val
, i
, mmu_idx
;
1693 int j
, n
, reg
, user
, loaded_base
;
1702 /* XXX: store correct base if write back */
1704 if (UCOP_SET_B
) { /* S bit in instruction table */
1706 ILLEGAL
; /* only usable in supervisor mode */
1708 if (UCOP_SET(18) == 0) { /* pc reg */
1713 mmu_idx
= (IS_USER(s
) || (!UCOP_SET_P
&& UCOP_SET_W
));
1714 addr
= load_reg(s
, UCOP_REG_N
);
1716 /* compute total size */
1718 TCGV_UNUSED(loaded_var
);
1720 for (i
= 0; i
< 6; i
++) {
1725 for (i
= 9; i
< 19; i
++) {
1730 /* XXX: test invalid n == 0 case ? */
1734 tcg_gen_addi_i32(addr
, addr
, 4);
1736 /* post increment */
1741 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1743 /* post decrement */
1745 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1751 reg
= UCOP_SET(6) ? 16 : 0;
1752 for (i
= 0; i
< 19; i
++, reg
++) {
1757 if (UCOP_SET_L
) { /* load */
1758 tmp
= gen_ld32(addr
, mmu_idx
);
1762 tmp2
= tcg_const_i32(reg
);
1763 gen_helper_set_user_reg(cpu_env
, tmp2
, tmp
);
1764 tcg_temp_free_i32(tmp2
);
1766 } else if (reg
== UCOP_REG_N
) {
1770 store_reg(s
, reg
, tmp
);
1772 } else { /* store */
1774 /* special case: r31 = PC + 4 */
1777 tcg_gen_movi_i32(tmp
, val
);
1780 tmp2
= tcg_const_i32(reg
);
1781 gen_helper_get_user_reg(tmp
, cpu_env
, tmp2
);
1782 tcg_temp_free_i32(tmp2
);
1784 tmp
= load_reg(s
, reg
);
1786 gen_st32(tmp
, addr
, mmu_idx
);
1789 /* no need to add after the last transfer */
1791 tcg_gen_addi_i32(addr
, addr
, 4);
1795 if (UCOP_SET_W
) { /* write back */
1800 /* post increment */
1801 tcg_gen_addi_i32(addr
, addr
, 4);
1807 tcg_gen_addi_i32(addr
, addr
, -((n
- 1) * 4));
1810 /* post decrement */
1811 tcg_gen_addi_i32(addr
, addr
, -(n
* 4));
1814 store_reg(s
, UCOP_REG_N
, addr
);
1819 store_reg(s
, UCOP_REG_N
, loaded_var
);
1821 if (UCOP_SET_B
&& !user
) {
1822 /* Restore ASR from BSR. */
1823 tmp
= load_cpu_field(bsr
);
1824 gen_set_asr(tmp
, 0xffffffff);
1826 s
->is_jmp
= DISAS_UPDATE
;
1830 /* branch (and link) */
1831 static void do_branch(CPUUniCore32State
*env
, DisasContext
*s
, uint32_t insn
)
1837 if (UCOP_COND
== 0xf) {
1841 if (UCOP_COND
!= 0xe) {
1842 /* if not always execute, we generate a conditional jump to
1844 s
->condlabel
= gen_new_label();
1845 gen_test_cc(UCOP_COND
^ 1, s
->condlabel
);
1849 val
= (int32_t)s
->pc
;
1852 tcg_gen_movi_i32(tmp
, val
);
1853 store_reg(s
, 30, tmp
);
1855 offset
= (((int32_t)insn
<< 8) >> 8);
1856 val
+= (offset
<< 2); /* unicore is pc+4 */
1860 static void disas_uc32_insn(CPUUniCore32State
*env
, DisasContext
*s
)
1864 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP
| CPU_LOG_TB_OP_OPT
))) {
1865 tcg_gen_debug_insn_start(s
->pc
);
1868 insn
= cpu_ldl_code(env
, s
->pc
);
1871 /* UniCore instructions class:
1872 * AAAB BBBC xxxx xxxx xxxx xxxD xxEx xxxx
1873 * AAA : see switch case
1874 * BBBB : opcodes or cond or PUBW
1879 switch (insn
>> 29) {
1881 if (UCOP_SET(5) && UCOP_SET(8) && !UCOP_SET(28)) {
1882 do_mult(env
, s
, insn
);
1887 do_misc(env
, s
, insn
);
1891 if (((UCOP_OPCODES
>> 2) == 2) && !UCOP_SET_S
) {
1892 do_misc(env
, s
, insn
);
1895 do_datap(env
, s
, insn
);
1899 if (UCOP_SET(8) && UCOP_SET(5)) {
1900 do_ldst_hwsb(env
, s
, insn
);
1903 if (UCOP_SET(8) || UCOP_SET(5)) {
1907 do_ldst_ir(env
, s
, insn
);
1912 ILLEGAL
; /* extended instructions */
1914 do_ldst_m(env
, s
, insn
);
1917 do_branch(env
, s
, insn
);
1921 disas_coproc_insn(env
, s
, insn
);
1924 if (!UCOP_SET(28)) {
1925 disas_coproc_insn(env
, s
, insn
);
1928 if ((insn
& 0xff000000) == 0xff000000) { /* syscall */
1929 gen_set_pc_im(s
->pc
);
1930 s
->is_jmp
= DISAS_SYSCALL
;
1937 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
1938 basic block 'tb'. If search_pc is TRUE, also generate PC
1939 information for each intermediate instruction. */
1940 static inline void gen_intermediate_code_internal(CPUUniCore32State
*env
,
1941 TranslationBlock
*tb
, int search_pc
)
1943 DisasContext dc1
, *dc
= &dc1
;
1945 uint16_t *gen_opc_end
;
1947 target_ulong pc_start
;
1948 uint32_t next_page_start
;
1952 /* generate intermediate code */
1959 gen_opc_end
= gen_opc_buf
+ OPC_MAX_SIZE
;
1961 dc
->is_jmp
= DISAS_NEXT
;
1963 dc
->singlestep_enabled
= env
->singlestep_enabled
;
1965 cpu_F0s
= tcg_temp_new_i32();
1966 cpu_F1s
= tcg_temp_new_i32();
1967 cpu_F0d
= tcg_temp_new_i64();
1968 cpu_F1d
= tcg_temp_new_i64();
1969 next_page_start
= (pc_start
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
1972 max_insns
= tb
->cflags
& CF_COUNT_MASK
;
1973 if (max_insns
== 0) {
1974 max_insns
= CF_COUNT_MASK
;
1977 #ifndef CONFIG_USER_ONLY
1978 if ((env
->uncached_asr
& ASR_M
) == ASR_MODE_USER
) {
1987 if (unlikely(!QTAILQ_EMPTY(&env
->breakpoints
))) {
1988 QTAILQ_FOREACH(bp
, &env
->breakpoints
, entry
) {
1989 if (bp
->pc
== dc
->pc
) {
1990 gen_set_pc_im(dc
->pc
);
1991 gen_exception(EXCP_DEBUG
);
1992 dc
->is_jmp
= DISAS_JUMP
;
1993 /* Advance PC so that clearing the breakpoint will
1994 invalidate this TB. */
1995 dc
->pc
+= 2; /* FIXME */
1996 goto done_generating
;
2002 j
= gen_opc_ptr
- gen_opc_buf
;
2006 gen_opc_instr_start
[lj
++] = 0;
2009 gen_opc_pc
[lj
] = dc
->pc
;
2010 gen_opc_instr_start
[lj
] = 1;
2011 gen_opc_icount
[lj
] = num_insns
;
2014 if (num_insns
+ 1 == max_insns
&& (tb
->cflags
& CF_LAST_IO
)) {
2018 disas_uc32_insn(env
, dc
);
2021 fprintf(stderr
, "Internal resource leak before %08x\n", dc
->pc
);
2025 if (dc
->condjmp
&& !dc
->is_jmp
) {
2026 gen_set_label(dc
->condlabel
);
2029 /* Translation stops when a conditional branch is encountered.
2030 * Otherwise the subsequent code could get translated several times.
2031 * Also stop translation when a page boundary is reached. This
2032 * ensures prefetch aborts occur at the right place. */
2034 } while (!dc
->is_jmp
&& gen_opc_ptr
< gen_opc_end
&&
2035 !env
->singlestep_enabled
&&
2037 dc
->pc
< next_page_start
&&
2038 num_insns
< max_insns
);
2040 if (tb
->cflags
& CF_LAST_IO
) {
2042 /* FIXME: This can theoretically happen with self-modifying
2044 cpu_abort(env
, "IO on conditional branch instruction");
2049 /* At this stage dc->condjmp will only be set when the skipped
2050 instruction was a conditional branch or trap, and the PC has
2051 already been written. */
2052 if (unlikely(env
->singlestep_enabled
)) {
2053 /* Make sure the pc is updated, and raise a debug exception. */
2055 if (dc
->is_jmp
== DISAS_SYSCALL
) {
2056 gen_exception(UC32_EXCP_PRIV
);
2058 gen_exception(EXCP_DEBUG
);
2060 gen_set_label(dc
->condlabel
);
2062 if (dc
->condjmp
|| !dc
->is_jmp
) {
2063 gen_set_pc_im(dc
->pc
);
2066 if (dc
->is_jmp
== DISAS_SYSCALL
&& !dc
->condjmp
) {
2067 gen_exception(UC32_EXCP_PRIV
);
2069 gen_exception(EXCP_DEBUG
);
2072 /* While branches must always occur at the end of an IT block,
2073 there are a few other things that can cause us to terminate
2074 the TB in the middel of an IT block:
2075 - Exception generating instructions (bkpt, swi, undefined).
2077 - Hardware watchpoints.
2078 Hardware breakpoints have already been handled and skip this code.
2080 switch (dc
->is_jmp
) {
2082 gen_goto_tb(dc
, 1, dc
->pc
);
2087 /* indicate that the hash table must be used to find the next TB */
2091 /* nothing more to generate */
2094 gen_exception(UC32_EXCP_PRIV
);
2098 gen_set_label(dc
->condlabel
);
2099 gen_goto_tb(dc
, 1, dc
->pc
);
2105 gen_icount_end(tb
, num_insns
);
2106 *gen_opc_ptr
= INDEX_op_end
;
2109 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM
)) {
2110 qemu_log("----------------\n");
2111 qemu_log("IN: %s\n", lookup_symbol(pc_start
));
2112 log_target_disas(pc_start
, dc
->pc
- pc_start
, 0);
2117 j
= gen_opc_ptr
- gen_opc_buf
;
2120 gen_opc_instr_start
[lj
++] = 0;
2123 tb
->size
= dc
->pc
- pc_start
;
2124 tb
->icount
= num_insns
;
2128 void gen_intermediate_code(CPUUniCore32State
*env
, TranslationBlock
*tb
)
2130 gen_intermediate_code_internal(env
, tb
, 0);
2133 void gen_intermediate_code_pc(CPUUniCore32State
*env
, TranslationBlock
*tb
)
2135 gen_intermediate_code_internal(env
, tb
, 1);
2138 static const char *cpu_mode_names
[16] = {
2139 "USER", "REAL", "INTR", "PRIV", "UM14", "UM15", "UM16", "TRAP",
2140 "UM18", "UM19", "UM1A", "EXTN", "UM1C", "UM1D", "UM1E", "SUSR"
2143 #undef UCF64_DUMP_STATE
2144 #ifdef UCF64_DUMP_STATE
2145 static void cpu_dump_state_ucf64(CPUUniCore32State
*env
, FILE *f
,
2146 fprintf_function cpu_fprintf
, int flags
)
2154 /* ??? This assumes float64 and double have the same layout.
2155 Oh well, it's only debug dumps. */
2161 for (i
= 0; i
< 16; i
++) {
2162 d
.d
= env
->ucf64
.regs
[i
];
2166 cpu_fprintf(f
, "s%02d=%08x(%8g) s%02d=%08x(%8g)",
2167 i
* 2, (int)s0
.i
, s0
.s
,
2168 i
* 2 + 1, (int)s1
.i
, s1
.s
);
2169 cpu_fprintf(f
, " d%02d=%" PRIx64
"(%8g)\n",
2170 i
, (uint64_t)d0
.f64
, d0
.d
);
2172 cpu_fprintf(f
, "FPSCR: %08x\n", (int)env
->ucf64
.xregs
[UC32_UCF64_FPSCR
]);
2175 #define cpu_dump_state_ucf64(env, file, pr, flags) do { } while (0)
2178 void cpu_dump_state(CPUUniCore32State
*env
, FILE *f
,
2179 fprintf_function cpu_fprintf
, int flags
)
2184 for (i
= 0; i
< 32; i
++) {
2185 cpu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
2187 cpu_fprintf(f
, "\n");
2189 cpu_fprintf(f
, " ");
2192 psr
= cpu_asr_read(env
);
2193 cpu_fprintf(f
, "PSR=%08x %c%c%c%c %s\n",
2195 psr
& (1 << 31) ? 'N' : '-',
2196 psr
& (1 << 30) ? 'Z' : '-',
2197 psr
& (1 << 29) ? 'C' : '-',
2198 psr
& (1 << 28) ? 'V' : '-',
2199 cpu_mode_names
[psr
& 0xf]);
2201 cpu_dump_state_ucf64(env
, f
, cpu_fprintf
, flags
);
2204 void restore_state_to_opc(CPUUniCore32State
*env
, TranslationBlock
*tb
, int pc_pos
)
2206 env
->regs
[31] = gen_opc_pc
[pc_pos
];