hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "ioapic.h"
  27 #include "qemu-timer.h"
  28 #include "host-utils.h"
  29 #include "sysbus.h"
  30
  31 //#define DEBUG_IOAPIC
  32
  33 #ifdef DEBUG_IOAPIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define MAX_IOAPICS                     1
  41
  42 #define IOAPIC_VERSION                  0x11
  43
  44 #define IOAPIC_LVT_DEST_SHIFT           56
  45 #define IOAPIC_LVT_MASKED_SHIFT         16
  46 #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
  47 #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
  48 #define IOAPIC_LVT_POLARITY_SHIFT       13
  49 #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
  50 #define IOAPIC_LVT_DEST_MODE_SHIFT      11
  51 #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
  52
  53 #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
  54 #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
  55
  56 #define IOAPIC_TRIGGER_EDGE             0
  57 #define IOAPIC_TRIGGER_LEVEL            1
  58
  59 /*io{apic,sapic} delivery mode*/
  60 #define IOAPIC_DM_FIXED                 0x0
  61 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  62 #define IOAPIC_DM_PMI                   0x2
  63 #define IOAPIC_DM_NMI                   0x4
  64 #define IOAPIC_DM_INIT                  0x5
  65 #define IOAPIC_DM_SIPI                  0x6
  66 #define IOAPIC_DM_EXTINT                0x7
  67 #define IOAPIC_DM_MASK                  0x7
  68
  69 #define IOAPIC_VECTOR_MASK              0xff
  70
  71 #define IOAPIC_IOREGSEL                 0x00
  72 #define IOAPIC_IOWIN                    0x10
  73
  74 #define IOAPIC_REG_ID                   0x00
  75 #define IOAPIC_REG_VER                  0x01
  76 #define IOAPIC_REG_ARB                  0x02
  77 #define IOAPIC_REG_REDTBL_BASE          0x10
  78 #define IOAPIC_ID                       0x00
  79
  80 #define IOAPIC_ID_SHIFT                 24
  81 #define IOAPIC_ID_MASK                  0xf
  82
  83 #define IOAPIC_VER_ENTRIES_SHIFT        16
  84
  85 typedef struct IOAPICState IOAPICState;
  86
  87 struct IOAPICState {
  88     SysBusDevice busdev;
  89     MemoryRegion io_memory;
  90     uint8_t id;
  91     uint8_t ioregsel;
  92     uint32_t irr;
  93     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  94 };
  95
  96 static IOAPICState *ioapics[MAX_IOAPICS];
  97
  98 static void ioapic_service(IOAPICState *s)
  99 {
 100     uint8_t i;
 101     uint8_t trig_mode;
 102     uint8_t vector;
 103     uint8_t delivery_mode;
 104     uint32_t mask;
 105     uint64_t entry;
 106     uint8_t dest;
 107     uint8_t dest_mode;
 108
 109     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 110         mask = 1 << i;
 111         if (s->irr & mask) {
 112             entry = s->ioredtbl[i];
 113             if (!(entry & IOAPIC_LVT_MASKED)) {
 114                 trig_mode = ((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1);
 115                 dest = entry >> IOAPIC_LVT_DEST_SHIFT;
 116                 dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
 117                 delivery_mode =
 118                     (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) & IOAPIC_DM_MASK;
 119                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
 120                     s->irr &= ~mask;
 121                 } else {
 122                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 123                 }
 124                 if (delivery_mode == IOAPIC_DM_EXTINT) {
 125                     vector = pic_read_irq(isa_pic);
 126                 } else {
 127                     vector = entry & IOAPIC_VECTOR_MASK;
 128                 }
 129                 apic_deliver_irq(dest, dest_mode, delivery_mode,
 130                                  vector, trig_mode);
 131             }
 132         }
 133     }
 134 }
 135
 136 static void ioapic_set_irq(void *opaque, int vector, int level)
 137 {
 138     IOAPICState *s = opaque;
 139
 140     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 141      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 142      * the cleanest way of doing it but it should work. */
 143
 144     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 145     if (vector == 0) {
 146         vector = 2;
 147     }
 148     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 149         uint32_t mask = 1 << vector;
 150         uint64_t entry = s->ioredtbl[vector];
 151
 152         if (entry & (1 << IOAPIC_LVT_POLARITY_SHIFT)) {
 153             level = !level;
 154         }
 155         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 156             IOAPIC_TRIGGER_LEVEL) {
 157             /* level triggered */
 158             if (level) {
 159                 s->irr |= mask;
 160                 ioapic_service(s);
 161             } else {
 162                 s->irr &= ~mask;
 163             }
 164         } else {
 165             /* According to the 82093AA manual, we must ignore edge requests
 166              * if the input pin is masked. */
 167             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 168                 s->irr |= mask;
 169                 ioapic_service(s);
 170             }
 171         }
 172     }
 173 }
 174
 175 void ioapic_eoi_broadcast(int vector)
 176 {
 177     IOAPICState *s;
 178     uint64_t entry;
 179     int i, n;
 180
 181     for (i = 0; i < MAX_IOAPICS; i++) {
 182         s = ioapics[i];
 183         if (!s) {
 184             continue;
 185         }
 186         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 187             entry = s->ioredtbl[n];
 188             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 189                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 190                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 191                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 192                     ioapic_service(s);
 193                 }
 194             }
 195         }
 196     }
 197 }
 198
 199 static uint64_t
 200 ioapic_mem_read(void *opaque, target_phys_addr_t addr, unsigned int size)
 201 {
 202     IOAPICState *s = opaque;
 203     int index;
 204     uint32_t val = 0;
 205
 206     switch (addr & 0xff) {
 207     case IOAPIC_IOREGSEL:
 208         val = s->ioregsel;
 209         break;
 210     case IOAPIC_IOWIN:
 211         if (size != 4) {
 212             break;
 213         }
 214         switch (s->ioregsel) {
 215         case IOAPIC_REG_ID:
 216             val = s->id << IOAPIC_ID_SHIFT;
 217             break;
 218         case IOAPIC_REG_VER:
 219             val = IOAPIC_VERSION |
 220                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 221             break;
 222         case IOAPIC_REG_ARB:
 223             val = 0;
 224             break;
 225         default:
 226             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 227             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 228                 if (s->ioregsel & 1) {
 229                     val = s->ioredtbl[index] >> 32;
 230                 } else {
 231                     val = s->ioredtbl[index] & 0xffffffff;
 232                 }
 233             }
 234         }
 235         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 236         break;
 237     }
 238     return val;
 239 }
 240
 241 static void
 242 ioapic_mem_write(void *opaque, target_phys_addr_t addr, uint64_t val,
 243                  unsigned int size)
 244 {
 245     IOAPICState *s = opaque;
 246     int index;
 247
 248     switch (addr & 0xff) {
 249     case IOAPIC_IOREGSEL:
 250         s->ioregsel = val;
 251         break;
 252     case IOAPIC_IOWIN:
 253         if (size != 4) {
 254             break;
 255         }
 256         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 257         switch (s->ioregsel) {
 258         case IOAPIC_REG_ID:
 259             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 260             break;
 261         case IOAPIC_REG_VER:
 262         case IOAPIC_REG_ARB:
 263             break;
 264         default:
 265             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 266             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 267                 if (s->ioregsel & 1) {
 268                     s->ioredtbl[index] &= 0xffffffff;
 269                     s->ioredtbl[index] |= (uint64_t)val << 32;
 270                 } else {
 271                     s->ioredtbl[index] &= ~0xffffffffULL;
 272                     s->ioredtbl[index] |= val;
 273                 }
 274                 ioapic_service(s);
 275             }
 276         }
 277         break;
 278     }
 279 }
 280
 281 static int ioapic_post_load(void *opaque, int version_id)
 282 {
 283     IOAPICState *s = opaque;
 284
 285     if (version_id == 1) {
 286         /* set sane value */
 287         s->irr = 0;
 288     }
 289     return 0;
 290 }
 291
 292 static const VMStateDescription vmstate_ioapic = {
 293     .name = "ioapic",
 294     .version_id = 3,
 295     .post_load = ioapic_post_load,
 296     .minimum_version_id = 1,
 297     .minimum_version_id_old = 1,
 298     .fields = (VMStateField[]) {
 299         VMSTATE_UINT8(id, IOAPICState),
 300         VMSTATE_UINT8(ioregsel, IOAPICState),
 301         VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
 302         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 303         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static void ioapic_reset(DeviceState *d)
 309 {
 310     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 311     int i;
 312
 313     s->id = 0;
 314     s->ioregsel = 0;
 315     s->irr = 0;
 316     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 317         s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
 318     }
 319 }
 320
 321 static const MemoryRegionOps ioapic_io_ops = {
 322     .read = ioapic_mem_read,
 323     .write = ioapic_mem_write,
 324     .endianness = DEVICE_NATIVE_ENDIAN,
 325 };
 326
 327 static int ioapic_init1(SysBusDevice *dev)
 328 {
 329     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 330     static int ioapic_no;
 331
 332     if (ioapic_no >= MAX_IOAPICS) {
 333         return -1;
 334     }
 335
 336     memory_region_init_io(&s->io_memory, &ioapic_io_ops, s, "ioapic", 0x1000);
 337     sysbus_init_mmio(dev, &s->io_memory);
 338
 339     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 340
 341     ioapics[ioapic_no++] = s;
 342
 343     return 0;
 344 }
 345
 346 static SysBusDeviceInfo ioapic_info = {
 347     .init = ioapic_init1,
 348     .qdev.name = "ioapic",
 349     .qdev.size = sizeof(IOAPICState),
 350     .qdev.vmsd = &vmstate_ioapic,
 351     .qdev.reset = ioapic_reset,
 352     .qdev.no_user = 1,
 353 };
 354
 355 static void ioapic_register_devices(void)
 356 {
 357     sysbus_register_withprop(&ioapic_info);
 358 }
 359
 360 device_init(ioapic_register_devices)