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Added cache configuration to command line options.
[qemu/ovp.git] / cris-dis.c
blob455ba8af3f035ded982a84bfd193d4b3f3d1f208
1 /* Disassembler code for CRIS.
2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Written by Hans-Peter Nilsson.
5
6 This file is part of the GNU binutils and GDB, the GNU debugger.
7
8 This program is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
20
21 #include "dis-asm.h"
22 //#include "sysdep.h"
23 #include "target-cris/opcode-cris.h"
24 //#include "libiberty.h"
25 \f
26
27 void *qemu_malloc(size_t len); /* can't include qemu-common.h here */
28
29 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
30
31 /* cris-opc.c -- Table of opcodes for the CRIS processor.
32 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
33 Contributed by Axis Communications AB, Lund, Sweden.
34 Originally written for GAS 1.38.1 by Mikael Asker.
35 Reorganized by Hans-Peter Nilsson.
36
37 This file is part of GAS, GDB and the GNU binutils.
38
39 GAS, GDB, and GNU binutils is free software; you can redistribute it
40 and/or modify it under the terms of the GNU General Public License as
41 published by the Free Software Foundation; either version 2, or (at your
42 option) any later version.
43
44 GAS, GDB, and GNU binutils are distributed in the hope that they will be
45 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
46 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
47 GNU General Public License for more details.
48
49 You should have received a copy of the GNU General Public License
50 along with this program; if not, see <http://www.gnu.org/licenses/>. */
51
52 #ifndef NULL
53 #define NULL (0)
54 #endif
55
56 /* This table isn't used for CRISv32 and the size of immediate operands. */
57 const struct cris_spec_reg
58 cris_spec_regs[] =
59 {
60 {"bz", 0, 1, cris_ver_v32p, NULL},
61 {"p0", 0, 1, 0, NULL},
62 {"vr", 1, 1, 0, NULL},
63 {"p1", 1, 1, 0, NULL},
64 {"pid", 2, 1, cris_ver_v32p, NULL},
65 {"p2", 2, 1, cris_ver_v32p, NULL},
66 {"p2", 2, 1, cris_ver_warning, NULL},
67 {"srs", 3, 1, cris_ver_v32p, NULL},
68 {"p3", 3, 1, cris_ver_v32p, NULL},
69 {"p3", 3, 1, cris_ver_warning, NULL},
70 {"wz", 4, 2, cris_ver_v32p, NULL},
71 {"p4", 4, 2, 0, NULL},
72 {"ccr", 5, 2, cris_ver_v0_10, NULL},
73 {"exs", 5, 4, cris_ver_v32p, NULL},
74 {"p5", 5, 2, cris_ver_v0_10, NULL},
75 {"p5", 5, 4, cris_ver_v32p, NULL},
76 {"dcr0",6, 2, cris_ver_v0_3, NULL},
77 {"eda", 6, 4, cris_ver_v32p, NULL},
78 {"p6", 6, 2, cris_ver_v0_3, NULL},
79 {"p6", 6, 4, cris_ver_v32p, NULL},
80 {"dcr1/mof", 7, 4, cris_ver_v10p,
81 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
82 {"dcr1/mof", 7, 2, cris_ver_v0_3,
83 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
84 {"mof", 7, 4, cris_ver_v10p, NULL},
85 {"dcr1",7, 2, cris_ver_v0_3, NULL},
86 {"p7", 7, 4, cris_ver_v10p, NULL},
87 {"p7", 7, 2, cris_ver_v0_3, NULL},
88 {"dz", 8, 4, cris_ver_v32p, NULL},
89 {"p8", 8, 4, 0, NULL},
90 {"ibr", 9, 4, cris_ver_v0_10, NULL},
91 {"ebp", 9, 4, cris_ver_v32p, NULL},
92 {"p9", 9, 4, 0, NULL},
93 {"irp", 10, 4, cris_ver_v0_10, NULL},
94 {"erp", 10, 4, cris_ver_v32p, NULL},
95 {"p10", 10, 4, 0, NULL},
96 {"srp", 11, 4, 0, NULL},
97 {"p11", 11, 4, 0, NULL},
98 /* For disassembly use only. Accept at assembly with a warning. */
99 {"bar/dtp0", 12, 4, cris_ver_warning,
100 "Ambiguous register `bar/dtp0' specified"},
101 {"nrp", 12, 4, cris_ver_v32p, NULL},
102 {"bar", 12, 4, cris_ver_v8_10, NULL},
103 {"dtp0",12, 4, cris_ver_v0_3, NULL},
104 {"p12", 12, 4, 0, NULL},
105 /* For disassembly use only. Accept at assembly with a warning. */
106 {"dccr/dtp1",13, 4, cris_ver_warning,
107 "Ambiguous register `dccr/dtp1' specified"},
108 {"ccs", 13, 4, cris_ver_v32p, NULL},
109 {"dccr",13, 4, cris_ver_v8_10, NULL},
110 {"dtp1",13, 4, cris_ver_v0_3, NULL},
111 {"p13", 13, 4, 0, NULL},
112 {"brp", 14, 4, cris_ver_v3_10, NULL},
113 {"usp", 14, 4, cris_ver_v32p, NULL},
114 {"p14", 14, 4, cris_ver_v3p, NULL},
115 {"usp", 15, 4, cris_ver_v10, NULL},
116 {"spc", 15, 4, cris_ver_v32p, NULL},
117 {"p15", 15, 4, cris_ver_v10p, NULL},
118 {NULL, 0, 0, cris_ver_version_all, NULL}
119 };
120
121 /* Add version specifiers to this table when necessary.
122 The (now) regular coding of register names suggests a simpler
123 implementation. */
124 const struct cris_support_reg cris_support_regs[] =
125 {
126 {"s0", 0},
127 {"s1", 1},
128 {"s2", 2},
129 {"s3", 3},
130 {"s4", 4},
131 {"s5", 5},
132 {"s6", 6},
133 {"s7", 7},
134 {"s8", 8},
135 {"s9", 9},
136 {"s10", 10},
137 {"s11", 11},
138 {"s12", 12},
139 {"s13", 13},
140 {"s14", 14},
141 {"s15", 15},
142 {NULL, 0}
143 };
144
145 /* All CRIS opcodes are 16 bits.
146
147 - The match component is a mask saying which bits must match a
148 particular opcode in order for an instruction to be an instance
149 of that opcode.
150
151 - The args component is a string containing characters symbolically
152 matching the operands of an instruction. Used for both assembly
153 and disassembly.
154
155 Operand-matching characters:
156 [ ] , space
157 Verbatim.
158 A The string "ACR" (case-insensitive).
159 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
160 output for the PUSH alias-instructions and recognizes a push-
161 prefix at disassembly. This letter isn't recognized for v32.
162 Must be followed by a R or P letter.
163 ! Non-match pattern, will not match if there's a prefix insn.
164 b Non-matching operand, used for branches with 16-bit
165 displacement. Only recognized by the disassembler.
166 c 5-bit unsigned immediate in bits <4:0>.
167 C 4-bit unsigned immediate in bits <3:0>.
168 d At assembly, optionally (as in put other cases before this one)
169 ".d" or ".D" at the start of the operands, followed by one space
170 character. At disassembly, nothing.
171 D General register in bits <15:12> and <3:0>.
172 f List of flags in bits <15:12> and <3:0>.
173 i 6-bit signed immediate in bits <5:0>.
174 I 6-bit unsigned immediate in bits <5:0>.
175 M Size modifier (B, W or D) for CLEAR instructions.
176 m Size modifier (B, W or D) in bits <5:4>
177 N A 32-bit dword, like in the difference between s and y.
178 This has no effect on bits in the opcode. Can also be expressed
179 as "[pc+]" in input.
180 n As N, but PC-relative (to the start of the instruction).
181 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
182 branch instructions.
183 O [-128..127] offset in bits <7:0>. Also matches a comma and a
184 general register after the expression, in bits <15:12>. Used
185 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
186 P Special register in bits <15:12>.
187 p Indicates that the insn is a prefix insn. Must be first
188 character.
189 Q As O, but don't relax; force an 8-bit offset.
190 R General register in bits <15:12>.
191 r General register in bits <3:0>.
192 S Source operand in bit <10> and a prefix; a 3-operand prefix
193 without side-effect.
194 s Source operand in bits <10> and <3:0>, optionally with a
195 side-effect prefix, except [pc] (the name, not R15 as in ACR)
196 isn't allowed for v32 and higher.
197 T Support register in bits <15:12>.
198 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
199 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
200 Not recognized at disassembly.
201 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
202 y Like 's' but do not allow an integer at assembly.
203 Y The difference s-y; only an integer is allowed.
204 z Size modifier (B or W) in bit <4>. */
205
206
207 /* Please note the order of the opcodes in this table is significant.
208 The assembler requires that all instances of the same mnemonic must
209 be consecutive. If they aren't, the assembler might not recognize
210 them, or may indicate an internal error.
211
212 The disassembler should not normally care about the order of the
213 opcodes, but will prefer an earlier alternative if the "match-score"
214 (see cris-dis.c) is computed as equal.
215
216 It should not be significant for proper execution that this table is
217 in alphabetical order, but please follow that convention for an easy
218 overview. */
219
220 const struct cris_opcode
221 cris_opcodes[] =
222 {
223 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
224 cris_abs_op},
225
226 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
227 cris_reg_mode_add_sub_cmp_and_or_move_op},
228
229 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
230 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
231
232 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
233 cris_ver_v0_10,
234 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
235
236 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
237 cris_ver_v0_10,
238 cris_three_operand_add_sub_cmp_and_or_op},
239
240 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
241 cris_ver_v32p,
242 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
243
244 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
245 cris_ver_v32p,
246 cris_not_implemented_op},
247
248 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
249 cris_ver_v32p,
250 cris_not_implemented_op},
251
252 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
253 cris_ver_v32p,
254 cris_addi_op},
255
256 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
257 cris_addi_op},
258
259 /* This collates after "addo", but we want to disassemble as "addoq",
260 not "addo". */
261 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
262 cris_ver_v32p,
263 cris_not_implemented_op},
264
265 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
266 cris_ver_v32p,
267 cris_not_implemented_op},
268
269 /* This must be located after the insn above, lest we misinterpret
270 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
271 parser bug. */
272 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
273 cris_ver_v32p,
274 cris_not_implemented_op},
275
276 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
277 cris_quick_mode_add_sub_op},
278
279 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
280 cris_reg_mode_add_sub_cmp_and_or_move_op},
281
282 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
283 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
284 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
285
286 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
287 cris_ver_v0_10,
288 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
289
290 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
291 cris_ver_v0_10,
292 cris_three_operand_add_sub_cmp_and_or_op},
293
294 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
295 cris_reg_mode_add_sub_cmp_and_or_move_op},
296
297 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
298 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
299 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
300
301 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
302 cris_ver_v0_10,
303 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
304
305 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
306 cris_ver_v0_10,
307 cris_three_operand_add_sub_cmp_and_or_op},
308
309 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
310 cris_reg_mode_add_sub_cmp_and_or_move_op},
311
312 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
313 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
314
315 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
316 cris_ver_v0_10,
317 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
318
319 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
320 cris_ver_v0_10,
321 cris_three_operand_add_sub_cmp_and_or_op},
322
323 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
324 cris_quick_mode_and_cmp_move_or_op},
325
326 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
327 cris_asr_op},
328
329 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
330 cris_asrq_op},
331
332 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
333 cris_ax_ei_setf_op},
334
335 /* FIXME: Should use branch #defines. */
336 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
337 cris_sixteen_bit_offset_branch_op},
338
339 {"ba",
340 BA_QUICK_OPCODE,
341 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
342 cris_eight_bit_offset_branch_op},
343
344 /* Needs to come after the usual "ba o", which might be relaxed to
345 this one. */
346 {"ba", BA_DWORD_OPCODE,
347 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
348 cris_ver_v32p,
349 cris_none_reg_mode_jump_op},
350
351 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
352 cris_ver_v32p,
353 cris_none_reg_mode_jump_op},
354
355 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
356 cris_ver_v32p,
357 cris_none_reg_mode_jump_op},
358
359 {"bcc",
360 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
361 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
362 cris_eight_bit_offset_branch_op},
363
364 {"bcs",
365 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
366 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
367 cris_eight_bit_offset_branch_op},
368
369 {"bdap",
370 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
371 cris_ver_v0_10,
372 cris_bdap_prefix},
373
374 {"bdap",
375 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
376 cris_ver_v0_10,
377 cris_quick_mode_bdap_prefix},
378
379 {"beq",
380 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
381 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
382 cris_eight_bit_offset_branch_op},
383
384 /* This is deliberately put before "bext" to trump it, even though not
385 in alphabetical order, since we don't do excluding version checks
386 for v0..v10. */
387 {"bwf",
388 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
389 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
390 cris_ver_v10,
391 cris_eight_bit_offset_branch_op},
392
393 {"bext",
394 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
395 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
396 cris_ver_v0_3,
397 cris_eight_bit_offset_branch_op},
398
399 {"bge",
400 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
401 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
402 cris_eight_bit_offset_branch_op},
403
404 {"bgt",
405 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
406 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
407 cris_eight_bit_offset_branch_op},
408
409 {"bhi",
410 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
411 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
412 cris_eight_bit_offset_branch_op},
413
414 {"bhs",
415 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
416 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
417 cris_eight_bit_offset_branch_op},
418
419 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
420 cris_ver_v0_10,
421 cris_biap_prefix},
422
423 {"ble",
424 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
425 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
426 cris_eight_bit_offset_branch_op},
427
428 {"blo",
429 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
430 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
431 cris_eight_bit_offset_branch_op},
432
433 {"bls",
434 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
435 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
436 cris_eight_bit_offset_branch_op},
437
438 {"blt",
439 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
440 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
441 cris_eight_bit_offset_branch_op},
442
443 {"bmi",
444 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
445 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
446 cris_eight_bit_offset_branch_op},
447
448 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
449 cris_ver_sim_v0_10,
450 cris_not_implemented_op},
451
452 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
453 cris_ver_sim_v0_10,
454 cris_not_implemented_op},
455
456 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
457 cris_ver_sim_v0_10,
458 cris_not_implemented_op},
459
460 {"bne",
461 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
462 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
463 cris_eight_bit_offset_branch_op},
464
465 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
466 cris_two_operand_bound_op},
467 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
468 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
469 cris_ver_v0_10,
470 cris_two_operand_bound_op},
471 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
472 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
473 cris_two_operand_bound_op},
474 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
475 cris_ver_v0_10,
476 cris_two_operand_bound_op},
477 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
478 cris_ver_v0_10,
479 cris_three_operand_bound_op},
480
481 {"bpl",
482 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
483 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
484 cris_eight_bit_offset_branch_op},
485
486 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
487 cris_ver_v3p,
488 cris_break_op},
489
490 {"bsb",
491 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
492 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
493 cris_ver_v32p,
494 cris_eight_bit_offset_branch_op},
495
496 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
497 cris_ver_v32p,
498 cris_none_reg_mode_jump_op},
499
500 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
501 cris_ver_v32p,
502 cris_none_reg_mode_jump_op},
503
504 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
505 cris_ver_warning,
506 cris_not_implemented_op},
507
508 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
509 cris_ver_warning,
510 cris_not_implemented_op},
511
512 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
513 cris_ver_warning,
514 cris_not_implemented_op},
515
516 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
517 cris_btst_nop_op},
518 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
519 cris_btst_nop_op},
520
521 {"bvc",
522 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
523 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
524 cris_eight_bit_offset_branch_op},
525
526 {"bvs",
527 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
528 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
529 cris_eight_bit_offset_branch_op},
530
531 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
532 cris_reg_mode_clear_op},
533
534 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
535 cris_none_reg_mode_clear_test_op},
536
537 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
538 cris_ver_v0_10,
539 cris_none_reg_mode_clear_test_op},
540
541 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
542 cris_clearf_di_op},
543
544 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
545 cris_reg_mode_add_sub_cmp_and_or_move_op},
546
547 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
548 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
549
550 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
551 cris_ver_v0_10,
552 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
553
554 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
555 cris_quick_mode_and_cmp_move_or_op},
556
557 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
558 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
559 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
560
561 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
562 cris_ver_v0_10,
563 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
564
565 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
566 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
567 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
568
569 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
570 cris_ver_v0_10,
571 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
572
573 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
574 cris_clearf_di_op},
575
576 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
577 cris_ver_v0_10,
578 cris_dip_prefix},
579
580 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
581 cris_not_implemented_op},
582
583 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
584 cris_dstep_logshift_mstep_neg_not_op},
585
586 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
587 cris_ax_ei_setf_op},
588
589 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
590 cris_ver_v32p,
591 cris_not_implemented_op},
592
593 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
594 cris_ver_v32p,
595 cris_not_implemented_op},
596
597 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
598 cris_ver_v32p,
599 cris_not_implemented_op},
600
601 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
602 cris_ver_v32p,
603 cris_not_implemented_op},
604
605 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
606 cris_ver_v32p,
607 cris_not_implemented_op},
608
609 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
610 cris_ver_v32p,
611 cris_reg_mode_jump_op},
612
613 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
614 cris_ver_v32p,
615 cris_reg_mode_jump_op},
616
617 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
618 cris_ver_v32p,
619 cris_reg_mode_jump_op},
620
621 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
622 cris_ver_v32p,
623 cris_reg_mode_jump_op},
624
625 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
626 cris_ver_v8_10,
627 cris_reg_mode_jump_op},
628
629 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
630 cris_ver_v8_10,
631 cris_none_reg_mode_jump_op},
632
633 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
634 cris_ver_v8_10,
635 cris_none_reg_mode_jump_op},
636
637 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
638 cris_ver_v8_10,
639 cris_reg_mode_jump_op},
640
641 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
642 cris_ver_v8_10,
643 cris_none_reg_mode_jump_op},
644
645 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
646 cris_ver_v8_10,
647 cris_none_reg_mode_jump_op},
648
649 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
650 cris_ver_v8_10,
651 cris_reg_mode_jump_op},
652
653 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
654 cris_ver_v8_10,
655 cris_none_reg_mode_jump_op},
656
657 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
658 cris_ver_v8_10,
659 cris_none_reg_mode_jump_op},
660
661 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
662 cris_reg_mode_jump_op},
663
664 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
665 cris_ver_v0_10,
666 cris_none_reg_mode_jump_op},
667
668 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
669 cris_ver_v32p,
670 cris_none_reg_mode_jump_op},
671
672 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
673 cris_ver_v0_10,
674 cris_none_reg_mode_jump_op},
675
676 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
677 cris_ver_v8_10,
678 cris_reg_mode_jump_op},
679
680 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
681 cris_ver_v8_10,
682 cris_none_reg_mode_jump_op},
683
684 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
685 cris_ver_v8_10,
686 cris_none_reg_mode_jump_op},
687
688 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
689 cris_ver_v32p,
690 cris_reg_mode_jump_op},
691
692 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
693 cris_ver_v32p,
694 cris_reg_mode_jump_op},
695
696 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
697 cris_reg_mode_jump_op},
698
699 {"jump",
700 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
701 cris_ver_v0_10,
702 cris_none_reg_mode_jump_op},
703
704 {"jump",
705 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
706 cris_ver_v0_10,
707 cris_none_reg_mode_jump_op},
708
709 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
710 cris_ver_v32p,
711 cris_none_reg_mode_jump_op},
712
713 {"jump",
714 JUMP_PC_INCR_OPCODE_V32,
715 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
716 cris_ver_v32p,
717 cris_none_reg_mode_jump_op},
718
719 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
720 cris_ver_v10,
721 cris_none_reg_mode_jump_op},
722
723 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
724 cris_ver_v10,
725 cris_none_reg_mode_jump_op},
726
727 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
728 cris_ver_v32p,
729 cris_not_implemented_op},
730
731 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
732 cris_ver_v32p,
733 cris_not_implemented_op},
734
735 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
736 cris_ver_v32p,
737 cris_addi_op},
738
739 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
740 cris_dstep_logshift_mstep_neg_not_op},
741
742 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
743 cris_dstep_logshift_mstep_neg_not_op},
744
745 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
746 cris_dstep_logshift_mstep_neg_not_op},
747
748 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
749 cris_dstep_logshift_mstep_neg_not_op},
750
751 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
752 cris_ver_v3p,
753 cris_not_implemented_op},
754
755 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
756 cris_ver_v32p,
757 cris_not_implemented_op},
758
759 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
760 cris_reg_mode_add_sub_cmp_and_or_move_op},
761
762 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
763 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
764
765 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
766 cris_ver_v0_10,
767 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
768
769 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
770 cris_move_to_preg_op},
771
772 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
773 cris_reg_mode_move_from_preg_op},
774
775 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
776 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
777
778 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
779 cris_ver_v0_10,
780 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
781
782 {"move",
783 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
784 "s,P", 0, SIZE_SPEC_REG, 0,
785 cris_move_to_preg_op},
786
787 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
788 cris_ver_v0_10,
789 cris_move_to_preg_op},
790
791 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
792 cris_none_reg_mode_move_from_preg_op},
793
794 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
795 cris_ver_v0_10,
796 cris_none_reg_mode_move_from_preg_op},
797
798 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
799 cris_ver_v32p,
800 cris_not_implemented_op},
801
802 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
803 cris_ver_v32p,
804 cris_not_implemented_op},
805
806 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
807 cris_move_reg_to_mem_movem_op},
808
809 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
810 cris_ver_v0_10,
811 cris_move_reg_to_mem_movem_op},
812
813 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
814 cris_move_mem_to_reg_movem_op},
815
816 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
817 cris_ver_v0_10,
818 cris_move_mem_to_reg_movem_op},
819
820 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
821 cris_quick_mode_and_cmp_move_or_op},
822
823 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
824 cris_reg_mode_add_sub_cmp_and_or_move_op},
825
826 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
827 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
828 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
829
830 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
831 cris_ver_v0_10,
832 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
833
834 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
835 cris_reg_mode_add_sub_cmp_and_or_move_op},
836
837 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
838 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
839 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
840
841 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
842 cris_ver_v0_10,
843 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
844
845 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
846 cris_ver_v0_10,
847 cris_dstep_logshift_mstep_neg_not_op},
848
849 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
850 cris_ver_v10p,
851 cris_muls_op},
852
853 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
854 cris_ver_v10p,
855 cris_mulu_op},
856
857 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
858 cris_dstep_logshift_mstep_neg_not_op},
859
860 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
861 cris_ver_v0_10,
862 cris_btst_nop_op},
863
864 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
865 cris_ver_v32p,
866 cris_btst_nop_op},
867
868 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
869 cris_dstep_logshift_mstep_neg_not_op},
870
871 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
872 cris_reg_mode_add_sub_cmp_and_or_move_op},
873
874 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
875 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
876
877 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
878 cris_ver_v0_10,
879 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
880
881 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
882 cris_ver_v0_10,
883 cris_three_operand_add_sub_cmp_and_or_op},
884
885 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
886 cris_quick_mode_and_cmp_move_or_op},
887
888 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
889 cris_ver_v0_10,
890 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
891
892 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
893 cris_ver_v0_10,
894 cris_none_reg_mode_move_from_preg_op},
895
896 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
897 cris_ver_v0_10,
898 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
899
900 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
901 cris_ver_v0_10,
902 cris_move_to_preg_op},
903
904 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
905 cris_ver_v10,
906 cris_not_implemented_op},
907
908 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
909 cris_ver_v10,
910 cris_not_implemented_op},
911
912 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
913 cris_ver_v32p,
914 cris_not_implemented_op},
915
916 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
917 cris_ver_v32p,
918 cris_not_implemented_op},
919
920 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
921 cris_ver_v32p,
922 cris_not_implemented_op},
923
924 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
925 cris_ver_v0_10,
926 cris_reg_mode_move_from_preg_op},
927
928 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
929 cris_ver_v32p,
930 cris_reg_mode_move_from_preg_op},
931
932 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
933 cris_ver_v0_10,
934 cris_reg_mode_move_from_preg_op},
935
936 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
937 cris_ver_v32p,
938 cris_reg_mode_move_from_preg_op},
939
940 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
941 cris_ver_v0_10,
942 cris_reg_mode_move_from_preg_op},
943
944 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
945 cris_ver_v32p,
946 cris_reg_mode_move_from_preg_op},
947
948 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
949 cris_ver_v10,
950 cris_not_implemented_op},
951
952 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
953 cris_ver_v10,
954 cris_not_implemented_op},
955
956 {"sa",
957 0x0530+CC_A*0x1000,
958 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
959 cris_scc_op},
960
961 {"ssb",
962 0x0530+CC_EXT*0x1000,
963 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
964 cris_ver_v32p,
965 cris_scc_op},
966
967 {"scc",
968 0x0530+CC_CC*0x1000,
969 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
970 cris_scc_op},
971
972 {"scs",
973 0x0530+CC_CS*0x1000,
974 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
975 cris_scc_op},
976
977 {"seq",
978 0x0530+CC_EQ*0x1000,
979 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
980 cris_scc_op},
981
982 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
983 cris_ax_ei_setf_op},
984
985 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
986 cris_ver_v32p,
987 cris_not_implemented_op},
988
989 /* Need to have "swf" in front of "sext" so it is the one displayed in
990 disassembly. */
991 {"swf",
992 0x0530+CC_EXT*0x1000,
993 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
994 cris_ver_v10,
995 cris_scc_op},
996
997 {"sext",
998 0x0530+CC_EXT*0x1000,
999 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
1000 cris_ver_v0_3,
1001 cris_scc_op},
1002
1003 {"sge",
1004 0x0530+CC_GE*0x1000,
1005 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
1006 cris_scc_op},
1007
1008 {"sgt",
1009 0x0530+CC_GT*0x1000,
1010 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
1011 cris_scc_op},
1012
1013 {"shi",
1014 0x0530+CC_HI*0x1000,
1015 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
1016 cris_scc_op},
1017
1018 {"shs",
1019 0x0530+CC_HS*0x1000,
1020 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
1021 cris_scc_op},
1022
1023 {"sle",
1024 0x0530+CC_LE*0x1000,
1025 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
1026 cris_scc_op},
1027
1028 {"slo",
1029 0x0530+CC_LO*0x1000,
1030 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1031 cris_scc_op},
1032
1033 {"sls",
1034 0x0530+CC_LS*0x1000,
1035 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1036 cris_scc_op},
1037
1038 {"slt",
1039 0x0530+CC_LT*0x1000,
1040 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1041 cris_scc_op},
1042
1043 {"smi",
1044 0x0530+CC_MI*0x1000,
1045 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1046 cris_scc_op},
1047
1048 {"sne",
1049 0x0530+CC_NE*0x1000,
1050 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1051 cris_scc_op},
1052
1053 {"spl",
1054 0x0530+CC_PL*0x1000,
1055 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1056 cris_scc_op},
1057
1058 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1059 cris_reg_mode_add_sub_cmp_and_or_move_op},
1060
1061 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1062 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1063
1064 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1065 cris_ver_v0_10,
1066 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1067
1068 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1069 cris_ver_v0_10,
1070 cris_three_operand_add_sub_cmp_and_or_op},
1071
1072 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1073 cris_quick_mode_add_sub_op},
1074
1075 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1076 cris_reg_mode_add_sub_cmp_and_or_move_op},
1077
1078 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1079 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1080 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1081
1082 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1083 cris_ver_v0_10,
1084 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1085
1086 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1087 cris_ver_v0_10,
1088 cris_three_operand_add_sub_cmp_and_or_op},
1089
1090 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1091 cris_reg_mode_add_sub_cmp_and_or_move_op},
1092
1093 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1094 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1095 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1096
1097 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1098 cris_ver_v0_10,
1099 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1100
1101 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1102 cris_ver_v0_10,
1103 cris_three_operand_add_sub_cmp_and_or_op},
1104
1105 {"svc",
1106 0x0530+CC_VC*0x1000,
1107 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1108 cris_scc_op},
1109
1110 {"svs",
1111 0x0530+CC_VS*0x1000,
1112 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1113 cris_scc_op},
1114
1115 /* The insn "swapn" is the same as "not" and will be disassembled as
1116 such, but the swap* family of mnmonics are generally v8-and-higher
1117 only, so count it in. */
1118 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1119 cris_ver_v8p,
1120 cris_not_implemented_op},
1121
1122 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1123 cris_ver_v8p,
1124 cris_not_implemented_op},
1125
1126 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1127 cris_ver_v8p,
1128 cris_not_implemented_op},
1129
1130 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1131 cris_ver_v8p,
1132 cris_not_implemented_op},
1133
1134 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1135 cris_ver_v8p,
1136 cris_not_implemented_op},
1137
1138 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1139 cris_ver_v8p,
1140 cris_not_implemented_op},
1141
1142 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1143 cris_ver_v8p,
1144 cris_not_implemented_op},
1145
1146 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1147 cris_ver_v8p,
1148 cris_not_implemented_op},
1149
1150 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1151 cris_ver_v8p,
1152 cris_not_implemented_op},
1153
1154 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1155 cris_ver_v8p,
1156 cris_not_implemented_op},
1157
1158 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1159 cris_ver_v8p,
1160 cris_not_implemented_op},
1161
1162 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1163 cris_ver_v8p,
1164 cris_not_implemented_op},
1165
1166 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1167 cris_ver_v8p,
1168 cris_not_implemented_op},
1169
1170 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1171 cris_ver_v8p,
1172 cris_not_implemented_op},
1173
1174 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1175 cris_ver_v8p,
1176 cris_not_implemented_op},
1177
1178 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1179 cris_ver_v0_10,
1180 cris_reg_mode_test_op},
1181
1182 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1183 cris_none_reg_mode_clear_test_op},
1184
1185 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1186 cris_ver_v0_10,
1187 cris_none_reg_mode_clear_test_op},
1188
1189 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1190 cris_xor_op},
1191
1192 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1193 };
1194
1195 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1196 const char * const
1197 cris_cc_strings[] =
1198 {
1199 "hs",
1200 "lo",
1201 "ne",
1202 "eq",
1203 "vc",
1204 "vs",
1205 "pl",
1206 "mi",
1207 "ls",
1208 "hi",
1209 "ge",
1210 "lt",
1211 "gt",
1212 "le",
1213 "a",
1214 /* This is a placeholder. In v0, this would be "ext". In v32, this
1215 is "sb". See cris_conds15. */
1216 "wf"
1217 };
1218
1219 /* Different names and semantics for condition 1111 (0xf). */
1220 const struct cris_cond15 cris_cond15s[] =
1221 {
1222 /* FIXME: In what version did condition "ext" disappear? */
1223 {"ext", cris_ver_v0_3},
1224 {"wf", cris_ver_v10},
1225 {"sb", cris_ver_v32p},
1226 {NULL, 0}
1227 };
1228
1229
1230 /*
1231 * Local variables:
1232 * eval: (c-set-style "gnu")
1233 * indent-tabs-mode: t
1234 * End:
1235 */
1236
1237
1238 /* No instruction will be disassembled longer than this. In theory, and
1239 in silicon, address prefixes can be cascaded. In practice, cascading
1240 is not used by GCC, and not supported by the assembler. */
1241 #ifndef MAX_BYTES_PER_CRIS_INSN
1242 #define MAX_BYTES_PER_CRIS_INSN 8
1243 #endif
1244
1245 /* Whether or not to decode prefixes, folding it into the following
1246 instruction. FIXME: Make this optional later. */
1247 #ifndef PARSE_PREFIX
1248 #define PARSE_PREFIX 1
1249 #endif
1250
1251 /* Sometimes we prefix all registers with this character. */
1252 #define REGISTER_PREFIX_CHAR '$'
1253
1254 /* Whether or not to trace the following sequence:
1255 sub* X,r%d
1256 bound* Y,r%d
1257 adds.w [pc+r%d.w],pc
1258
1259 This is the assembly form of a switch-statement in C.
1260 The "sub is optional. If there is none, then X will be zero.
1261 X is the value of the first case,
1262 Y is the number of cases (including default).
1263
1264 This results in case offsets printed on the form:
1265 case N: -> case_address
1266 where N is an estimation on the corresponding 'case' operand in C,
1267 and case_address is where execution of that case continues after the
1268 sequence presented above.
1269
1270 The old style of output was to print the offsets as instructions,
1271 which made it hard to follow "case"-constructs in the disassembly,
1272 and caused a lot of annoying warnings about undefined instructions.
1273
1274 FIXME: Make this optional later. */
1275 #ifndef TRACE_CASE
1276 #define TRACE_CASE (disdata->trace_case)
1277 #endif
1278
1279 enum cris_disass_family
1280 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1281
1282 /* Stored in the disasm_info->private_data member. */
1283 struct cris_disasm_data
1284 {
1285 /* Whether to print something less confusing if we find something
1286 matching a switch-construct. */
1287 bfd_boolean trace_case;
1288
1289 /* Whether this code is flagged as crisv32. FIXME: Should be an enum
1290 that includes "compatible". */
1291 enum cris_disass_family distype;
1292 };
1293
1294 /* Value of first element in switch. */
1295 static long case_offset = 0;
1296
1297 /* How many more case-offsets to print. */
1298 static long case_offset_counter = 0;
1299
1300 /* Number of case offsets. */
1301 static long no_of_case_offsets = 0;
1302
1303 /* Candidate for next case_offset. */
1304 static long last_immediate = 0;
1305
1306 static int cris_constraint
1307 (const char *, unsigned, unsigned, struct cris_disasm_data *);
1308
1309 /* Parse disassembler options and store state in info. FIXME: For the
1310 time being, we abuse static variables. */
1311
1312 static bfd_boolean
1313 cris_parse_disassembler_options (disassemble_info *info,
1314 enum cris_disass_family distype)
1315 {
1316 struct cris_disasm_data *disdata;
1317
1318 info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1319 disdata = (struct cris_disasm_data *) info->private_data;
1320 if (disdata == NULL)
1321 return false;
1322
1323 /* Default true. */
1324 disdata->trace_case
1325 = (info->disassembler_options == NULL
1326 || (strcmp (info->disassembler_options, "nocase") != 0));
1327
1328 disdata->distype = distype;
1329 return true;
1330 }
1331
1332 static const struct cris_spec_reg *
1333 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1334 {
1335 int i;
1336
1337 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1338 {
1339 if (cris_spec_regs[i].number == sreg)
1340 {
1341 if (distype == cris_dis_v32)
1342 switch (cris_spec_regs[i].applicable_version)
1343 {
1344 case cris_ver_warning:
1345 case cris_ver_version_all:
1346 case cris_ver_v3p:
1347 case cris_ver_v8p:
1348 case cris_ver_v10p:
1349 case cris_ver_v32p:
1350 /* No ambiguous sizes or register names with CRISv32. */
1351 if (cris_spec_regs[i].warning == NULL)
1352 return &cris_spec_regs[i];
1353 default:
1354 ;
1355 }
1356 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1357 return &cris_spec_regs[i];
1358 }
1359 }
1360
1361 return NULL;
1362 }
1363
1364 /* Return the number of bits in the argument. */
1365
1366 static int
1367 number_of_bits (unsigned int val)
1368 {
1369 int bits;
1370
1371 for (bits = 0; val != 0; val &= val - 1)
1372 bits++;
1373
1374 return bits;
1375 }
1376
1377 /* Get an entry in the opcode-table. */
1378
1379 static const struct cris_opcode *
1380 get_opcode_entry (unsigned int insn,
1381 unsigned int prefix_insn,
1382 struct cris_disasm_data *disdata)
1383 {
1384 /* For non-prefixed insns, we keep a table of pointers, indexed by the
1385 insn code. Each entry is initialized when found to be NULL. */
1386 static const struct cris_opcode **opc_table = NULL;
1387
1388 const struct cris_opcode *max_matchedp = NULL;
1389 const struct cris_opcode **prefix_opc_table = NULL;
1390
1391 /* We hold a table for each prefix that need to be handled differently. */
1392 static const struct cris_opcode **dip_prefixes = NULL;
1393 static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1394 static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1395 static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1396 static const struct cris_opcode **rest_prefixes = NULL;
1397
1398 /* Allocate and clear the opcode-table. */
1399 if (opc_table == NULL)
1400 {
1401 opc_table = qemu_malloc (65536 * sizeof (opc_table[0]));
1402
1403 memset (opc_table, 0, 65536 * sizeof (const struct cris_opcode *));
1404
1405 dip_prefixes
1406 = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1407
1408 memset (dip_prefixes, 0, 65536 * sizeof (dip_prefixes[0]));
1409
1410 bdapq_m1_prefixes
1411 = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1412
1413 memset (bdapq_m1_prefixes, 0, 65536 * sizeof (bdapq_m1_prefixes[0]));
1414
1415 bdapq_m2_prefixes
1416 = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1417
1418 memset (bdapq_m2_prefixes, 0, 65536 * sizeof (bdapq_m2_prefixes[0]));
1419
1420 bdapq_m4_prefixes
1421 = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1422
1423 memset (bdapq_m4_prefixes, 0, 65536 * sizeof (bdapq_m4_prefixes[0]));
1424
1425 rest_prefixes
1426 = qemu_malloc (65536 * sizeof (const struct cris_opcode **));
1427
1428 memset (rest_prefixes, 0, 65536 * sizeof (rest_prefixes[0]));
1429 }
1430
1431 /* Get the right table if this is a prefix.
1432 This code is connected to cris_constraints in that it knows what
1433 prefixes play a role in recognition of patterns; the necessary
1434 state is reflected by which table is used. If constraints
1435 involving match or non-match of prefix insns are changed, then this
1436 probably needs changing too. */
1437 if (prefix_insn != NO_CRIS_PREFIX)
1438 {
1439 const struct cris_opcode *popcodep
1440 = (opc_table[prefix_insn] != NULL
1441 ? opc_table[prefix_insn]
1442 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1443
1444 if (popcodep == NULL)
1445 return NULL;
1446
1447 if (popcodep->match == BDAP_QUICK_OPCODE)
1448 {
1449 /* Since some offsets are recognized with "push" macros, we
1450 have to have different tables for them. */
1451 int offset = (prefix_insn & 255);
1452
1453 if (offset > 127)
1454 offset -= 256;
1455
1456 switch (offset)
1457 {
1458 case -4:
1459 prefix_opc_table = bdapq_m4_prefixes;
1460 break;
1461
1462 case -2:
1463 prefix_opc_table = bdapq_m2_prefixes;
1464 break;
1465
1466 case -1:
1467 prefix_opc_table = bdapq_m1_prefixes;
1468 break;
1469
1470 default:
1471 prefix_opc_table = rest_prefixes;
1472 break;
1473 }
1474 }
1475 else if (popcodep->match == DIP_OPCODE)
1476 /* We don't allow postincrement when the prefix is DIP, so use a
1477 different table for DIP. */
1478 prefix_opc_table = dip_prefixes;
1479 else
1480 prefix_opc_table = rest_prefixes;
1481 }
1482
1483 if (prefix_insn != NO_CRIS_PREFIX
1484 && prefix_opc_table[insn] != NULL)
1485 max_matchedp = prefix_opc_table[insn];
1486 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1487 max_matchedp = opc_table[insn];
1488 else
1489 {
1490 const struct cris_opcode *opcodep;
1491 int max_level_of_match = -1;
1492
1493 for (opcodep = cris_opcodes;
1494 opcodep->name != NULL;
1495 opcodep++)
1496 {
1497 int level_of_match;
1498
1499 if (disdata->distype == cris_dis_v32)
1500 {
1501 switch (opcodep->applicable_version)
1502 {
1503 case cris_ver_version_all:
1504 break;
1505
1506 case cris_ver_v0_3:
1507 case cris_ver_v0_10:
1508 case cris_ver_v3_10:
1509 case cris_ver_sim_v0_10:
1510 case cris_ver_v8_10:
1511 case cris_ver_v10:
1512 case cris_ver_warning:
1513 continue;
1514
1515 case cris_ver_v3p:
1516 case cris_ver_v8p:
1517 case cris_ver_v10p:
1518 case cris_ver_v32p:
1519 break;
1520
1521 case cris_ver_v8:
1522 abort ();
1523 default:
1524 abort ();
1525 }
1526 }
1527 else
1528 {
1529 switch (opcodep->applicable_version)
1530 {
1531 case cris_ver_version_all:
1532 case cris_ver_v0_3:
1533 case cris_ver_v3p:
1534 case cris_ver_v0_10:
1535 case cris_ver_v8p:
1536 case cris_ver_v8_10:
1537 case cris_ver_v10:
1538 case cris_ver_sim_v0_10:
1539 case cris_ver_v10p:
1540 case cris_ver_warning:
1541 break;
1542
1543 case cris_ver_v32p:
1544 continue;
1545
1546 case cris_ver_v8:
1547 abort ();
1548 default:
1549 abort ();
1550 }
1551 }
1552
1553 /* We give a double lead for bits matching the template in
1554 cris_opcodes. Not even, because then "move p8,r10" would
1555 be given 2 bits lead over "clear.d r10". When there's a
1556 tie, the first entry in the table wins. This is
1557 deliberate, to avoid a more complicated recognition
1558 formula. */
1559 if ((opcodep->match & insn) == opcodep->match
1560 && (opcodep->lose & insn) == 0
1561 && ((level_of_match
1562 = cris_constraint (opcodep->args,
1563 insn,
1564 prefix_insn,
1565 disdata))
1566 >= 0)
1567 && ((level_of_match
1568 += 2 * number_of_bits (opcodep->match
1569 | opcodep->lose))
1570 > max_level_of_match))
1571 {
1572 max_matchedp = opcodep;
1573 max_level_of_match = level_of_match;
1574
1575 /* If there was a full match, never mind looking
1576 further. */
1577 if (level_of_match >= 2 * 16)
1578 break;
1579 }
1580 }
1581 /* Fill in the new entry.
1582
1583 If there are changes to the opcode-table involving prefixes, and
1584 disassembly then does not work correctly, try removing the
1585 else-clause below that fills in the prefix-table. If that
1586 helps, you need to change the prefix_opc_table setting above, or
1587 something related. */
1588 if (prefix_insn == NO_CRIS_PREFIX)
1589 opc_table[insn] = max_matchedp;
1590 else
1591 prefix_opc_table[insn] = max_matchedp;
1592 }
1593
1594 return max_matchedp;
1595 }
1596
1597 /* Return -1 if the constraints of a bitwise-matched instruction say
1598 that there is no match. Otherwise return a nonnegative number
1599 indicating the confidence in the match (higher is better). */
1600
1601 static int
1602 cris_constraint (const char *cs,
1603 unsigned int insn,
1604 unsigned int prefix_insn,
1605 struct cris_disasm_data *disdata)
1606 {
1607 int retval = 0;
1608 int tmp;
1609 int prefix_ok = 0;
1610 const char *s;
1611
1612 for (s = cs; *s; s++)
1613 switch (*s)
1614 {
1615 case '!':
1616 /* Do not recognize "pop" if there's a prefix and then only for
1617 v0..v10. */
1618 if (prefix_insn != NO_CRIS_PREFIX
1619 || disdata->distype != cris_dis_v0_v10)
1620 return -1;
1621 break;
1622
1623 case 'U':
1624 /* Not recognized at disassembly. */
1625 return -1;
1626
1627 case 'M':
1628 /* Size modifier for "clear", i.e. special register 0, 4 or 8.
1629 Check that it is one of them. Only special register 12 could
1630 be mismatched, but checking for matches is more logical than
1631 checking for mismatches when there are only a few cases. */
1632 tmp = ((insn >> 12) & 0xf);
1633 if (tmp != 0 && tmp != 4 && tmp != 8)
1634 return -1;
1635 break;
1636
1637 case 'm':
1638 if ((insn & 0x30) == 0x30)
1639 return -1;
1640 break;
1641
1642 case 'S':
1643 /* A prefix operand without side-effect. */
1644 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1645 {
1646 prefix_ok = 1;
1647 break;
1648 }
1649 else
1650 return -1;
1651
1652 case 's':
1653 case 'y':
1654 case 'Y':
1655 /* If this is a prefixed insn with postincrement (side-effect),
1656 the prefix must not be DIP. */
1657 if (prefix_insn != NO_CRIS_PREFIX)
1658 {
1659 if (insn & 0x400)
1660 {
1661 const struct cris_opcode *prefix_opcodep
1662 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1663
1664 if (prefix_opcodep->match == DIP_OPCODE)
1665 return -1;
1666 }
1667
1668 prefix_ok = 1;
1669 }
1670 break;
1671
1672 case 'B':
1673 /* If we don't fall through, then the prefix is ok. */
1674 prefix_ok = 1;
1675
1676 /* A "push" prefix. Check for valid "push" size.
1677 In case of special register, it may be != 4. */
1678 if (prefix_insn != NO_CRIS_PREFIX)
1679 {
1680 /* Match the prefix insn to BDAPQ. */
1681 const struct cris_opcode *prefix_opcodep
1682 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1683
1684 if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1685 {
1686 int pushsize = (prefix_insn & 255);
1687
1688 if (pushsize > 127)
1689 pushsize -= 256;
1690
1691 if (s[1] == 'P')
1692 {
1693 unsigned int spec_reg = (insn >> 12) & 15;
1694 const struct cris_spec_reg *sregp
1695 = spec_reg_info (spec_reg, disdata->distype);
1696
1697 /* For a special-register, the "prefix size" must
1698 match the size of the register. */
1699 if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1700 break;
1701 }
1702 else if (s[1] == 'R')
1703 {
1704 if ((insn & 0x30) == 0x20 && pushsize == -4)
1705 break;
1706 }
1707 /* FIXME: Should abort here; next constraint letter
1708 *must* be 'P' or 'R'. */
1709 }
1710 }
1711 return -1;
1712
1713 case 'D':
1714 retval = (((insn >> 12) & 15) == (insn & 15));
1715 if (!retval)
1716 return -1;
1717 else
1718 retval += 4;
1719 break;
1720
1721 case 'P':
1722 {
1723 const struct cris_spec_reg *sregp
1724 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1725
1726 /* Since we match four bits, we will give a value of 4-1 = 3
1727 in a match. If there is a corresponding exact match of a
1728 special register in another pattern, it will get a value of
1729 4, which will be higher. This should be correct in that an
1730 exact pattern would match better than a general pattern.
1731
1732 Note that there is a reason for not returning zero; the
1733 pattern for "clear" is partly matched in the bit-pattern
1734 (the two lower bits must be zero), while the bit-pattern
1735 for a move from a special register is matched in the
1736 register constraint. */
1737
1738 if (sregp != NULL)
1739 {
1740 retval += 3;
1741 break;
1742 }
1743 else
1744 return -1;
1745 }
1746 }
1747
1748 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1749 return -1;
1750
1751 return retval;
1752 }
1753
1754 /* Format number as hex with a leading "0x" into outbuffer. */
1755
1756 static char *
1757 format_hex (unsigned long number,
1758 char *outbuffer,
1759 struct cris_disasm_data *disdata)
1760 {
1761 /* Truncate negative numbers on >32-bit hosts. */
1762 number &= 0xffffffff;
1763
1764 sprintf (outbuffer, "0x%lx", number);
1765
1766 /* Save this value for the "case" support. */
1767 if (TRACE_CASE)
1768 last_immediate = number;
1769
1770 return outbuffer + strlen (outbuffer);
1771 }
1772
1773 /* Format number as decimal into outbuffer. Parameter signedp says
1774 whether the number should be formatted as signed (!= 0) or
1775 unsigned (== 0). */
1776
1777 static char *
1778 format_dec (long number, char *outbuffer, int signedp)
1779 {
1780 last_immediate = number;
1781 sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1782
1783 return outbuffer + strlen (outbuffer);
1784 }
1785
1786 /* Format the name of the general register regno into outbuffer. */
1787
1788 static char *
1789 format_reg (struct cris_disasm_data *disdata,
1790 int regno,
1791 char *outbuffer_start,
1792 bfd_boolean with_reg_prefix)
1793 {
1794 char *outbuffer = outbuffer_start;
1795
1796 if (with_reg_prefix)
1797 *outbuffer++ = REGISTER_PREFIX_CHAR;
1798
1799 switch (regno)
1800 {
1801 case 15:
1802 /* For v32, there is no context in which we output PC. */
1803 if (disdata->distype == cris_dis_v32)
1804 strcpy (outbuffer, "acr");
1805 else
1806 strcpy (outbuffer, "pc");
1807 break;
1808
1809 case 14:
1810 strcpy (outbuffer, "sp");
1811 break;
1812
1813 default:
1814 sprintf (outbuffer, "r%d", regno);
1815 break;
1816 }
1817
1818 return outbuffer_start + strlen (outbuffer_start);
1819 }
1820
1821 /* Format the name of a support register into outbuffer. */
1822
1823 static char *
1824 format_sup_reg (unsigned int regno,
1825 char *outbuffer_start,
1826 bfd_boolean with_reg_prefix)
1827 {
1828 char *outbuffer = outbuffer_start;
1829 int i;
1830
1831 if (with_reg_prefix)
1832 *outbuffer++ = REGISTER_PREFIX_CHAR;
1833
1834 for (i = 0; cris_support_regs[i].name != NULL; i++)
1835 if (cris_support_regs[i].number == regno)
1836 {
1837 sprintf (outbuffer, "%s", cris_support_regs[i].name);
1838 return outbuffer_start + strlen (outbuffer_start);
1839 }
1840
1841 /* There's supposed to be register names covering all numbers, though
1842 some may be generic names. */
1843 sprintf (outbuffer, "format_sup_reg-BUG");
1844 return outbuffer_start + strlen (outbuffer_start);
1845 }
1846
1847 /* Return the length of an instruction. */
1848
1849 static unsigned
1850 bytes_to_skip (unsigned int insn,
1851 const struct cris_opcode *matchedp,
1852 enum cris_disass_family distype,
1853 const struct cris_opcode *prefix_matchedp)
1854 {
1855 /* Each insn is a word plus "immediate" operands. */
1856 unsigned to_skip = 2;
1857 const char *template = matchedp->args;
1858 const char *s;
1859
1860 for (s = template; *s; s++)
1861 if ((*s == 's' || *s == 'N' || *s == 'Y')
1862 && (insn & 0x400) && (insn & 15) == 15
1863 && prefix_matchedp == NULL)
1864 {
1865 /* Immediate via [pc+], so we have to check the size of the
1866 operand. */
1867 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1868
1869 if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1870 to_skip += 4;
1871 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1872 {
1873 const struct cris_spec_reg *sregp
1874 = spec_reg_info ((insn >> 12) & 15, distype);
1875
1876 /* FIXME: Improve error handling; should have been caught
1877 earlier. */
1878 if (sregp == NULL)
1879 return 2;
1880
1881 /* PC is incremented by two, not one, for a byte. Except on
1882 CRISv32, where constants are always DWORD-size for
1883 special registers. */
1884 to_skip +=
1885 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1886 }
1887 else
1888 to_skip += (mode_size + 1) & ~1;
1889 }
1890 else if (*s == 'n')
1891 to_skip += 4;
1892 else if (*s == 'b')
1893 to_skip += 2;
1894
1895 return to_skip;
1896 }
1897
1898 /* Print condition code flags. */
1899
1900 static char *
1901 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1902 {
1903 /* Use the v8 (Etrax 100) flag definitions for disassembly.
1904 The differences with v0 (Etrax 1..4) vs. Svinto are:
1905 v0 'd' <=> v8 'm'
1906 v0 'e' <=> v8 'b'.
1907 FIXME: Emit v0..v3 flag names somehow. */
1908 static const char v8_fnames[] = "cvznxibm";
1909 static const char v32_fnames[] = "cvznxiup";
1910 const char *fnames
1911 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1912
1913 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1914 int i;
1915
1916 for (i = 0; i < 8; i++)
1917 if (flagbits & (1 << i))
1918 *cp++ = fnames[i];
1919
1920 return cp;
1921 }
1922
1923 /* Print out an insn with its operands, and update the info->insn_type
1924 fields. The prefix_opcodep and the rest hold a prefix insn that is
1925 supposed to be output as an address mode. */
1926
1927 static void
1928 print_with_operands (const struct cris_opcode *opcodep,
1929 unsigned int insn,
1930 unsigned char *buffer,
1931 bfd_vma addr,
1932 disassemble_info *info,
1933 /* If a prefix insn was before this insn (and is supposed
1934 to be output as an address), here is a description of
1935 it. */
1936 const struct cris_opcode *prefix_opcodep,
1937 unsigned int prefix_insn,
1938 unsigned char *prefix_buffer,
1939 bfd_boolean with_reg_prefix)
1940 {
1941 /* Get a buffer of somewhat reasonable size where we store
1942 intermediate parts of the insn. */
1943 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1944 char *tp = temp;
1945 static const char mode_char[] = "bwd?";
1946 const char *s;
1947 const char *cs;
1948 struct cris_disasm_data *disdata
1949 = (struct cris_disasm_data *) info->private_data;
1950
1951 /* Print out the name first thing we do. */
1952 (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1953
1954 cs = opcodep->args;
1955 s = cs;
1956
1957 /* Ignore any prefix indicator. */
1958 if (*s == 'p')
1959 s++;
1960
1961 if (*s == 'm' || *s == 'M' || *s == 'z')
1962 {
1963 *tp++ = '.';
1964
1965 /* Get the size-letter. */
1966 *tp++ = *s == 'M'
1967 ? (insn & 0x8000 ? 'd'
1968 : insn & 0x4000 ? 'w' : 'b')
1969 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1970
1971 /* Ignore the size and the space character that follows. */
1972 s += 2;
1973 }
1974
1975 /* Add a space if this isn't a long-branch, because for those will add
1976 the condition part of the name later. */
1977 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1978 *tp++ = ' ';
1979
1980 /* Fill in the insn-type if deducible from the name (and there's no
1981 better way). */
1982 if (opcodep->name[0] == 'j')
1983 {
1984 if (CONST_STRNEQ (opcodep->name, "jsr"))
1985 /* It's "jsr" or "jsrc". */
1986 info->insn_type = dis_jsr;
1987 else
1988 /* Any other jump-type insn is considered a branch. */
1989 info->insn_type = dis_branch;
1990 }
1991
1992 /* We might know some more fields right now. */
1993 info->branch_delay_insns = opcodep->delayed;
1994
1995 /* Handle operands. */
1996 for (; *s; s++)
1997 {
1998 switch (*s)
1999 {
2000 case 'T':
2001 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
2002 break;
2003
2004 case 'A':
2005 if (with_reg_prefix)
2006 *tp++ = REGISTER_PREFIX_CHAR;
2007 *tp++ = 'a';
2008 *tp++ = 'c';
2009 *tp++ = 'r';
2010 break;
2011
2012 case '[':
2013 case ']':
2014 case ',':
2015 *tp++ = *s;
2016 break;
2017
2018 case '!':
2019 /* Ignore at this point; used at earlier stages to avoid
2020 recognition if there's a prefix at something that in other
2021 ways looks like a "pop". */
2022 break;
2023
2024 case 'd':
2025 /* Ignore. This is an optional ".d " on the large one of
2026 relaxable insns. */
2027 break;
2028
2029 case 'B':
2030 /* This was the prefix that made this a "push". We've already
2031 handled it by recognizing it, so signal that the prefix is
2032 handled by setting it to NULL. */
2033 prefix_opcodep = NULL;
2034 break;
2035
2036 case 'D':
2037 case 'r':
2038 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2039 break;
2040
2041 case 'R':
2042 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2043 break;
2044
2045 case 'n':
2046 {
2047 /* Like N but pc-relative to the start of the insn. */
2048 unsigned long number
2049 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2050 + buffer[5] * 0x1000000 + addr);
2051
2052 /* Finish off and output previous formatted bytes. */
2053 *tp = 0;
2054 if (temp[0])
2055 (*info->fprintf_func) (info->stream, "%s", temp);
2056 tp = temp;
2057
2058 (*info->print_address_func) ((bfd_vma) number, info);
2059 }
2060 break;
2061
2062 case 'u':
2063 {
2064 /* Like n but the offset is bits <3:0> in the instruction. */
2065 unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2066
2067 /* Finish off and output previous formatted bytes. */
2068 *tp = 0;
2069 if (temp[0])
2070 (*info->fprintf_func) (info->stream, "%s", temp);
2071 tp = temp;
2072
2073 (*info->print_address_func) ((bfd_vma) number, info);
2074 }
2075 break;
2076
2077 case 'N':
2078 case 'y':
2079 case 'Y':
2080 case 'S':
2081 case 's':
2082 /* Any "normal" memory operand. */
2083 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2084 {
2085 /* We're looking at [pc+], i.e. we need to output an immediate
2086 number, where the size can depend on different things. */
2087 long number;
2088 int signedp
2089 = ((*cs == 'z' && (insn & 0x20))
2090 || opcodep->match == BDAP_QUICK_OPCODE);
2091 int nbytes;
2092
2093 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2094 nbytes = 4;
2095 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2096 {
2097 const struct cris_spec_reg *sregp
2098 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2099
2100 /* A NULL return should have been as a non-match earlier,
2101 so catch it as an internal error in the error-case
2102 below. */
2103 if (sregp == NULL)
2104 /* Whatever non-valid size. */
2105 nbytes = 42;
2106 else
2107 /* PC is always incremented by a multiple of two.
2108 For CRISv32, immediates are always 4 bytes for
2109 special registers. */
2110 nbytes = disdata->distype == cris_dis_v32
2111 ? 4 : (sregp->reg_size + 1) & ~1;
2112 }
2113 else
2114 {
2115 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2116
2117 if (mode_size == 1)
2118 nbytes = 2;
2119 else
2120 nbytes = mode_size;
2121 }
2122
2123 switch (nbytes)
2124 {
2125 case 1:
2126 number = buffer[2];
2127 if (signedp && number > 127)
2128 number -= 256;
2129 break;
2130
2131 case 2:
2132 number = buffer[2] + buffer[3] * 256;
2133 if (signedp && number > 32767)
2134 number -= 65536;
2135 break;
2136
2137 case 4:
2138 number
2139 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2140 + buffer[5] * 0x1000000;
2141 break;
2142
2143 default:
2144 strcpy (tp, "bug");
2145 tp += 3;
2146 number = 42;
2147 }
2148
2149 if ((*cs == 'z' && (insn & 0x20))
2150 || (opcodep->match == BDAP_QUICK_OPCODE
2151 && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2152 tp = format_dec (number, tp, signedp);
2153 else
2154 {
2155 unsigned int highbyte = (number >> 24) & 0xff;
2156
2157 /* Either output this as an address or as a number. If it's
2158 a dword with the same high-byte as the address of the
2159 insn, assume it's an address, and also if it's a non-zero
2160 non-0xff high-byte. If this is a jsr or a jump, then
2161 it's definitely an address. */
2162 if (nbytes == 4
2163 && (highbyte == ((addr >> 24) & 0xff)
2164 || (highbyte != 0 && highbyte != 0xff)
2165 || info->insn_type == dis_branch
2166 || info->insn_type == dis_jsr))
2167 {
2168 /* Finish off and output previous formatted bytes. */
2169 *tp = 0;
2170 tp = temp;
2171 if (temp[0])
2172 (*info->fprintf_func) (info->stream, "%s", temp);
2173
2174 (*info->print_address_func) ((bfd_vma) number, info);
2175
2176 info->target = number;
2177 }
2178 else
2179 tp = format_hex (number, tp, disdata);
2180 }
2181 }
2182 else
2183 {
2184 /* Not an immediate number. Then this is a (possibly
2185 prefixed) memory operand. */
2186 if (info->insn_type != dis_nonbranch)
2187 {
2188 int mode_size
2189 = 1 << ((insn >> 4)
2190 & (opcodep->args[0] == 'z' ? 1 : 3));
2191 int size;
2192 info->insn_type = dis_dref;
2193 info->flags |= CRIS_DIS_FLAG_MEMREF;
2194
2195 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2196 size = 4;
2197 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2198 {
2199 const struct cris_spec_reg *sregp
2200 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2201
2202 /* FIXME: Improve error handling; should have been caught
2203 earlier. */
2204 if (sregp == NULL)
2205 size = 4;
2206 else
2207 size = sregp->reg_size;
2208 }
2209 else
2210 size = mode_size;
2211
2212 info->data_size = size;
2213 }
2214
2215 *tp++ = '[';
2216
2217 if (prefix_opcodep
2218 /* We don't match dip with a postincremented field
2219 as a side-effect address mode. */
2220 && ((insn & 0x400) == 0
2221 || prefix_opcodep->match != DIP_OPCODE))
2222 {
2223 if (insn & 0x400)
2224 {
2225 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2226 *tp++ = '=';
2227 }
2228
2229
2230 /* We mainly ignore the prefix format string when the
2231 address-mode syntax is output. */
2232 switch (prefix_opcodep->match)
2233 {
2234 case DIP_OPCODE:
2235 /* It's [r], [r+] or [pc+]. */
2236 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2237 {
2238 /* It's [pc+]. This cannot possibly be anything
2239 but an address. */
2240 unsigned long number
2241 = prefix_buffer[2] + prefix_buffer[3] * 256
2242 + prefix_buffer[4] * 65536
2243 + prefix_buffer[5] * 0x1000000;
2244
2245 info->target = (bfd_vma) number;
2246
2247 /* Finish off and output previous formatted
2248 data. */
2249 *tp = 0;
2250 tp = temp;
2251 if (temp[0])
2252 (*info->fprintf_func) (info->stream, "%s", temp);
2253
2254 (*info->print_address_func) ((bfd_vma) number, info);
2255 }
2256 else
2257 {
2258 /* For a memref in an address, we use target2.
2259 In this case, target is zero. */
2260 info->flags
2261 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2262 | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2263
2264 info->target2 = prefix_insn & 15;
2265
2266 *tp++ = '[';
2267 tp = format_reg (disdata, prefix_insn & 15, tp,
2268 with_reg_prefix);
2269 if (prefix_insn & 0x400)
2270 *tp++ = '+';
2271 *tp++ = ']';
2272 }
2273 break;
2274
2275 case BDAP_QUICK_OPCODE:
2276 {
2277 int number;
2278
2279 number = prefix_buffer[0];
2280 if (number > 127)
2281 number -= 256;
2282
2283 /* Output "reg+num" or, if num < 0, "reg-num". */
2284 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2285 with_reg_prefix);
2286 if (number >= 0)
2287 *tp++ = '+';
2288 tp = format_dec (number, tp, 1);
2289
2290 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2291 info->target = (prefix_insn >> 12) & 15;
2292 info->target2 = (bfd_vma) number;
2293 break;
2294 }
2295
2296 case BIAP_OPCODE:
2297 /* Output "r+R.m". */
2298 tp = format_reg (disdata, prefix_insn & 15, tp,
2299 with_reg_prefix);
2300 *tp++ = '+';
2301 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2302 with_reg_prefix);
2303 *tp++ = '.';
2304 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2305
2306 info->flags
2307 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2308 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2309
2310 | ((prefix_insn & 0x8000)
2311 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2312 : ((prefix_insn & 0x8000)
2313 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2314
2315 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
2316 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2317 /* Then start interpreting data as offsets. */
2318 case_offset_counter = no_of_case_offsets;
2319 break;
2320
2321 case BDAP_INDIR_OPCODE:
2322 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2323 "r-s". */
2324 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2325 with_reg_prefix);
2326
2327 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2328 {
2329 long number;
2330 unsigned int nbytes;
2331
2332 /* It's a value. Get its size. */
2333 int mode_size = 1 << ((prefix_insn >> 4) & 3);
2334
2335 if (mode_size == 1)
2336 nbytes = 2;
2337 else
2338 nbytes = mode_size;
2339
2340 switch (nbytes)
2341 {
2342 case 1:
2343 number = prefix_buffer[2];
2344 if (number > 127)
2345 number -= 256;
2346 break;
2347
2348 case 2:
2349 number = prefix_buffer[2] + prefix_buffer[3] * 256;
2350 if (number > 32767)
2351 number -= 65536;
2352 break;
2353
2354 case 4:
2355 number
2356 = prefix_buffer[2] + prefix_buffer[3] * 256
2357 + prefix_buffer[4] * 65536
2358 + prefix_buffer[5] * 0x1000000;
2359 break;
2360
2361 default:
2362 strcpy (tp, "bug");
2363 tp += 3;
2364 number = 42;
2365 }
2366
2367 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2368 info->target2 = (bfd_vma) number;
2369
2370 /* If the size is dword, then assume it's an
2371 address. */
2372 if (nbytes == 4)
2373 {
2374 /* Finish off and output previous formatted
2375 bytes. */
2376 *tp++ = '+';
2377 *tp = 0;
2378 tp = temp;
2379 (*info->fprintf_func) (info->stream, "%s", temp);
2380
2381 (*info->print_address_func) ((bfd_vma) number, info);
2382 }
2383 else
2384 {
2385 if (number >= 0)
2386 *tp++ = '+';
2387 tp = format_dec (number, tp, 1);
2388 }
2389 }
2390 else
2391 {
2392 /* Output "r+[R].m" or "r+[R+].m". */
2393 *tp++ = '+';
2394 *tp++ = '[';
2395 tp = format_reg (disdata, prefix_insn & 15, tp,
2396 with_reg_prefix);
2397 if (prefix_insn & 0x400)
2398 *tp++ = '+';
2399 *tp++ = ']';
2400 *tp++ = '.';
2401 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2402
2403 info->flags
2404 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2405 | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2406 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2407
2408 | (((prefix_insn >> 4) == 2)
2409 ? 0
2410 : (((prefix_insn >> 4) & 3) == 1
2411 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2412 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2413 }
2414 break;
2415
2416 default:
2417 (*info->fprintf_func) (info->stream, "?prefix-bug");
2418 }
2419
2420 /* To mark that the prefix is used, reset it. */
2421 prefix_opcodep = NULL;
2422 }
2423 else
2424 {
2425 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2426
2427 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2428 info->target = insn & 15;
2429
2430 if (insn & 0x400)
2431 *tp++ = '+';
2432 }
2433 *tp++ = ']';
2434 }
2435 break;
2436
2437 case 'x':
2438 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2439 *tp++ = '.';
2440 *tp++ = mode_char[(insn >> 4) & 3];
2441 break;
2442
2443 case 'I':
2444 tp = format_dec (insn & 63, tp, 0);
2445 break;
2446
2447 case 'b':
2448 {
2449 int where = buffer[2] + buffer[3] * 256;
2450
2451 if (where > 32767)
2452 where -= 65536;
2453
2454 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2455
2456 if (insn == BA_PC_INCR_OPCODE)
2457 info->insn_type = dis_branch;
2458 else
2459 info->insn_type = dis_condbranch;
2460
2461 info->target = (bfd_vma) where;
2462
2463 *tp = 0;
2464 tp = temp;
2465 (*info->fprintf_func) (info->stream, "%s%s ",
2466 temp, cris_cc_strings[insn >> 12]);
2467
2468 (*info->print_address_func) ((bfd_vma) where, info);
2469 }
2470 break;
2471
2472 case 'c':
2473 tp = format_dec (insn & 31, tp, 0);
2474 break;
2475
2476 case 'C':
2477 tp = format_dec (insn & 15, tp, 0);
2478 break;
2479
2480 case 'o':
2481 {
2482 long offset = insn & 0xfe;
2483 bfd_vma target;
2484
2485 if (insn & 1)
2486 offset |= ~0xff;
2487
2488 if (opcodep->match == BA_QUICK_OPCODE)
2489 info->insn_type = dis_branch;
2490 else
2491 info->insn_type = dis_condbranch;
2492
2493 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2494 info->target = target;
2495 *tp = 0;
2496 tp = temp;
2497 (*info->fprintf_func) (info->stream, "%s", temp);
2498 (*info->print_address_func) (target, info);
2499 }
2500 break;
2501
2502 case 'Q':
2503 case 'O':
2504 {
2505 long number = buffer[0];
2506
2507 if (number > 127)
2508 number = number - 256;
2509
2510 tp = format_dec (number, tp, 1);
2511 *tp++ = ',';
2512 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2513 }
2514 break;
2515
2516 case 'f':
2517 tp = print_flags (disdata, insn, tp);
2518 break;
2519
2520 case 'i':
2521 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2522 break;
2523
2524 case 'P':
2525 {
2526 const struct cris_spec_reg *sregp
2527 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2528
2529 if (sregp->name == NULL)
2530 /* Should have been caught as a non-match eariler. */
2531 *tp++ = '?';
2532 else
2533 {
2534 if (with_reg_prefix)
2535 *tp++ = REGISTER_PREFIX_CHAR;
2536 strcpy (tp, sregp->name);
2537 tp += strlen (tp);
2538 }
2539 }
2540 break;
2541
2542 default:
2543 strcpy (tp, "???");
2544 tp += 3;
2545 }
2546 }
2547
2548 *tp = 0;
2549
2550 if (prefix_opcodep)
2551 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2552 prefix_opcodep->name, prefix_opcodep->args);
2553
2554 (*info->fprintf_func) (info->stream, "%s", temp);
2555
2556 /* Get info for matching case-tables, if we don't have any active.
2557 We assume that the last constant seen is used; either in the insn
2558 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
2559 if (TRACE_CASE && case_offset_counter == 0)
2560 {
2561 if (CONST_STRNEQ (opcodep->name, "sub"))
2562 case_offset = last_immediate;
2563
2564 /* It could also be an "add", if there are negative case-values. */
2565 else if (CONST_STRNEQ (opcodep->name, "add"))
2566 /* The first case is the negated operand to the add. */
2567 case_offset = -last_immediate;
2568
2569 /* A bound insn will tell us the number of cases. */
2570 else if (CONST_STRNEQ (opcodep->name, "bound"))
2571 no_of_case_offsets = last_immediate + 1;
2572
2573 /* A jump or jsr or branch breaks the chain of insns for a
2574 case-table, so assume default first-case again. */
2575 else if (info->insn_type == dis_jsr
2576 || info->insn_type == dis_branch
2577 || info->insn_type == dis_condbranch)
2578 case_offset = 0;
2579 }
2580 }
2581
2582
2583 /* Print the CRIS instruction at address memaddr on stream. Returns
2584 length of the instruction, in bytes. Prefix register names with `$' if
2585 WITH_REG_PREFIX. */
2586
2587 static int
2588 print_insn_cris_generic (bfd_vma memaddr,
2589 disassemble_info *info,
2590 bfd_boolean with_reg_prefix)
2591 {
2592 int nbytes;
2593 unsigned int insn;
2594 const struct cris_opcode *matchedp;
2595 int advance = 0;
2596 struct cris_disasm_data *disdata
2597 = (struct cris_disasm_data *) info->private_data;
2598
2599 /* No instruction will be disassembled as longer than this number of
2600 bytes; stacked prefixes will not be expanded. */
2601 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2602 unsigned char *bufp;
2603 int status = 0;
2604 bfd_vma addr;
2605
2606 /* There will be an "out of range" error after the last instruction.
2607 Reading pairs of bytes in decreasing number, we hope that we will get
2608 at least the amount that we will consume.
2609
2610 If we can't get any data, or we do not get enough data, we print
2611 the error message. */
2612
2613 nbytes = info->buffer_length;
2614 if (nbytes > MAX_BYTES_PER_CRIS_INSN)
2615 nbytes = MAX_BYTES_PER_CRIS_INSN;
2616 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2617
2618 /* If we did not get all we asked for, then clear the rest.
2619 Hopefully this makes a reproducible result in case of errors. */
2620 if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2621 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2622
2623 addr = memaddr;
2624 bufp = buffer;
2625
2626 /* Set some defaults for the insn info. */
2627 info->insn_info_valid = 1;
2628 info->branch_delay_insns = 0;
2629 info->data_size = 0;
2630 info->insn_type = dis_nonbranch;
2631 info->flags = 0;
2632 info->target = 0;
2633 info->target2 = 0;
2634
2635 /* If we got any data, disassemble it. */
2636 if (nbytes != 0)
2637 {
2638 matchedp = NULL;
2639
2640 insn = bufp[0] + bufp[1] * 256;
2641
2642 /* If we're in a case-table, don't disassemble the offsets. */
2643 if (TRACE_CASE && case_offset_counter != 0)
2644 {
2645 info->insn_type = dis_noninsn;
2646 advance += 2;
2647
2648 /* If to print data as offsets, then shortcut here. */
2649 (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2650 case_offset + no_of_case_offsets
2651 - case_offset_counter,
2652 case_offset_counter == 1 ? "/default" :
2653 "");
2654
2655 (*info->print_address_func) ((bfd_vma)
2656 ((short) (insn)
2657 + (long) (addr
2658 - (no_of_case_offsets
2659 - case_offset_counter)
2660 * 2)), info);
2661 case_offset_counter--;
2662
2663 /* The default case start (without a "sub" or "add") must be
2664 zero. */
2665 if (case_offset_counter == 0)
2666 case_offset = 0;
2667 }
2668 else if (insn == 0)
2669 {
2670 /* We're often called to disassemble zeroes. While this is a
2671 valid "bcc .+2" insn, it is also useless enough and enough
2672 of a nuiscance that we will just output "bcc .+2" for it
2673 and signal it as a noninsn. */
2674 (*info->fprintf_func) (info->stream,
2675 disdata->distype == cris_dis_v32
2676 ? "bcc ." : "bcc .+2");
2677 info->insn_type = dis_noninsn;
2678 advance += 2;
2679 }
2680 else
2681 {
2682 const struct cris_opcode *prefix_opcodep = NULL;
2683 unsigned char *prefix_buffer = bufp;
2684 unsigned int prefix_insn = insn;
2685 int prefix_size = 0;
2686
2687 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2688
2689 /* Check if we're supposed to write out prefixes as address
2690 modes and if this was a prefix. */
2691 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2692 {
2693 /* If it's a prefix, put it into the prefix vars and get the
2694 main insn. */
2695 prefix_size = bytes_to_skip (prefix_insn, matchedp,
2696 disdata->distype, NULL);
2697 prefix_opcodep = matchedp;
2698
2699 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2700 matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2701
2702 if (matchedp != NULL)
2703 {
2704 addr += prefix_size;
2705 bufp += prefix_size;
2706 advance += prefix_size;
2707 }
2708 else
2709 {
2710 /* The "main" insn wasn't valid, at least not when
2711 prefixed. Put back things enough to output the
2712 prefix insn only, as a normal insn. */
2713 matchedp = prefix_opcodep;
2714 insn = prefix_insn;
2715 prefix_opcodep = NULL;
2716 }
2717 }
2718
2719 if (matchedp == NULL)
2720 {
2721 (*info->fprintf_func) (info->stream, "??0x%x", insn);
2722 advance += 2;
2723
2724 info->insn_type = dis_noninsn;
2725 }
2726 else
2727 {
2728 advance
2729 += bytes_to_skip (insn, matchedp, disdata->distype,
2730 prefix_opcodep);
2731
2732 /* The info_type and assorted fields will be set according
2733 to the operands. */
2734 print_with_operands (matchedp, insn, bufp, addr, info,
2735 prefix_opcodep, prefix_insn,
2736 prefix_buffer, with_reg_prefix);
2737 }
2738 }
2739 }
2740 else
2741 info->insn_type = dis_noninsn;
2742
2743 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2744 status when reading that much, and the insn decoding indicated a
2745 length exceeding what we read, there is an error. */
2746 if (status != 0 && (nbytes == 0 || advance > nbytes))
2747 {
2748 (*info->memory_error_func) (status, memaddr, info);
2749 return -1;
2750 }
2751
2752 /* Max supported insn size with one folded prefix insn. */
2753 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2754
2755 /* I would like to set this to a fixed value larger than the actual
2756 number of bytes to print in order to avoid spaces between bytes,
2757 but objdump.c (2.9.1) does not like that, so we print 16-bit
2758 chunks, which is the next choice. */
2759 info->bytes_per_chunk = 2;
2760
2761 /* Printing bytes in order of increasing addresses makes sense,
2762 especially on a little-endian target.
2763 This is completely the opposite of what you think; setting this to
2764 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2765 we want. */
2766 info->display_endian = BFD_ENDIAN_BIG;
2767
2768 return advance;
2769 }
2770
2771 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
2772 #if 0
2773 static int
2774 print_insn_cris_with_register_prefix (bfd_vma vma,
2775 disassemble_info *info)
2776 {
2777 if (info->private_data == NULL
2778 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2779 return -1;
2780 return print_insn_cris_generic (vma, info, true);
2781 }
2782 #endif
2783 /* Disassemble, prefixing register names with `$'. CRIS v32. */
2784
2785 static int
2786 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2787 disassemble_info *info)
2788 {
2789 if (info->private_data == NULL
2790 && !cris_parse_disassembler_options (info, cris_dis_v32))
2791 return -1;
2792 return print_insn_cris_generic (vma, info, true);
2793 }
2794
2795 #if 0
2796 /* Disassemble, prefixing register names with `$'.
2797 Common v10 and v32 subset. */
2798
2799 static int
2800 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2801 disassemble_info *info)
2802 {
2803 if (info->private_data == NULL
2804 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2805 return -1;
2806 return print_insn_cris_generic (vma, info, true);
2807 }
2808
2809 /* Disassemble, no prefixes on register names. CRIS v0..v10. */
2810
2811 static int
2812 print_insn_cris_without_register_prefix (bfd_vma vma,
2813 disassemble_info *info)
2814 {
2815 if (info->private_data == NULL
2816 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2817 return -1;
2818 return print_insn_cris_generic (vma, info, false);
2819 }
2820
2821 /* Disassemble, no prefixes on register names. CRIS v32. */
2822
2823 static int
2824 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2825 disassemble_info *info)
2826 {
2827 if (info->private_data == NULL
2828 && !cris_parse_disassembler_options (info, cris_dis_v32))
2829 return -1;
2830 return print_insn_cris_generic (vma, info, false);
2831 }
2832
2833 /* Disassemble, no prefixes on register names.
2834 Common v10 and v32 subset. */
2835
2836 static int
2837 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2838 disassemble_info *info)
2839 {
2840 if (info->private_data == NULL
2841 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2842 return -1;
2843 return print_insn_cris_generic (vma, info, false);
2844 }
2845 #endif
2846
2847 int
2848 print_insn_crisv32 (bfd_vma vma,
2849 disassemble_info *info)
2850 {
2851 return print_insn_crisv32_with_register_prefix(vma, info);
2852 }
2853
2854 /* Return a disassembler-function that prints registers with a `$' prefix,
2855 or one that prints registers without a prefix.
2856 FIXME: We should improve the solution to avoid the multitude of
2857 functions seen above. */
2858 #if 0
2859 disassembler_ftype
2860 cris_get_disassembler (bfd *abfd)
2861 {
2862 /* If there's no bfd in sight, we return what is valid as input in all
2863 contexts if fed back to the assembler: disassembly *with* register
2864 prefix. Unfortunately this will be totally wrong for v32. */
2865 if (abfd == NULL)
2866 return print_insn_cris_with_register_prefix;
2867
2868 if (bfd_get_symbol_leading_char (abfd) == 0)
2869 {
2870 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2871 return print_insn_crisv32_with_register_prefix;
2872 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2873 return print_insn_crisv10_v32_with_register_prefix;
2874
2875 /* We default to v10. This may be specifically specified in the
2876 bfd mach, but is also the default setting. */
2877 return print_insn_cris_with_register_prefix;
2878 }
2879
2880 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2881 return print_insn_crisv32_without_register_prefix;
2882 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2883 return print_insn_crisv10_v32_without_register_prefix;
2884 return print_insn_cris_without_register_prefix;
2885 }
2886 #endif
2887 /* Local variables:
2888 eval: (c-set-style "gnu")
2889 indent-tabs-mode: t
2890 End: */
Virtio block backend used in Open Virtualization on Power