hw/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "sysbus.h"
  11 #include "ui/console.h"
  12 #include "framebuffer.h"
  13 #include "ui/pixel_ops.h"
  14
  15 #define PL110_CR_EN   0x001
  16 #define PL110_CR_BGR  0x100
  17 #define PL110_CR_BEBO 0x200
  18 #define PL110_CR_BEPO 0x400
  19 #define PL110_CR_PWR  0x800
  20
  21 enum pl110_bppmode
  22 {
  23     BPP_1,
  24     BPP_2,
  25     BPP_4,
  26     BPP_8,
  27     BPP_16,
  28     BPP_32,
  29     BPP_16_565, /* PL111 only */
  30     BPP_12      /* PL111 only */
  31 };
  32
  33
  34 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  35 enum pl110_version
  36 {
  37     PL110,
  38     PL110_VERSATILE,
  39     PL111
  40 };
  41
  42 typedef struct {
  43     SysBusDevice busdev;
  44     MemoryRegion iomem;
  45     DisplayState *ds;
  46
  47     int version;
  48     uint32_t timing[4];
  49     uint32_t cr;
  50     uint32_t upbase;
  51     uint32_t lpbase;
  52     uint32_t int_status;
  53     uint32_t int_mask;
  54     int cols;
  55     int rows;
  56     enum pl110_bppmode bpp;
  57     int invalidate;
  58     uint32_t mux_ctrl;
  59     uint32_t palette[256];
  60     uint32_t raw_palette[128];
  61     qemu_irq irq;
  62 } pl110_state;
  63
  64 static int vmstate_pl110_post_load(void *opaque, int version_id);
  65
  66 static const VMStateDescription vmstate_pl110 = {
  67     .name = "pl110",
  68     .version_id = 2,
  69     .minimum_version_id = 1,
  70     .post_load = vmstate_pl110_post_load,
  71     .fields = (VMStateField[]) {
  72         VMSTATE_INT32(version, pl110_state),
  73         VMSTATE_UINT32_ARRAY(timing, pl110_state, 4),
  74         VMSTATE_UINT32(cr, pl110_state),
  75         VMSTATE_UINT32(upbase, pl110_state),
  76         VMSTATE_UINT32(lpbase, pl110_state),
  77         VMSTATE_UINT32(int_status, pl110_state),
  78         VMSTATE_UINT32(int_mask, pl110_state),
  79         VMSTATE_INT32(cols, pl110_state),
  80         VMSTATE_INT32(rows, pl110_state),
  81         VMSTATE_UINT32(bpp, pl110_state),
  82         VMSTATE_INT32(invalidate, pl110_state),
  83         VMSTATE_UINT32_ARRAY(palette, pl110_state, 256),
  84         VMSTATE_UINT32_ARRAY(raw_palette, pl110_state, 128),
  85         VMSTATE_UINT32_V(mux_ctrl, pl110_state, 2),
  86         VMSTATE_END_OF_LIST()
  87     }
  88 };
  89
  90 static const unsigned char pl110_id[] =
  91 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  92
  93 /* The Arm documentation (DDI0224C) says the CLDC on the Versatile board
  94    has a different ID.  However Linux only looks for the normal ID.  */
  95 #if 0
  96 static const unsigned char pl110_versatile_id[] =
  97 { 0x93, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  98 #else
  99 #define pl110_versatile_id pl110_id
 100 #endif
 101
 102 static const unsigned char pl111_id[] = {
 103     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
 104 };
 105
 106 /* Indexed by pl110_version */
 107 static const unsigned char *idregs[] = {
 108     pl110_id,
 109     pl110_versatile_id,
 110     pl111_id
 111 };
 112
 113 #define BITS 8
 114 #include "pl110_template.h"
 115 #define BITS 15
 116 #include "pl110_template.h"
 117 #define BITS 16
 118 #include "pl110_template.h"
 119 #define BITS 24
 120 #include "pl110_template.h"
 121 #define BITS 32
 122 #include "pl110_template.h"
 123
 124 static int pl110_enabled(pl110_state *s)
 125 {
 126   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 127 }
 128
 129 static void pl110_update_display(void *opaque)
 130 {
 131     pl110_state *s = (pl110_state *)opaque;
 132     drawfn* fntable;
 133     drawfn fn;
 134     int dest_width;
 135     int src_width;
 136     int bpp_offset;
 137     int first;
 138     int last;
 139
 140     if (!pl110_enabled(s))
 141         return;
 142
 143     switch (ds_get_bits_per_pixel(s->ds)) {
 144     case 0:
 145         return;
 146     case 8:
 147         fntable = pl110_draw_fn_8;
 148         dest_width = 1;
 149         break;
 150     case 15:
 151         fntable = pl110_draw_fn_15;
 152         dest_width = 2;
 153         break;
 154     case 16:
 155         fntable = pl110_draw_fn_16;
 156         dest_width = 2;
 157         break;
 158     case 24:
 159         fntable = pl110_draw_fn_24;
 160         dest_width = 3;
 161         break;
 162     case 32:
 163         fntable = pl110_draw_fn_32;
 164         dest_width = 4;
 165         break;
 166     default:
 167         fprintf(stderr, "pl110: Bad color depth\n");
 168         exit(1);
 169     }
 170     if (s->cr & PL110_CR_BGR)
 171         bpp_offset = 0;
 172     else
 173         bpp_offset = 24;
 174
 175     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 176         /* The PL110's native 16 bit mode is 5551; however
 177          * most boards with a PL110 implement an external
 178          * mux which allows bits to be reshuffled to give
 179          * 565 format. The mux is typically controlled by
 180          * an external system register.
 181          * This is controlled by a GPIO input pin
 182          * so boards can wire it up to their register.
 183          *
 184          * The PL111 straightforwardly implements both
 185          * 5551 and 565 under control of the bpp field
 186          * in the LCDControl register.
 187          */
 188         switch (s->mux_ctrl) {
 189         case 3: /* 565 BGR */
 190             bpp_offset = (BPP_16_565 - BPP_16);
 191             break;
 192         case 1: /* 5551 */
 193             break;
 194         case 0: /* 888; also if we have loaded vmstate from an old version */
 195         case 2: /* 565 RGB */
 196         default:
 197             /* treat as 565 but honour BGR bit */
 198             bpp_offset += (BPP_16_565 - BPP_16);
 199             break;
 200         }
 201     }
 202
 203     if (s->cr & PL110_CR_BEBO)
 204         fn = fntable[s->bpp + 8 + bpp_offset];
 205     else if (s->cr & PL110_CR_BEPO)
 206         fn = fntable[s->bpp + 16 + bpp_offset];
 207     else
 208         fn = fntable[s->bpp + bpp_offset];
 209
 210     src_width = s->cols;
 211     switch (s->bpp) {
 212     case BPP_1:
 213         src_width >>= 3;
 214         break;
 215     case BPP_2:
 216         src_width >>= 2;
 217         break;
 218     case BPP_4:
 219         src_width >>= 1;
 220         break;
 221     case BPP_8:
 222         break;
 223     case BPP_16:
 224     case BPP_16_565:
 225     case BPP_12:
 226         src_width <<= 1;
 227         break;
 228     case BPP_32:
 229         src_width <<= 2;
 230         break;
 231     }
 232     dest_width *= s->cols;
 233     first = 0;
 234     framebuffer_update_display(s->ds, sysbus_address_space(&s->busdev),
 235                                s->upbase, s->cols, s->rows,
 236                                src_width, dest_width, 0,
 237                                s->invalidate,
 238                                fn, s->palette,
 239                                &first, &last);
 240     if (first >= 0) {
 241         dpy_gfx_update(s->ds, 0, first, s->cols, last - first + 1);
 242     }
 243     s->invalidate = 0;
 244 }
 245
 246 static void pl110_invalidate_display(void * opaque)
 247 {
 248     pl110_state *s = (pl110_state *)opaque;
 249     s->invalidate = 1;
 250     if (pl110_enabled(s)) {
 251         qemu_console_resize(s->ds, s->cols, s->rows);
 252     }
 253 }
 254
 255 static void pl110_update_palette(pl110_state *s, int n)
 256 {
 257     int i;
 258     uint32_t raw;
 259     unsigned int r, g, b;
 260
 261     raw = s->raw_palette[n];
 262     n <<= 1;
 263     for (i = 0; i < 2; i++) {
 264         r = (raw & 0x1f) << 3;
 265         raw >>= 5;
 266         g = (raw & 0x1f) << 3;
 267         raw >>= 5;
 268         b = (raw & 0x1f) << 3;
 269         /* The I bit is ignored.  */
 270         raw >>= 6;
 271         switch (ds_get_bits_per_pixel(s->ds)) {
 272         case 8:
 273             s->palette[n] = rgb_to_pixel8(r, g, b);
 274             break;
 275         case 15:
 276             s->palette[n] = rgb_to_pixel15(r, g, b);
 277             break;
 278         case 16:
 279             s->palette[n] = rgb_to_pixel16(r, g, b);
 280             break;
 281         case 24:
 282         case 32:
 283             s->palette[n] = rgb_to_pixel32(r, g, b);
 284             break;
 285         }
 286         n++;
 287     }
 288 }
 289
 290 static void pl110_resize(pl110_state *s, int width, int height)
 291 {
 292     if (width != s->cols || height != s->rows) {
 293         if (pl110_enabled(s)) {
 294             qemu_console_resize(s->ds, width, height);
 295         }
 296     }
 297     s->cols = width;
 298     s->rows = height;
 299 }
 300
 301 /* Update interrupts.  */
 302 static void pl110_update(pl110_state *s)
 303 {
 304   /* TODO: Implement interrupts.  */
 305 }
 306
 307 static uint64_t pl110_read(void *opaque, hwaddr offset,
 308                            unsigned size)
 309 {
 310     pl110_state *s = (pl110_state *)opaque;
 311
 312     if (offset >= 0xfe0 && offset < 0x1000) {
 313         return idregs[s->version][(offset - 0xfe0) >> 2];
 314     }
 315     if (offset >= 0x200 && offset < 0x400) {
 316         return s->raw_palette[(offset - 0x200) >> 2];
 317     }
 318     switch (offset >> 2) {
 319     case 0: /* LCDTiming0 */
 320         return s->timing[0];
 321     case 1: /* LCDTiming1 */
 322         return s->timing[1];
 323     case 2: /* LCDTiming2 */
 324         return s->timing[2];
 325     case 3: /* LCDTiming3 */
 326         return s->timing[3];
 327     case 4: /* LCDUPBASE */
 328         return s->upbase;
 329     case 5: /* LCDLPBASE */
 330         return s->lpbase;
 331     case 6: /* LCDIMSC */
 332         if (s->version != PL110) {
 333             return s->cr;
 334         }
 335         return s->int_mask;
 336     case 7: /* LCDControl */
 337         if (s->version != PL110) {
 338             return s->int_mask;
 339         }
 340         return s->cr;
 341     case 8: /* LCDRIS */
 342         return s->int_status;
 343     case 9: /* LCDMIS */
 344         return s->int_status & s->int_mask;
 345     case 11: /* LCDUPCURR */
 346         /* TODO: Implement vertical refresh.  */
 347         return s->upbase;
 348     case 12: /* LCDLPCURR */
 349         return s->lpbase;
 350     default:
 351         qemu_log_mask(LOG_GUEST_ERROR,
 352                       "pl110_read: Bad offset %x\n", (int)offset);
 353         return 0;
 354     }
 355 }
 356
 357 static void pl110_write(void *opaque, hwaddr offset,
 358                         uint64_t val, unsigned size)
 359 {
 360     pl110_state *s = (pl110_state *)opaque;
 361     int n;
 362
 363     /* For simplicity invalidate the display whenever a control register
 364        is written to.  */
 365     s->invalidate = 1;
 366     if (offset >= 0x200 && offset < 0x400) {
 367         /* Palette.  */
 368         n = (offset - 0x200) >> 2;
 369         s->raw_palette[(offset - 0x200) >> 2] = val;
 370         pl110_update_palette(s, n);
 371         return;
 372     }
 373     switch (offset >> 2) {
 374     case 0: /* LCDTiming0 */
 375         s->timing[0] = val;
 376         n = ((val & 0xfc) + 4) * 4;
 377         pl110_resize(s, n, s->rows);
 378         break;
 379     case 1: /* LCDTiming1 */
 380         s->timing[1] = val;
 381         n = (val & 0x3ff) + 1;
 382         pl110_resize(s, s->cols, n);
 383         break;
 384     case 2: /* LCDTiming2 */
 385         s->timing[2] = val;
 386         break;
 387     case 3: /* LCDTiming3 */
 388         s->timing[3] = val;
 389         break;
 390     case 4: /* LCDUPBASE */
 391         s->upbase = val;
 392         break;
 393     case 5: /* LCDLPBASE */
 394         s->lpbase = val;
 395         break;
 396     case 6: /* LCDIMSC */
 397         if (s->version != PL110) {
 398             goto control;
 399         }
 400     imsc:
 401         s->int_mask = val;
 402         pl110_update(s);
 403         break;
 404     case 7: /* LCDControl */
 405         if (s->version != PL110) {
 406             goto imsc;
 407         }
 408     control:
 409         s->cr = val;
 410         s->bpp = (val >> 1) & 7;
 411         if (pl110_enabled(s)) {
 412             qemu_console_resize(s->ds, s->cols, s->rows);
 413         }
 414         break;
 415     case 10: /* LCDICR */
 416         s->int_status &= ~val;
 417         pl110_update(s);
 418         break;
 419     default:
 420         qemu_log_mask(LOG_GUEST_ERROR,
 421                       "pl110_write: Bad offset %x\n", (int)offset);
 422     }
 423 }
 424
 425 static const MemoryRegionOps pl110_ops = {
 426     .read = pl110_read,
 427     .write = pl110_write,
 428     .endianness = DEVICE_NATIVE_ENDIAN,
 429 };
 430
 431 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 432 {
 433     pl110_state *s = (pl110_state *)opaque;
 434     s->mux_ctrl = level;
 435 }
 436
 437 static int vmstate_pl110_post_load(void *opaque, int version_id)
 438 {
 439     pl110_state *s = opaque;
 440     /* Make sure we redraw, and at the right size */
 441     pl110_invalidate_display(s);
 442     return 0;
 443 }
 444
 445 static int pl110_init(SysBusDevice *dev)
 446 {
 447     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 448
 449     memory_region_init_io(&s->iomem, &pl110_ops, s, "pl110", 0x1000);
 450     sysbus_init_mmio(dev, &s->iomem);
 451     sysbus_init_irq(dev, &s->irq);
 452     qdev_init_gpio_in(&s->busdev.qdev, pl110_mux_ctrl_set, 1);
 453     s->ds = graphic_console_init(pl110_update_display,
 454                                  pl110_invalidate_display,
 455                                  NULL, NULL, s);
 456     return 0;
 457 }
 458
 459 static int pl110_versatile_init(SysBusDevice *dev)
 460 {
 461     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 462     s->version = PL110_VERSATILE;
 463     return pl110_init(dev);
 464 }
 465
 466 static int pl111_init(SysBusDevice *dev)
 467 {
 468     pl110_state *s = FROM_SYSBUS(pl110_state, dev);
 469     s->version = PL111;
 470     return pl110_init(dev);
 471 }
 472
 473 static void pl110_class_init(ObjectClass *klass, void *data)
 474 {
 475     DeviceClass *dc = DEVICE_CLASS(klass);
 476     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 477
 478     k->init = pl110_init;
 479     dc->no_user = 1;
 480     dc->vmsd = &vmstate_pl110;
 481 }
 482
 483 static const TypeInfo pl110_info = {
 484     .name          = "pl110",
 485     .parent        = TYPE_SYS_BUS_DEVICE,
 486     .instance_size = sizeof(pl110_state),
 487     .class_init    = pl110_class_init,
 488 };
 489
 490 static void pl110_versatile_class_init(ObjectClass *klass, void *data)
 491 {
 492     DeviceClass *dc = DEVICE_CLASS(klass);
 493     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 494
 495     k->init = pl110_versatile_init;
 496     dc->no_user = 1;
 497     dc->vmsd = &vmstate_pl110;
 498 }
 499
 500 static const TypeInfo pl110_versatile_info = {
 501     .name          = "pl110_versatile",
 502     .parent        = TYPE_SYS_BUS_DEVICE,
 503     .instance_size = sizeof(pl110_state),
 504     .class_init    = pl110_versatile_class_init,
 505 };
 506
 507 static void pl111_class_init(ObjectClass *klass, void *data)
 508 {
 509     DeviceClass *dc = DEVICE_CLASS(klass);
 510     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 511
 512     k->init = pl111_init;
 513     dc->no_user = 1;
 514     dc->vmsd = &vmstate_pl110;
 515 }
 516
 517 static const TypeInfo pl111_info = {
 518     .name          = "pl111",
 519     .parent        = TYPE_SYS_BUS_DEVICE,
 520     .instance_size = sizeof(pl110_state),
 521     .class_init    = pl111_class_init,
 522 };
 523
 524 static void pl110_register_types(void)
 525 {
 526     type_register_static(&pl110_info);
 527     type_register_static(&pl110_versatile_info);
 528     type_register_static(&pl111_info);
 529 }
 530
 531 type_init(pl110_register_types)