hw/q35.h

   1 /*
   2  * q35.h
   3  *
   4  * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  20  */
  21
  22 #ifndef HW_Q35_H
  23 #define HW_Q35_H
  24
  25 #include "hw.h"
  26 #include "qemu/range.h"
  27 #include "isa.h"
  28 #include "sysbus.h"
  29 #include "pc.h"
  30 #include "apm.h"
  31 #include "apic.h"
  32 #include "pci/pci.h"
  33 #include "pci/pcie_host.h"
  34 #include "acpi.h"
  35 #include "acpi_ich9.h"
  36 #include "pam.h"
  37
  38 #define TYPE_Q35_HOST_DEVICE "q35-pcihost"
  39 #define Q35_HOST_DEVICE(obj) \
  40      OBJECT_CHECK(Q35PCIHost, (obj), TYPE_Q35_HOST_DEVICE)
  41
  42 #define TYPE_MCH_PCI_DEVICE "mch"
  43 #define MCH_PCI_DEVICE(obj) \
  44      OBJECT_CHECK(MCHPCIState, (obj), TYPE_MCH_PCI_DEVICE)
  45
  46 typedef struct MCHPCIState {
  47     PCIDevice d;
  48     MemoryRegion *ram_memory;
  49     MemoryRegion *pci_address_space;
  50     MemoryRegion *system_memory;
  51     MemoryRegion *address_space_io;
  52     PAMMemoryRegion pam_regions[13];
  53     MemoryRegion smram_region;
  54     MemoryRegion pci_hole;
  55     MemoryRegion pci_hole_64bit;
  56     uint8_t smm_enabled;
  57     ram_addr_t below_4g_mem_size;
  58     ram_addr_t above_4g_mem_size;
  59 } MCHPCIState;
  60
  61 typedef struct Q35PCIHost {
  62     PCIExpressHost host;
  63     MCHPCIState mch;
  64 } Q35PCIHost;
  65
  66 #define Q35_MASK(bit, ms_bit, ls_bit) \
  67 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
  68
  69 /*
  70  * gmch part
  71  */
  72
  73 /* PCI configuration */
  74 #define MCH_HOST_BRIDGE                        "MCH"
  75
  76 #define MCH_HOST_BRIDGE_CONFIG_ADDR            0xcf8
  77 #define MCH_HOST_BRIDGE_CONFIG_DATA            0xcfc
  78
  79 /* D0:F0 configuration space */
  80 #define MCH_HOST_BRIDGE_REVISION_DEFUALT       0x0
  81
  82 #define MCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
  83 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE          8       /* 64bit register */
  84 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT       0xb0000000
  85 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK         Q35_MASK(64, 35, 28)
  86 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK      ((uint64_t)(1 << 26))
  87 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK       ((uint64_t)(1 << 25))
  88 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK   ((uint64_t)(0x3 << 1))
  89 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M   ((uint64_t)(0x0 << 1))
  90 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M   ((uint64_t)(0x1 << 1))
  91 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M    ((uint64_t)(0x2 << 1))
  92 #define MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD    ((uint64_t)(0x3 << 1))
  93 #define MCH_HOST_BRIDGE_PCIEXBAREN             ((uint64_t)1)
  94
  95 #define MCH_HOST_BRIDGE_PAM_NB                 7
  96 #define MCH_HOST_BRIDGE_PAM_SIZE               7
  97 #define MCH_HOST_BRIDGE_PAM0                   0x90
  98 #define MCH_HOST_BRIDGE_PAM_BIOS_AREA          0xf0000
  99 #define MCH_HOST_BRIDGE_PAM_AREA_SIZE          0x10000 /* 16KB */
 100 #define MCH_HOST_BRIDGE_PAM1                   0x91
 101 #define MCH_HOST_BRIDGE_PAM_EXPAN_AREA         0xc0000
 102 #define MCH_HOST_BRIDGE_PAM_EXPAN_SIZE         0x04000
 103 #define MCH_HOST_BRIDGE_PAM2                   0x92
 104 #define MCH_HOST_BRIDGE_PAM3                   0x93
 105 #define MCH_HOST_BRIDGE_PAM4                   0x94
 106 #define MCH_HOST_BRIDGE_PAM_EXBIOS_AREA        0xe0000
 107 #define MCH_HOST_BRIDGE_PAM_EXBIOS_SIZE        0x04000
 108 #define MCH_HOST_BRIDGE_PAM5                   0x95
 109 #define MCH_HOST_BRIDGE_PAM6                   0x96
 110 #define MCH_HOST_BRIDGE_PAM_WE_HI              ((uint8_t)(0x2 << 4))
 111 #define MCH_HOST_BRIDGE_PAM_RE_HI              ((uint8_t)(0x1 << 4))
 112 #define MCH_HOST_BRIDGE_PAM_HI_MASK            ((uint8_t)(0x3 << 4))
 113 #define MCH_HOST_BRIDGE_PAM_WE_LO              ((uint8_t)0x2)
 114 #define MCH_HOST_BRIDGE_PAM_RE_LO              ((uint8_t)0x1)
 115 #define MCH_HOST_BRIDGE_PAM_LO_MASK            ((uint8_t)0x3)
 116 #define MCH_HOST_BRIDGE_PAM_WE                 ((uint8_t)0x2)
 117 #define MCH_HOST_BRIDGE_PAM_RE                 ((uint8_t)0x1)
 118 #define MCH_HOST_BRIDGE_PAM_MASK               ((uint8_t)0x3)
 119
 120 #define MCH_HOST_BRDIGE_SMRAM                  0x9d
 121 #define MCH_HOST_BRDIGE_SMRAM_SIZE             1
 122 #define MCH_HOST_BRIDGE_SMRAM_DEFAULT          ((uint8_t)0x2)
 123 #define MCH_HOST_BRIDGE_SMRAM_D_OPEN           ((uint8_t)(1 << 6))
 124 #define MCH_HOST_BRIDGE_SMRAM_D_CLS            ((uint8_t)(1 << 5))
 125 #define MCH_HOST_BRIDGE_SMRAM_D_LCK            ((uint8_t)(1 << 4))
 126 #define MCH_HOST_BRIDGE_SMRAM_G_SMRAME         ((uint8_t)(1 << 3))
 127 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK  ((uint8_t)0x7)
 128 #define MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG       ((uint8_t)0x2)  /* hardwired to b010 */
 129 #define MCH_HOST_BRIDGE_SMRAM_C_BASE           0xa0000
 130 #define MCH_HOST_BRIDGE_SMRAM_C_END            0xc0000
 131 #define MCH_HOST_BRIDGE_SMRAM_C_SIZE           0x20000
 132 #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END  0x100000
 133
 134 #define MCH_HOST_BRIDGE_ESMRAMC                0x9e
 135 #define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME       ((uint8_t)(1 << 6))
 136 #define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR        ((uint8_t)(1 << 5))
 137 #define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE       ((uint8_t)(1 << 4))
 138 #define MCH_HOST_BRDIGE_ESMRAMC_SM_L1          ((uint8_t)(1 << 3))
 139 #define MCH_HOST_BRDIGE_ESMRAMC_SM_L2          ((uint8_t)(1 << 2))
 140 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK   ((uint8_t)(0x3 << 1))
 141 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB    ((uint8_t)(0x0 << 1))
 142 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB    ((uint8_t)(0x1 << 1))
 143 #define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB    ((uint8_t)(0x2 << 1))
 144 #define MCH_HOST_BRDIGE_ESMRAMC_T_EN           ((uint8_t)1)
 145
 146 /* D1:F0 PCIE* port*/
 147 #define MCH_PCIE_DEV                           1
 148 #define MCH_PCIE_FUNC                          0
 149
 150 #endif /* HW_Q35_H */