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target-i386: Use mulu2 and muls2
[qemu/pbrook.git] / target-ppc / translate.c
blob80d5366d27ea37b9617194ead7b058a8b5d73319
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 8*5 /* CRF */];
55 static TCGv cpu_gpr[32];
56 #if !defined(TARGET_PPC64)
57 static TCGv cpu_gprh[32];
58 #endif
59 static TCGv_i64 cpu_fpr[32];
60 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
61 static TCGv_i32 cpu_crf[8];
62 static TCGv cpu_nip;
63 static TCGv cpu_msr;
64 static TCGv cpu_ctr;
65 static TCGv cpu_lr;
66 #if defined(TARGET_PPC64)
67 static TCGv cpu_cfar;
68 #endif
69 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
70 static TCGv cpu_reserve;
71 static TCGv cpu_fpscr;
72 static TCGv_i32 cpu_access_type;
73
74 #include "exec/gen-icount.h"
75
76 void ppc_translate_init(void)
77 {
78 int i;
79 char* p;
80 size_t cpu_reg_names_size;
81 static int done_init = 0;
82
83 if (done_init)
84 return;
85
86 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
87
88 p = cpu_reg_names;
89 cpu_reg_names_size = sizeof(cpu_reg_names);
90
91 for (i = 0; i < 8; i++) {
92 snprintf(p, cpu_reg_names_size, "crf%d", i);
93 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUPPCState, crf[i]), p);
95 p += 5;
96 cpu_reg_names_size -= 5;
97 }
98
99 for (i = 0; i < 32; i++) {
100 snprintf(p, cpu_reg_names_size, "r%d", i);
101 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
102 offsetof(CPUPPCState, gpr[i]), p);
103 p += (i < 10) ? 3 : 4;
104 cpu_reg_names_size -= (i < 10) ? 3 : 4;
105 #if !defined(TARGET_PPC64)
106 snprintf(p, cpu_reg_names_size, "r%dH", i);
107 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
108 offsetof(CPUPPCState, gprh[i]), p);
109 p += (i < 10) ? 4 : 5;
110 cpu_reg_names_size -= (i < 10) ? 4 : 5;
111 #endif
112
113 snprintf(p, cpu_reg_names_size, "fp%d", i);
114 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
115 offsetof(CPUPPCState, fpr[i]), p);
116 p += (i < 10) ? 4 : 5;
117 cpu_reg_names_size -= (i < 10) ? 4 : 5;
118
119 snprintf(p, cpu_reg_names_size, "avr%dH", i);
120 #ifdef HOST_WORDS_BIGENDIAN
121 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
122 offsetof(CPUPPCState, avr[i].u64[0]), p);
123 #else
124 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
125 offsetof(CPUPPCState, avr[i].u64[1]), p);
126 #endif
127 p += (i < 10) ? 6 : 7;
128 cpu_reg_names_size -= (i < 10) ? 6 : 7;
129
130 snprintf(p, cpu_reg_names_size, "avr%dL", i);
131 #ifdef HOST_WORDS_BIGENDIAN
132 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
133 offsetof(CPUPPCState, avr[i].u64[1]), p);
134 #else
135 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
136 offsetof(CPUPPCState, avr[i].u64[0]), p);
137 #endif
138 p += (i < 10) ? 6 : 7;
139 cpu_reg_names_size -= (i < 10) ? 6 : 7;
140 }
141
142 cpu_nip = tcg_global_mem_new(TCG_AREG0,
143 offsetof(CPUPPCState, nip), "nip");
144
145 cpu_msr = tcg_global_mem_new(TCG_AREG0,
146 offsetof(CPUPPCState, msr), "msr");
147
148 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
149 offsetof(CPUPPCState, ctr), "ctr");
150
151 cpu_lr = tcg_global_mem_new(TCG_AREG0,
152 offsetof(CPUPPCState, lr), "lr");
153
154 #if defined(TARGET_PPC64)
155 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, cfar), "cfar");
157 #endif
158
159 cpu_xer = tcg_global_mem_new(TCG_AREG0,
160 offsetof(CPUPPCState, xer), "xer");
161 cpu_so = tcg_global_mem_new(TCG_AREG0,
162 offsetof(CPUPPCState, so), "SO");
163 cpu_ov = tcg_global_mem_new(TCG_AREG0,
164 offsetof(CPUPPCState, ov), "OV");
165 cpu_ca = tcg_global_mem_new(TCG_AREG0,
166 offsetof(CPUPPCState, ca), "CA");
167
168 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, reserve_addr),
170 "reserve_addr");
171
172 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, fpscr), "fpscr");
174
175 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
176 offsetof(CPUPPCState, access_type), "access_type");
177
178 /* register helpers */
179 #define GEN_HELPER 2
180 #include "helper.h"
181
182 done_init = 1;
183 }
184
185 /* internal defines */
186 typedef struct DisasContext {
187 struct TranslationBlock *tb;
188 target_ulong nip;
189 uint32_t opcode;
190 uint32_t exception;
191 /* Routine used to access memory */
192 int mem_idx;
193 int access_type;
194 /* Translation flags */
195 int le_mode;
196 #if defined(TARGET_PPC64)
197 int sf_mode;
198 int has_cfar;
199 #endif
200 int fpu_enabled;
201 int altivec_enabled;
202 int spe_enabled;
203 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
204 int singlestep_enabled;
205 } DisasContext;
206
207 struct opc_handler_t {
208 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
209 uint32_t inval1;
210 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
211 uint32_t inval2;
212 /* instruction type */
213 uint64_t type;
214 /* extended instruction type */
215 uint64_t type2;
216 /* handler */
217 void (*handler)(DisasContext *ctx);
218 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
219 const char *oname;
220 #endif
221 #if defined(DO_PPC_STATISTICS)
222 uint64_t count;
223 #endif
224 };
225
226 static inline void gen_reset_fpstatus(void)
227 {
228 gen_helper_reset_fpstatus(cpu_env);
229 }
230
231 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
232 {
233 TCGv_i32 t0 = tcg_temp_new_i32();
234
235 if (set_fprf != 0) {
236 /* This case might be optimized later */
237 tcg_gen_movi_i32(t0, 1);
238 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
239 if (unlikely(set_rc)) {
240 tcg_gen_mov_i32(cpu_crf[1], t0);
241 }
242 gen_helper_float_check_status(cpu_env);
243 } else if (unlikely(set_rc)) {
244 /* We always need to compute fpcc */
245 tcg_gen_movi_i32(t0, 0);
246 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
247 tcg_gen_mov_i32(cpu_crf[1], t0);
248 }
249
250 tcg_temp_free_i32(t0);
251 }
252
253 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
254 {
255 if (ctx->access_type != access_type) {
256 tcg_gen_movi_i32(cpu_access_type, access_type);
257 ctx->access_type = access_type;
258 }
259 }
260
261 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
262 {
263 #if defined(TARGET_PPC64)
264 if (ctx->sf_mode)
265 tcg_gen_movi_tl(cpu_nip, nip);
266 else
267 #endif
268 tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
269 }
270
271 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
272 {
273 TCGv_i32 t0, t1;
274 if (ctx->exception == POWERPC_EXCP_NONE) {
275 gen_update_nip(ctx, ctx->nip);
276 }
277 t0 = tcg_const_i32(excp);
278 t1 = tcg_const_i32(error);
279 gen_helper_raise_exception_err(cpu_env, t0, t1);
280 tcg_temp_free_i32(t0);
281 tcg_temp_free_i32(t1);
282 ctx->exception = (excp);
283 }
284
285 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
286 {
287 TCGv_i32 t0;
288 if (ctx->exception == POWERPC_EXCP_NONE) {
289 gen_update_nip(ctx, ctx->nip);
290 }
291 t0 = tcg_const_i32(excp);
292 gen_helper_raise_exception(cpu_env, t0);
293 tcg_temp_free_i32(t0);
294 ctx->exception = (excp);
295 }
296
297 static inline void gen_debug_exception(DisasContext *ctx)
298 {
299 TCGv_i32 t0;
300
301 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
302 (ctx->exception != POWERPC_EXCP_SYNC)) {
303 gen_update_nip(ctx, ctx->nip);
304 }
305 t0 = tcg_const_i32(EXCP_DEBUG);
306 gen_helper_raise_exception(cpu_env, t0);
307 tcg_temp_free_i32(t0);
308 }
309
310 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
311 {
312 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
313 }
314
315 /* Stop translation */
316 static inline void gen_stop_exception(DisasContext *ctx)
317 {
318 gen_update_nip(ctx, ctx->nip);
319 ctx->exception = POWERPC_EXCP_STOP;
320 }
321
322 /* No need to update nip here, as execution flow will change */
323 static inline void gen_sync_exception(DisasContext *ctx)
324 {
325 ctx->exception = POWERPC_EXCP_SYNC;
326 }
327
328 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
329 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
330
331 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
332 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
333
334 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
335 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
336
337 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
338 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
339
340 typedef struct opcode_t {
341 unsigned char opc1, opc2, opc3;
342 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
343 unsigned char pad[5];
344 #else
345 unsigned char pad[1];
346 #endif
347 opc_handler_t handler;
348 const char *oname;
349 } opcode_t;
350
351 /*****************************************************************************/
352 /*** Instruction decoding ***/
353 #define EXTRACT_HELPER(name, shift, nb) \
354 static inline uint32_t name(uint32_t opcode) \
355 { \
356 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
357 }
358
359 #define EXTRACT_SHELPER(name, shift, nb) \
360 static inline int32_t name(uint32_t opcode) \
361 { \
362 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
363 }
364
365 /* Opcode part 1 */
366 EXTRACT_HELPER(opc1, 26, 6);
367 /* Opcode part 2 */
368 EXTRACT_HELPER(opc2, 1, 5);
369 /* Opcode part 3 */
370 EXTRACT_HELPER(opc3, 6, 5);
371 /* Update Cr0 flags */
372 EXTRACT_HELPER(Rc, 0, 1);
373 /* Destination */
374 EXTRACT_HELPER(rD, 21, 5);
375 /* Source */
376 EXTRACT_HELPER(rS, 21, 5);
377 /* First operand */
378 EXTRACT_HELPER(rA, 16, 5);
379 /* Second operand */
380 EXTRACT_HELPER(rB, 11, 5);
381 /* Third operand */
382 EXTRACT_HELPER(rC, 6, 5);
383 /*** Get CRn ***/
384 EXTRACT_HELPER(crfD, 23, 3);
385 EXTRACT_HELPER(crfS, 18, 3);
386 EXTRACT_HELPER(crbD, 21, 5);
387 EXTRACT_HELPER(crbA, 16, 5);
388 EXTRACT_HELPER(crbB, 11, 5);
389 /* SPR / TBL */
390 EXTRACT_HELPER(_SPR, 11, 10);
391 static inline uint32_t SPR(uint32_t opcode)
392 {
393 uint32_t sprn = _SPR(opcode);
394
395 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
396 }
397 /*** Get constants ***/
398 EXTRACT_HELPER(IMM, 12, 8);
399 /* 16 bits signed immediate value */
400 EXTRACT_SHELPER(SIMM, 0, 16);
401 /* 16 bits unsigned immediate value */
402 EXTRACT_HELPER(UIMM, 0, 16);
403 /* 5 bits signed immediate value */
404 EXTRACT_HELPER(SIMM5, 16, 5);
405 /* 5 bits signed immediate value */
406 EXTRACT_HELPER(UIMM5, 16, 5);
407 /* Bit count */
408 EXTRACT_HELPER(NB, 11, 5);
409 /* Shift count */
410 EXTRACT_HELPER(SH, 11, 5);
411 /* Vector shift count */
412 EXTRACT_HELPER(VSH, 6, 4);
413 /* Mask start */
414 EXTRACT_HELPER(MB, 6, 5);
415 /* Mask end */
416 EXTRACT_HELPER(ME, 1, 5);
417 /* Trap operand */
418 EXTRACT_HELPER(TO, 21, 5);
419
420 EXTRACT_HELPER(CRM, 12, 8);
421 EXTRACT_HELPER(FM, 17, 8);
422 EXTRACT_HELPER(SR, 16, 4);
423 EXTRACT_HELPER(FPIMM, 12, 4);
424
425 /*** Jump target decoding ***/
426 /* Displacement */
427 EXTRACT_SHELPER(d, 0, 16);
428 /* Immediate address */
429 static inline target_ulong LI(uint32_t opcode)
430 {
431 return (opcode >> 0) & 0x03FFFFFC;
432 }
433
434 static inline uint32_t BD(uint32_t opcode)
435 {
436 return (opcode >> 0) & 0xFFFC;
437 }
438
439 EXTRACT_HELPER(BO, 21, 5);
440 EXTRACT_HELPER(BI, 16, 5);
441 /* Absolute/relative address */
442 EXTRACT_HELPER(AA, 1, 1);
443 /* Link */
444 EXTRACT_HELPER(LK, 0, 1);
445
446 /* Create a mask between <start> and <end> bits */
447 static inline target_ulong MASK(uint32_t start, uint32_t end)
448 {
449 target_ulong ret;
450
451 #if defined(TARGET_PPC64)
452 if (likely(start == 0)) {
453 ret = UINT64_MAX << (63 - end);
454 } else if (likely(end == 63)) {
455 ret = UINT64_MAX >> start;
456 }
457 #else
458 if (likely(start == 0)) {
459 ret = UINT32_MAX << (31 - end);
460 } else if (likely(end == 31)) {
461 ret = UINT32_MAX >> start;
462 }
463 #endif
464 else {
465 ret = (((target_ulong)(-1ULL)) >> (start)) ^
466 (((target_ulong)(-1ULL) >> (end)) >> 1);
467 if (unlikely(start > end))
468 return ~ret;
469 }
470
471 return ret;
472 }
473
474 /*****************************************************************************/
475 /* PowerPC instructions table */
476
477 #if defined(DO_PPC_STATISTICS)
478 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
479 { \
480 .opc1 = op1, \
481 .opc2 = op2, \
482 .opc3 = op3, \
483 .pad = { 0, }, \
484 .handler = { \
485 .inval1 = invl, \
486 .type = _typ, \
487 .type2 = _typ2, \
488 .handler = &gen_##name, \
489 .oname = stringify(name), \
490 }, \
491 .oname = stringify(name), \
492 }
493 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
494 { \
495 .opc1 = op1, \
496 .opc2 = op2, \
497 .opc3 = op3, \
498 .pad = { 0, }, \
499 .handler = { \
500 .inval1 = invl1, \
501 .inval2 = invl2, \
502 .type = _typ, \
503 .type2 = _typ2, \
504 .handler = &gen_##name, \
505 .oname = stringify(name), \
506 }, \
507 .oname = stringify(name), \
508 }
509 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
510 { \
511 .opc1 = op1, \
512 .opc2 = op2, \
513 .opc3 = op3, \
514 .pad = { 0, }, \
515 .handler = { \
516 .inval1 = invl, \
517 .type = _typ, \
518 .type2 = _typ2, \
519 .handler = &gen_##name, \
520 .oname = onam, \
521 }, \
522 .oname = onam, \
523 }
524 #else
525 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
526 { \
527 .opc1 = op1, \
528 .opc2 = op2, \
529 .opc3 = op3, \
530 .pad = { 0, }, \
531 .handler = { \
532 .inval1 = invl, \
533 .type = _typ, \
534 .type2 = _typ2, \
535 .handler = &gen_##name, \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl1, \
547 .inval2 = invl2, \
548 .type = _typ, \
549 .type2 = _typ2, \
550 .handler = &gen_##name, \
551 }, \
552 .oname = stringify(name), \
553 }
554 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
555 { \
556 .opc1 = op1, \
557 .opc2 = op2, \
558 .opc3 = op3, \
559 .pad = { 0, }, \
560 .handler = { \
561 .inval1 = invl, \
562 .type = _typ, \
563 .type2 = _typ2, \
564 .handler = &gen_##name, \
565 }, \
566 .oname = onam, \
567 }
568 #endif
569
570 /* SPR load/store helpers */
571 static inline void gen_load_spr(TCGv t, int reg)
572 {
573 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
574 }
575
576 static inline void gen_store_spr(int reg, TCGv t)
577 {
578 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
579 }
580
581 /* Invalid instruction */
582 static void gen_invalid(DisasContext *ctx)
583 {
584 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
585 }
586
587 static opc_handler_t invalid_handler = {
588 .inval1 = 0xFFFFFFFF,
589 .inval2 = 0xFFFFFFFF,
590 .type = PPC_NONE,
591 .type2 = PPC_NONE,
592 .handler = gen_invalid,
593 };
594
595 /*** Integer comparison ***/
596
597 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
598 {
599 TCGv t0 = tcg_temp_new();
600 TCGv_i32 t1 = tcg_temp_new_i32();
601
602 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
603
604 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
605 tcg_gen_trunc_tl_i32(t1, t0);
606 tcg_gen_shli_i32(t1, t1, CRF_LT);
607 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
608
609 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
610 tcg_gen_trunc_tl_i32(t1, t0);
611 tcg_gen_shli_i32(t1, t1, CRF_GT);
612 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
613
614 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
615 tcg_gen_trunc_tl_i32(t1, t0);
616 tcg_gen_shli_i32(t1, t1, CRF_EQ);
617 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
618
619 tcg_temp_free(t0);
620 tcg_temp_free_i32(t1);
621 }
622
623 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
624 {
625 TCGv t0 = tcg_const_tl(arg1);
626 gen_op_cmp(arg0, t0, s, crf);
627 tcg_temp_free(t0);
628 }
629
630 #if defined(TARGET_PPC64)
631 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
632 {
633 TCGv t0, t1;
634 t0 = tcg_temp_new();
635 t1 = tcg_temp_new();
636 if (s) {
637 tcg_gen_ext32s_tl(t0, arg0);
638 tcg_gen_ext32s_tl(t1, arg1);
639 } else {
640 tcg_gen_ext32u_tl(t0, arg0);
641 tcg_gen_ext32u_tl(t1, arg1);
642 }
643 gen_op_cmp(t0, t1, s, crf);
644 tcg_temp_free(t1);
645 tcg_temp_free(t0);
646 }
647
648 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
649 {
650 TCGv t0 = tcg_const_tl(arg1);
651 gen_op_cmp32(arg0, t0, s, crf);
652 tcg_temp_free(t0);
653 }
654 #endif
655
656 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
657 {
658 #if defined(TARGET_PPC64)
659 if (!(ctx->sf_mode))
660 gen_op_cmpi32(reg, 0, 1, 0);
661 else
662 #endif
663 gen_op_cmpi(reg, 0, 1, 0);
664 }
665
666 /* cmp */
667 static void gen_cmp(DisasContext *ctx)
668 {
669 #if defined(TARGET_PPC64)
670 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
671 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
672 1, crfD(ctx->opcode));
673 else
674 #endif
675 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
676 1, crfD(ctx->opcode));
677 }
678
679 /* cmpi */
680 static void gen_cmpi(DisasContext *ctx)
681 {
682 #if defined(TARGET_PPC64)
683 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
684 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
685 1, crfD(ctx->opcode));
686 else
687 #endif
688 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
689 1, crfD(ctx->opcode));
690 }
691
692 /* cmpl */
693 static void gen_cmpl(DisasContext *ctx)
694 {
695 #if defined(TARGET_PPC64)
696 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
697 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 0, crfD(ctx->opcode));
699 else
700 #endif
701 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
702 0, crfD(ctx->opcode));
703 }
704
705 /* cmpli */
706 static void gen_cmpli(DisasContext *ctx)
707 {
708 #if defined(TARGET_PPC64)
709 if (!(ctx->sf_mode && (ctx->opcode & 0x00200000)))
710 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
711 0, crfD(ctx->opcode));
712 else
713 #endif
714 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
715 0, crfD(ctx->opcode));
716 }
717
718 /* isel (PowerPC 2.03 specification) */
719 static void gen_isel(DisasContext *ctx)
720 {
721 int l1, l2;
722 uint32_t bi = rC(ctx->opcode);
723 uint32_t mask;
724 TCGv_i32 t0;
725
726 l1 = gen_new_label();
727 l2 = gen_new_label();
728
729 mask = 1 << (3 - (bi & 0x03));
730 t0 = tcg_temp_new_i32();
731 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
732 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
733 if (rA(ctx->opcode) == 0)
734 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
735 else
736 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
737 tcg_gen_br(l2);
738 gen_set_label(l1);
739 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
740 gen_set_label(l2);
741 tcg_temp_free_i32(t0);
742 }
743
744 /*** Integer arithmetic ***/
745
746 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
747 TCGv arg1, TCGv arg2, int sub)
748 {
749 TCGv t0 = tcg_temp_new();
750
751 tcg_gen_xor_tl(cpu_ov, arg0, arg1);
752 tcg_gen_xor_tl(t0, arg1, arg2);
753 if (sub) {
754 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
755 } else {
756 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
757 }
758 tcg_temp_free(t0);
759 #if defined(TARGET_PPC64)
760 if (!ctx->sf_mode) {
761 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
762 }
763 #endif
764 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
765 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
766 }
767
768 /* Common add function */
769 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
770 TCGv arg2, bool add_ca, bool compute_ca,
771 bool compute_ov, bool compute_rc0)
772 {
773 TCGv t0 = ret;
774
775 if (((compute_ca && add_ca) || compute_ov)
776 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
777 t0 = tcg_temp_new();
778 }
779
780 if (compute_ca) {
781 TCGv zero = tcg_const_tl(0);
782 if (add_ca) {
783 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
784 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
785 } else {
786 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
787 }
788 tcg_temp_free(zero);
789 } else {
790 tcg_gen_add_tl(t0, arg1, arg2);
791 if (add_ca) {
792 tcg_gen_add_tl(t0, t0, cpu_ca);
793 }
794 }
795
796 if (compute_ov) {
797 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
798 }
799 if (unlikely(compute_rc0)) {
800 gen_set_Rc0(ctx, t0);
801 }
802
803 if (!TCGV_EQUAL(t0, ret)) {
804 tcg_gen_mov_tl(ret, t0);
805 tcg_temp_free(t0);
806 }
807 }
808 /* Add functions with two operands */
809 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
810 static void glue(gen_, name)(DisasContext *ctx) \
811 { \
812 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
813 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
814 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
815 }
816 /* Add functions with one operand and one immediate */
817 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
818 add_ca, compute_ca, compute_ov) \
819 static void glue(gen_, name)(DisasContext *ctx) \
820 { \
821 TCGv t0 = tcg_const_tl(const_val); \
822 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
823 cpu_gpr[rA(ctx->opcode)], t0, \
824 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
825 tcg_temp_free(t0); \
826 }
827
828 /* add add. addo addo. */
829 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
830 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
831 /* addc addc. addco addco. */
832 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
833 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
834 /* adde adde. addeo addeo. */
835 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
836 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
837 /* addme addme. addmeo addmeo. */
838 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
839 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
840 /* addze addze. addzeo addzeo.*/
841 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
842 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
843 /* addi */
844 static void gen_addi(DisasContext *ctx)
845 {
846 target_long simm = SIMM(ctx->opcode);
847
848 if (rA(ctx->opcode) == 0) {
849 /* li case */
850 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
851 } else {
852 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
853 cpu_gpr[rA(ctx->opcode)], simm);
854 }
855 }
856 /* addic addic.*/
857 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
858 {
859 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
860 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
861 c, 0, 1, 0, compute_rc0);
862 tcg_temp_free(c);
863 }
864
865 static void gen_addic(DisasContext *ctx)
866 {
867 gen_op_addic(ctx, 0);
868 }
869
870 static void gen_addic_(DisasContext *ctx)
871 {
872 gen_op_addic(ctx, 1);
873 }
874
875 /* addis */
876 static void gen_addis(DisasContext *ctx)
877 {
878 target_long simm = SIMM(ctx->opcode);
879
880 if (rA(ctx->opcode) == 0) {
881 /* lis case */
882 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
883 } else {
884 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
885 cpu_gpr[rA(ctx->opcode)], simm << 16);
886 }
887 }
888
889 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
890 TCGv arg2, int sign, int compute_ov)
891 {
892 int l1 = gen_new_label();
893 int l2 = gen_new_label();
894 TCGv_i32 t0 = tcg_temp_local_new_i32();
895 TCGv_i32 t1 = tcg_temp_local_new_i32();
896
897 tcg_gen_trunc_tl_i32(t0, arg1);
898 tcg_gen_trunc_tl_i32(t1, arg2);
899 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
900 if (sign) {
901 int l3 = gen_new_label();
902 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
903 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
904 gen_set_label(l3);
905 tcg_gen_div_i32(t0, t0, t1);
906 } else {
907 tcg_gen_divu_i32(t0, t0, t1);
908 }
909 if (compute_ov) {
910 tcg_gen_movi_tl(cpu_ov, 0);
911 }
912 tcg_gen_br(l2);
913 gen_set_label(l1);
914 if (sign) {
915 tcg_gen_sari_i32(t0, t0, 31);
916 } else {
917 tcg_gen_movi_i32(t0, 0);
918 }
919 if (compute_ov) {
920 tcg_gen_movi_tl(cpu_ov, 1);
921 tcg_gen_movi_tl(cpu_so, 1);
922 }
923 gen_set_label(l2);
924 tcg_gen_extu_i32_tl(ret, t0);
925 tcg_temp_free_i32(t0);
926 tcg_temp_free_i32(t1);
927 if (unlikely(Rc(ctx->opcode) != 0))
928 gen_set_Rc0(ctx, ret);
929 }
930 /* Div functions */
931 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
932 static void glue(gen_, name)(DisasContext *ctx) \
933 { \
934 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
935 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
936 sign, compute_ov); \
937 }
938 /* divwu divwu. divwuo divwuo. */
939 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
940 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
941 /* divw divw. divwo divwo. */
942 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
943 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
944 #if defined(TARGET_PPC64)
945 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
946 TCGv arg2, int sign, int compute_ov)
947 {
948 int l1 = gen_new_label();
949 int l2 = gen_new_label();
950
951 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
952 if (sign) {
953 int l3 = gen_new_label();
954 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
955 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
956 gen_set_label(l3);
957 tcg_gen_div_i64(ret, arg1, arg2);
958 } else {
959 tcg_gen_divu_i64(ret, arg1, arg2);
960 }
961 if (compute_ov) {
962 tcg_gen_movi_tl(cpu_ov, 0);
963 }
964 tcg_gen_br(l2);
965 gen_set_label(l1);
966 if (sign) {
967 tcg_gen_sari_i64(ret, arg1, 63);
968 } else {
969 tcg_gen_movi_i64(ret, 0);
970 }
971 if (compute_ov) {
972 tcg_gen_movi_tl(cpu_ov, 1);
973 tcg_gen_movi_tl(cpu_so, 1);
974 }
975 gen_set_label(l2);
976 if (unlikely(Rc(ctx->opcode) != 0))
977 gen_set_Rc0(ctx, ret);
978 }
979 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
980 static void glue(gen_, name)(DisasContext *ctx) \
981 { \
982 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
983 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
984 sign, compute_ov); \
985 }
986 /* divwu divwu. divwuo divwuo. */
987 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
988 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
989 /* divw divw. divwo divwo. */
990 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
991 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
992 #endif
993
994 /* mulhw mulhw. */
995 static void gen_mulhw(DisasContext *ctx)
996 {
997 TCGv_i32 t0 = tcg_temp_new_i32();
998 TCGv_i32 t1 = tcg_temp_new_i32();
999
1000 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1001 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1002 tcg_gen_muls2_i32(t0, t1, t0, t1);
1003 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1004 tcg_temp_free_i32(t0);
1005 tcg_temp_free_i32(t1);
1006 if (unlikely(Rc(ctx->opcode) != 0))
1007 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1008 }
1009
1010 /* mulhwu mulhwu. */
1011 static void gen_mulhwu(DisasContext *ctx)
1012 {
1013 TCGv_i32 t0 = tcg_temp_new_i32();
1014 TCGv_i32 t1 = tcg_temp_new_i32();
1015
1016 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1017 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1018 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1019 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1020 tcg_temp_free_i32(t0);
1021 tcg_temp_free_i32(t1);
1022 if (unlikely(Rc(ctx->opcode) != 0))
1023 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1024 }
1025
1026 /* mullw mullw. */
1027 static void gen_mullw(DisasContext *ctx)
1028 {
1029 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1030 cpu_gpr[rB(ctx->opcode)]);
1031 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1032 if (unlikely(Rc(ctx->opcode) != 0))
1033 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1034 }
1035
1036 /* mullwo mullwo. */
1037 static void gen_mullwo(DisasContext *ctx)
1038 {
1039 TCGv_i32 t0 = tcg_temp_new_i32();
1040 TCGv_i32 t1 = tcg_temp_new_i32();
1041
1042 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1043 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1044 tcg_gen_muls2_i32(t0, t1, t0, t1);
1045 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1046
1047 tcg_gen_sari_i32(t0, t0, 31);
1048 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1049 tcg_gen_extu_i32_tl(cpu_ov, t0);
1050 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1051
1052 tcg_temp_free_i32(t0);
1053 tcg_temp_free_i32(t1);
1054 if (unlikely(Rc(ctx->opcode) != 0))
1055 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1056 }
1057
1058 /* mulli */
1059 static void gen_mulli(DisasContext *ctx)
1060 {
1061 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1062 SIMM(ctx->opcode));
1063 }
1064
1065 #if defined(TARGET_PPC64)
1066 /* mulhd mulhd. */
1067 static void gen_mulhd(DisasContext *ctx)
1068 {
1069 TCGv lo = tcg_temp_new();
1070 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1071 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1072 tcg_temp_free(lo);
1073 if (unlikely(Rc(ctx->opcode) != 0)) {
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076 }
1077
1078 /* mulhdu mulhdu. */
1079 static void gen_mulhdu(DisasContext *ctx)
1080 {
1081 TCGv lo = tcg_temp_new();
1082 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1083 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1084 tcg_temp_free(lo);
1085 if (unlikely(Rc(ctx->opcode) != 0)) {
1086 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1087 }
1088 }
1089
1090 /* mulld mulld. */
1091 static void gen_mulld(DisasContext *ctx)
1092 {
1093 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1094 cpu_gpr[rB(ctx->opcode)]);
1095 if (unlikely(Rc(ctx->opcode) != 0))
1096 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1097 }
1098
1099 /* mulldo mulldo. */
1100 static void gen_mulldo(DisasContext *ctx)
1101 {
1102 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1103 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1104 if (unlikely(Rc(ctx->opcode) != 0)) {
1105 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1106 }
1107 }
1108 #endif
1109
1110 /* Common subf function */
1111 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1112 TCGv arg2, bool add_ca, bool compute_ca,
1113 bool compute_ov, bool compute_rc0)
1114 {
1115 TCGv t0 = ret;
1116
1117 if (((add_ca && compute_ca) || compute_ov)
1118 && (TCGV_EQUAL(ret, arg1) || TCGV_EQUAL(ret, arg2))) {
1119 t0 = tcg_temp_new();
1120 }
1121
1122 if (add_ca) {
1123 /* dest = ~arg1 + arg2 + ca. */
1124 if (compute_ca) {
1125 TCGv zero, inv1 = tcg_temp_new();
1126 tcg_gen_not_tl(inv1, arg1);
1127 zero = tcg_const_tl(0);
1128 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1129 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1130 tcg_temp_free(zero);
1131 tcg_temp_free(inv1);
1132 } else {
1133 tcg_gen_sub_tl(t0, arg2, arg1);
1134 tcg_gen_add_tl(t0, t0, cpu_ca);
1135 tcg_gen_subi_tl(t0, t0, 1);
1136 }
1137 } else {
1138 if (compute_ca) {
1139 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1140 }
1141 tcg_gen_sub_tl(t0, arg2, arg1);
1142 }
1143
1144 if (compute_ov) {
1145 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1146 }
1147 if (unlikely(compute_rc0)) {
1148 gen_set_Rc0(ctx, t0);
1149 }
1150
1151 if (!TCGV_EQUAL(t0, ret)) {
1152 tcg_gen_mov_tl(ret, t0);
1153 tcg_temp_free(t0);
1154 }
1155 }
1156 /* Sub functions with Two operands functions */
1157 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1158 static void glue(gen_, name)(DisasContext *ctx) \
1159 { \
1160 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1161 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1162 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1163 }
1164 /* Sub functions with one operand and one immediate */
1165 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1166 add_ca, compute_ca, compute_ov) \
1167 static void glue(gen_, name)(DisasContext *ctx) \
1168 { \
1169 TCGv t0 = tcg_const_tl(const_val); \
1170 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1171 cpu_gpr[rA(ctx->opcode)], t0, \
1172 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1173 tcg_temp_free(t0); \
1174 }
1175 /* subf subf. subfo subfo. */
1176 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1177 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1178 /* subfc subfc. subfco subfco. */
1179 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1180 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1181 /* subfe subfe. subfeo subfo. */
1182 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1183 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1184 /* subfme subfme. subfmeo subfmeo. */
1185 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1186 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1187 /* subfze subfze. subfzeo subfzeo.*/
1188 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1189 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1190
1191 /* subfic */
1192 static void gen_subfic(DisasContext *ctx)
1193 {
1194 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1195 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1196 c, 0, 1, 0, 0);
1197 tcg_temp_free(c);
1198 }
1199
1200 /* neg neg. nego nego. */
1201 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1202 {
1203 TCGv zero = tcg_const_tl(0);
1204 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1205 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1206 tcg_temp_free(zero);
1207 }
1208
1209 static void gen_neg(DisasContext *ctx)
1210 {
1211 gen_op_arith_neg(ctx, 0);
1212 }
1213
1214 static void gen_nego(DisasContext *ctx)
1215 {
1216 gen_op_arith_neg(ctx, 1);
1217 }
1218
1219 /*** Integer logical ***/
1220 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1221 static void glue(gen_, name)(DisasContext *ctx) \
1222 { \
1223 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1224 cpu_gpr[rB(ctx->opcode)]); \
1225 if (unlikely(Rc(ctx->opcode) != 0)) \
1226 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1227 }
1228
1229 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1230 static void glue(gen_, name)(DisasContext *ctx) \
1231 { \
1232 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1233 if (unlikely(Rc(ctx->opcode) != 0)) \
1234 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1235 }
1236
1237 /* and & and. */
1238 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1239 /* andc & andc. */
1240 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1241
1242 /* andi. */
1243 static void gen_andi_(DisasContext *ctx)
1244 {
1245 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1246 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1247 }
1248
1249 /* andis. */
1250 static void gen_andis_(DisasContext *ctx)
1251 {
1252 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1253 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1254 }
1255
1256 /* cntlzw */
1257 static void gen_cntlzw(DisasContext *ctx)
1258 {
1259 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1260 if (unlikely(Rc(ctx->opcode) != 0))
1261 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1262 }
1263 /* eqv & eqv. */
1264 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1265 /* extsb & extsb. */
1266 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1267 /* extsh & extsh. */
1268 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1269 /* nand & nand. */
1270 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1271 /* nor & nor. */
1272 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1273
1274 /* or & or. */
1275 static void gen_or(DisasContext *ctx)
1276 {
1277 int rs, ra, rb;
1278
1279 rs = rS(ctx->opcode);
1280 ra = rA(ctx->opcode);
1281 rb = rB(ctx->opcode);
1282 /* Optimisation for mr. ri case */
1283 if (rs != ra || rs != rb) {
1284 if (rs != rb)
1285 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1286 else
1287 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1288 if (unlikely(Rc(ctx->opcode) != 0))
1289 gen_set_Rc0(ctx, cpu_gpr[ra]);
1290 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1291 gen_set_Rc0(ctx, cpu_gpr[rs]);
1292 #if defined(TARGET_PPC64)
1293 } else {
1294 int prio = 0;
1295
1296 switch (rs) {
1297 case 1:
1298 /* Set process priority to low */
1299 prio = 2;
1300 break;
1301 case 6:
1302 /* Set process priority to medium-low */
1303 prio = 3;
1304 break;
1305 case 2:
1306 /* Set process priority to normal */
1307 prio = 4;
1308 break;
1309 #if !defined(CONFIG_USER_ONLY)
1310 case 31:
1311 if (ctx->mem_idx > 0) {
1312 /* Set process priority to very low */
1313 prio = 1;
1314 }
1315 break;
1316 case 5:
1317 if (ctx->mem_idx > 0) {
1318 /* Set process priority to medium-hight */
1319 prio = 5;
1320 }
1321 break;
1322 case 3:
1323 if (ctx->mem_idx > 0) {
1324 /* Set process priority to high */
1325 prio = 6;
1326 }
1327 break;
1328 case 7:
1329 if (ctx->mem_idx > 1) {
1330 /* Set process priority to very high */
1331 prio = 7;
1332 }
1333 break;
1334 #endif
1335 default:
1336 /* nop */
1337 break;
1338 }
1339 if (prio) {
1340 TCGv t0 = tcg_temp_new();
1341 gen_load_spr(t0, SPR_PPR);
1342 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1343 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1344 gen_store_spr(SPR_PPR, t0);
1345 tcg_temp_free(t0);
1346 }
1347 #endif
1348 }
1349 }
1350 /* orc & orc. */
1351 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1352
1353 /* xor & xor. */
1354 static void gen_xor(DisasContext *ctx)
1355 {
1356 /* Optimisation for "set to zero" case */
1357 if (rS(ctx->opcode) != rB(ctx->opcode))
1358 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1359 else
1360 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1361 if (unlikely(Rc(ctx->opcode) != 0))
1362 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1363 }
1364
1365 /* ori */
1366 static void gen_ori(DisasContext *ctx)
1367 {
1368 target_ulong uimm = UIMM(ctx->opcode);
1369
1370 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1371 /* NOP */
1372 /* XXX: should handle special NOPs for POWER series */
1373 return;
1374 }
1375 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1376 }
1377
1378 /* oris */
1379 static void gen_oris(DisasContext *ctx)
1380 {
1381 target_ulong uimm = UIMM(ctx->opcode);
1382
1383 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1384 /* NOP */
1385 return;
1386 }
1387 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1388 }
1389
1390 /* xori */
1391 static void gen_xori(DisasContext *ctx)
1392 {
1393 target_ulong uimm = UIMM(ctx->opcode);
1394
1395 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1396 /* NOP */
1397 return;
1398 }
1399 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1400 }
1401
1402 /* xoris */
1403 static void gen_xoris(DisasContext *ctx)
1404 {
1405 target_ulong uimm = UIMM(ctx->opcode);
1406
1407 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1408 /* NOP */
1409 return;
1410 }
1411 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1412 }
1413
1414 /* popcntb : PowerPC 2.03 specification */
1415 static void gen_popcntb(DisasContext *ctx)
1416 {
1417 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1418 }
1419
1420 static void gen_popcntw(DisasContext *ctx)
1421 {
1422 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1423 }
1424
1425 #if defined(TARGET_PPC64)
1426 /* popcntd: PowerPC 2.06 specification */
1427 static void gen_popcntd(DisasContext *ctx)
1428 {
1429 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1430 }
1431 #endif
1432
1433 #if defined(TARGET_PPC64)
1434 /* extsw & extsw. */
1435 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1436
1437 /* cntlzd */
1438 static void gen_cntlzd(DisasContext *ctx)
1439 {
1440 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1441 if (unlikely(Rc(ctx->opcode) != 0))
1442 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1443 }
1444 #endif
1445
1446 /*** Integer rotate ***/
1447
1448 /* rlwimi & rlwimi. */
1449 static void gen_rlwimi(DisasContext *ctx)
1450 {
1451 uint32_t mb, me, sh;
1452
1453 mb = MB(ctx->opcode);
1454 me = ME(ctx->opcode);
1455 sh = SH(ctx->opcode);
1456 if (likely(sh == 0 && mb == 0 && me == 31)) {
1457 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1458 } else {
1459 target_ulong mask;
1460 TCGv t1;
1461 TCGv t0 = tcg_temp_new();
1462 #if defined(TARGET_PPC64)
1463 TCGv_i32 t2 = tcg_temp_new_i32();
1464 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1465 tcg_gen_rotli_i32(t2, t2, sh);
1466 tcg_gen_extu_i32_i64(t0, t2);
1467 tcg_temp_free_i32(t2);
1468 #else
1469 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1470 #endif
1471 #if defined(TARGET_PPC64)
1472 mb += 32;
1473 me += 32;
1474 #endif
1475 mask = MASK(mb, me);
1476 t1 = tcg_temp_new();
1477 tcg_gen_andi_tl(t0, t0, mask);
1478 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1479 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1480 tcg_temp_free(t0);
1481 tcg_temp_free(t1);
1482 }
1483 if (unlikely(Rc(ctx->opcode) != 0))
1484 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1485 }
1486
1487 /* rlwinm & rlwinm. */
1488 static void gen_rlwinm(DisasContext *ctx)
1489 {
1490 uint32_t mb, me, sh;
1491
1492 sh = SH(ctx->opcode);
1493 mb = MB(ctx->opcode);
1494 me = ME(ctx->opcode);
1495
1496 if (likely(mb == 0 && me == (31 - sh))) {
1497 if (likely(sh == 0)) {
1498 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1499 } else {
1500 TCGv t0 = tcg_temp_new();
1501 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1502 tcg_gen_shli_tl(t0, t0, sh);
1503 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1504 tcg_temp_free(t0);
1505 }
1506 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1507 TCGv t0 = tcg_temp_new();
1508 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1509 tcg_gen_shri_tl(t0, t0, mb);
1510 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1511 tcg_temp_free(t0);
1512 } else {
1513 TCGv t0 = tcg_temp_new();
1514 #if defined(TARGET_PPC64)
1515 TCGv_i32 t1 = tcg_temp_new_i32();
1516 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1517 tcg_gen_rotli_i32(t1, t1, sh);
1518 tcg_gen_extu_i32_i64(t0, t1);
1519 tcg_temp_free_i32(t1);
1520 #else
1521 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1522 #endif
1523 #if defined(TARGET_PPC64)
1524 mb += 32;
1525 me += 32;
1526 #endif
1527 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1528 tcg_temp_free(t0);
1529 }
1530 if (unlikely(Rc(ctx->opcode) != 0))
1531 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1532 }
1533
1534 /* rlwnm & rlwnm. */
1535 static void gen_rlwnm(DisasContext *ctx)
1536 {
1537 uint32_t mb, me;
1538 TCGv t0;
1539 #if defined(TARGET_PPC64)
1540 TCGv_i32 t1, t2;
1541 #endif
1542
1543 mb = MB(ctx->opcode);
1544 me = ME(ctx->opcode);
1545 t0 = tcg_temp_new();
1546 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1547 #if defined(TARGET_PPC64)
1548 t1 = tcg_temp_new_i32();
1549 t2 = tcg_temp_new_i32();
1550 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1551 tcg_gen_trunc_i64_i32(t2, t0);
1552 tcg_gen_rotl_i32(t1, t1, t2);
1553 tcg_gen_extu_i32_i64(t0, t1);
1554 tcg_temp_free_i32(t1);
1555 tcg_temp_free_i32(t2);
1556 #else
1557 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1558 #endif
1559 if (unlikely(mb != 0 || me != 31)) {
1560 #if defined(TARGET_PPC64)
1561 mb += 32;
1562 me += 32;
1563 #endif
1564 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1565 } else {
1566 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1567 }
1568 tcg_temp_free(t0);
1569 if (unlikely(Rc(ctx->opcode) != 0))
1570 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1571 }
1572
1573 #if defined(TARGET_PPC64)
1574 #define GEN_PPC64_R2(name, opc1, opc2) \
1575 static void glue(gen_, name##0)(DisasContext *ctx) \
1576 { \
1577 gen_##name(ctx, 0); \
1578 } \
1579 \
1580 static void glue(gen_, name##1)(DisasContext *ctx) \
1581 { \
1582 gen_##name(ctx, 1); \
1583 }
1584 #define GEN_PPC64_R4(name, opc1, opc2) \
1585 static void glue(gen_, name##0)(DisasContext *ctx) \
1586 { \
1587 gen_##name(ctx, 0, 0); \
1588 } \
1589 \
1590 static void glue(gen_, name##1)(DisasContext *ctx) \
1591 { \
1592 gen_##name(ctx, 0, 1); \
1593 } \
1594 \
1595 static void glue(gen_, name##2)(DisasContext *ctx) \
1596 { \
1597 gen_##name(ctx, 1, 0); \
1598 } \
1599 \
1600 static void glue(gen_, name##3)(DisasContext *ctx) \
1601 { \
1602 gen_##name(ctx, 1, 1); \
1603 }
1604
1605 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1606 uint32_t sh)
1607 {
1608 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1609 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1610 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1611 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1612 } else {
1613 TCGv t0 = tcg_temp_new();
1614 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1615 if (likely(mb == 0 && me == 63)) {
1616 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1617 } else {
1618 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1619 }
1620 tcg_temp_free(t0);
1621 }
1622 if (unlikely(Rc(ctx->opcode) != 0))
1623 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1624 }
1625 /* rldicl - rldicl. */
1626 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1627 {
1628 uint32_t sh, mb;
1629
1630 sh = SH(ctx->opcode) | (shn << 5);
1631 mb = MB(ctx->opcode) | (mbn << 5);
1632 gen_rldinm(ctx, mb, 63, sh);
1633 }
1634 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1635 /* rldicr - rldicr. */
1636 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1637 {
1638 uint32_t sh, me;
1639
1640 sh = SH(ctx->opcode) | (shn << 5);
1641 me = MB(ctx->opcode) | (men << 5);
1642 gen_rldinm(ctx, 0, me, sh);
1643 }
1644 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1645 /* rldic - rldic. */
1646 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1647 {
1648 uint32_t sh, mb;
1649
1650 sh = SH(ctx->opcode) | (shn << 5);
1651 mb = MB(ctx->opcode) | (mbn << 5);
1652 gen_rldinm(ctx, mb, 63 - sh, sh);
1653 }
1654 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1655
1656 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1657 {
1658 TCGv t0;
1659
1660 mb = MB(ctx->opcode);
1661 me = ME(ctx->opcode);
1662 t0 = tcg_temp_new();
1663 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1664 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1665 if (unlikely(mb != 0 || me != 63)) {
1666 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1667 } else {
1668 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1669 }
1670 tcg_temp_free(t0);
1671 if (unlikely(Rc(ctx->opcode) != 0))
1672 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1673 }
1674
1675 /* rldcl - rldcl. */
1676 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1677 {
1678 uint32_t mb;
1679
1680 mb = MB(ctx->opcode) | (mbn << 5);
1681 gen_rldnm(ctx, mb, 63);
1682 }
1683 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1684 /* rldcr - rldcr. */
1685 static inline void gen_rldcr(DisasContext *ctx, int men)
1686 {
1687 uint32_t me;
1688
1689 me = MB(ctx->opcode) | (men << 5);
1690 gen_rldnm(ctx, 0, me);
1691 }
1692 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1693 /* rldimi - rldimi. */
1694 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1695 {
1696 uint32_t sh, mb, me;
1697
1698 sh = SH(ctx->opcode) | (shn << 5);
1699 mb = MB(ctx->opcode) | (mbn << 5);
1700 me = 63 - sh;
1701 if (unlikely(sh == 0 && mb == 0)) {
1702 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1703 } else {
1704 TCGv t0, t1;
1705 target_ulong mask;
1706
1707 t0 = tcg_temp_new();
1708 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1709 t1 = tcg_temp_new();
1710 mask = MASK(mb, me);
1711 tcg_gen_andi_tl(t0, t0, mask);
1712 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1713 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1714 tcg_temp_free(t0);
1715 tcg_temp_free(t1);
1716 }
1717 if (unlikely(Rc(ctx->opcode) != 0))
1718 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1719 }
1720 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1721 #endif
1722
1723 /*** Integer shift ***/
1724
1725 /* slw & slw. */
1726 static void gen_slw(DisasContext *ctx)
1727 {
1728 TCGv t0, t1;
1729
1730 t0 = tcg_temp_new();
1731 /* AND rS with a mask that is 0 when rB >= 0x20 */
1732 #if defined(TARGET_PPC64)
1733 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1734 tcg_gen_sari_tl(t0, t0, 0x3f);
1735 #else
1736 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1737 tcg_gen_sari_tl(t0, t0, 0x1f);
1738 #endif
1739 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1740 t1 = tcg_temp_new();
1741 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1742 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1743 tcg_temp_free(t1);
1744 tcg_temp_free(t0);
1745 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1746 if (unlikely(Rc(ctx->opcode) != 0))
1747 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1748 }
1749
1750 /* sraw & sraw. */
1751 static void gen_sraw(DisasContext *ctx)
1752 {
1753 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1754 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1755 if (unlikely(Rc(ctx->opcode) != 0))
1756 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1757 }
1758
1759 /* srawi & srawi. */
1760 static void gen_srawi(DisasContext *ctx)
1761 {
1762 int sh = SH(ctx->opcode);
1763 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1764 TCGv src = cpu_gpr[rS(ctx->opcode)];
1765 if (sh == 0) {
1766 tcg_gen_mov_tl(dst, src);
1767 tcg_gen_movi_tl(cpu_ca, 0);
1768 } else {
1769 TCGv t0;
1770 tcg_gen_ext32s_tl(dst, src);
1771 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1772 t0 = tcg_temp_new();
1773 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1774 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1775 tcg_temp_free(t0);
1776 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1777 tcg_gen_sari_tl(dst, dst, sh);
1778 }
1779 if (unlikely(Rc(ctx->opcode) != 0)) {
1780 gen_set_Rc0(ctx, dst);
1781 }
1782 }
1783
1784 /* srw & srw. */
1785 static void gen_srw(DisasContext *ctx)
1786 {
1787 TCGv t0, t1;
1788
1789 t0 = tcg_temp_new();
1790 /* AND rS with a mask that is 0 when rB >= 0x20 */
1791 #if defined(TARGET_PPC64)
1792 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1793 tcg_gen_sari_tl(t0, t0, 0x3f);
1794 #else
1795 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1796 tcg_gen_sari_tl(t0, t0, 0x1f);
1797 #endif
1798 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1799 tcg_gen_ext32u_tl(t0, t0);
1800 t1 = tcg_temp_new();
1801 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1802 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1803 tcg_temp_free(t1);
1804 tcg_temp_free(t0);
1805 if (unlikely(Rc(ctx->opcode) != 0))
1806 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1807 }
1808
1809 #if defined(TARGET_PPC64)
1810 /* sld & sld. */
1811 static void gen_sld(DisasContext *ctx)
1812 {
1813 TCGv t0, t1;
1814
1815 t0 = tcg_temp_new();
1816 /* AND rS with a mask that is 0 when rB >= 0x40 */
1817 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1818 tcg_gen_sari_tl(t0, t0, 0x3f);
1819 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1820 t1 = tcg_temp_new();
1821 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1822 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1823 tcg_temp_free(t1);
1824 tcg_temp_free(t0);
1825 if (unlikely(Rc(ctx->opcode) != 0))
1826 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1827 }
1828
1829 /* srad & srad. */
1830 static void gen_srad(DisasContext *ctx)
1831 {
1832 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1833 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1834 if (unlikely(Rc(ctx->opcode) != 0))
1835 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1836 }
1837 /* sradi & sradi. */
1838 static inline void gen_sradi(DisasContext *ctx, int n)
1839 {
1840 int sh = SH(ctx->opcode) + (n << 5);
1841 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1842 TCGv src = cpu_gpr[rS(ctx->opcode)];
1843 if (sh == 0) {
1844 tcg_gen_mov_tl(dst, src);
1845 tcg_gen_movi_tl(cpu_ca, 0);
1846 } else {
1847 TCGv t0;
1848 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1849 t0 = tcg_temp_new();
1850 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1851 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1852 tcg_temp_free(t0);
1853 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1854 tcg_gen_sari_tl(dst, src, sh);
1855 }
1856 if (unlikely(Rc(ctx->opcode) != 0)) {
1857 gen_set_Rc0(ctx, dst);
1858 }
1859 }
1860
1861 static void gen_sradi0(DisasContext *ctx)
1862 {
1863 gen_sradi(ctx, 0);
1864 }
1865
1866 static void gen_sradi1(DisasContext *ctx)
1867 {
1868 gen_sradi(ctx, 1);
1869 }
1870
1871 /* srd & srd. */
1872 static void gen_srd(DisasContext *ctx)
1873 {
1874 TCGv t0, t1;
1875
1876 t0 = tcg_temp_new();
1877 /* AND rS with a mask that is 0 when rB >= 0x40 */
1878 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1879 tcg_gen_sari_tl(t0, t0, 0x3f);
1880 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1881 t1 = tcg_temp_new();
1882 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1883 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1884 tcg_temp_free(t1);
1885 tcg_temp_free(t0);
1886 if (unlikely(Rc(ctx->opcode) != 0))
1887 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1888 }
1889 #endif
1890
1891 /*** Floating-Point arithmetic ***/
1892 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
1893 static void gen_f##name(DisasContext *ctx) \
1894 { \
1895 if (unlikely(!ctx->fpu_enabled)) { \
1896 gen_exception(ctx, POWERPC_EXCP_FPU); \
1897 return; \
1898 } \
1899 /* NIP cannot be restored if the memory exception comes from an helper */ \
1900 gen_update_nip(ctx, ctx->nip - 4); \
1901 gen_reset_fpstatus(); \
1902 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1903 cpu_fpr[rA(ctx->opcode)], \
1904 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
1905 if (isfloat) { \
1906 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1907 cpu_fpr[rD(ctx->opcode)]); \
1908 } \
1909 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
1910 Rc(ctx->opcode) != 0); \
1911 }
1912
1913 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
1914 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
1915 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
1916
1917 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1918 static void gen_f##name(DisasContext *ctx) \
1919 { \
1920 if (unlikely(!ctx->fpu_enabled)) { \
1921 gen_exception(ctx, POWERPC_EXCP_FPU); \
1922 return; \
1923 } \
1924 /* NIP cannot be restored if the memory exception comes from an helper */ \
1925 gen_update_nip(ctx, ctx->nip - 4); \
1926 gen_reset_fpstatus(); \
1927 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1928 cpu_fpr[rA(ctx->opcode)], \
1929 cpu_fpr[rB(ctx->opcode)]); \
1930 if (isfloat) { \
1931 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1932 cpu_fpr[rD(ctx->opcode)]); \
1933 } \
1934 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1935 set_fprf, Rc(ctx->opcode) != 0); \
1936 }
1937 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
1938 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1939 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1940
1941 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
1942 static void gen_f##name(DisasContext *ctx) \
1943 { \
1944 if (unlikely(!ctx->fpu_enabled)) { \
1945 gen_exception(ctx, POWERPC_EXCP_FPU); \
1946 return; \
1947 } \
1948 /* NIP cannot be restored if the memory exception comes from an helper */ \
1949 gen_update_nip(ctx, ctx->nip - 4); \
1950 gen_reset_fpstatus(); \
1951 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1952 cpu_fpr[rA(ctx->opcode)], \
1953 cpu_fpr[rC(ctx->opcode)]); \
1954 if (isfloat) { \
1955 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1956 cpu_fpr[rD(ctx->opcode)]); \
1957 } \
1958 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1959 set_fprf, Rc(ctx->opcode) != 0); \
1960 }
1961 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
1962 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
1963 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
1964
1965 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
1966 static void gen_f##name(DisasContext *ctx) \
1967 { \
1968 if (unlikely(!ctx->fpu_enabled)) { \
1969 gen_exception(ctx, POWERPC_EXCP_FPU); \
1970 return; \
1971 } \
1972 /* NIP cannot be restored if the memory exception comes from an helper */ \
1973 gen_update_nip(ctx, ctx->nip - 4); \
1974 gen_reset_fpstatus(); \
1975 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1976 cpu_fpr[rB(ctx->opcode)]); \
1977 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1978 set_fprf, Rc(ctx->opcode) != 0); \
1979 }
1980
1981 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
1982 static void gen_f##name(DisasContext *ctx) \
1983 { \
1984 if (unlikely(!ctx->fpu_enabled)) { \
1985 gen_exception(ctx, POWERPC_EXCP_FPU); \
1986 return; \
1987 } \
1988 /* NIP cannot be restored if the memory exception comes from an helper */ \
1989 gen_update_nip(ctx, ctx->nip - 4); \
1990 gen_reset_fpstatus(); \
1991 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
1992 cpu_fpr[rB(ctx->opcode)]); \
1993 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
1994 set_fprf, Rc(ctx->opcode) != 0); \
1995 }
1996
1997 /* fadd - fadds */
1998 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
1999 /* fdiv - fdivs */
2000 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2001 /* fmul - fmuls */
2002 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2003
2004 /* fre */
2005 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2006
2007 /* fres */
2008 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2009
2010 /* frsqrte */
2011 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2012
2013 /* frsqrtes */
2014 static void gen_frsqrtes(DisasContext *ctx)
2015 {
2016 if (unlikely(!ctx->fpu_enabled)) {
2017 gen_exception(ctx, POWERPC_EXCP_FPU);
2018 return;
2019 }
2020 /* NIP cannot be restored if the memory exception comes from an helper */
2021 gen_update_nip(ctx, ctx->nip - 4);
2022 gen_reset_fpstatus();
2023 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2024 cpu_fpr[rB(ctx->opcode)]);
2025 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2026 cpu_fpr[rD(ctx->opcode)]);
2027 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2028 }
2029
2030 /* fsel */
2031 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2032 /* fsub - fsubs */
2033 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2034 /* Optional: */
2035
2036 /* fsqrt */
2037 static void gen_fsqrt(DisasContext *ctx)
2038 {
2039 if (unlikely(!ctx->fpu_enabled)) {
2040 gen_exception(ctx, POWERPC_EXCP_FPU);
2041 return;
2042 }
2043 /* NIP cannot be restored if the memory exception comes from an helper */
2044 gen_update_nip(ctx, ctx->nip - 4);
2045 gen_reset_fpstatus();
2046 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2047 cpu_fpr[rB(ctx->opcode)]);
2048 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2049 }
2050
2051 static void gen_fsqrts(DisasContext *ctx)
2052 {
2053 if (unlikely(!ctx->fpu_enabled)) {
2054 gen_exception(ctx, POWERPC_EXCP_FPU);
2055 return;
2056 }
2057 /* NIP cannot be restored if the memory exception comes from an helper */
2058 gen_update_nip(ctx, ctx->nip - 4);
2059 gen_reset_fpstatus();
2060 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2061 cpu_fpr[rB(ctx->opcode)]);
2062 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2063 cpu_fpr[rD(ctx->opcode)]);
2064 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2065 }
2066
2067 /*** Floating-Point multiply-and-add ***/
2068 /* fmadd - fmadds */
2069 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2070 /* fmsub - fmsubs */
2071 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2072 /* fnmadd - fnmadds */
2073 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2074 /* fnmsub - fnmsubs */
2075 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2076
2077 /*** Floating-Point round & convert ***/
2078 /* fctiw */
2079 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2080 /* fctiwz */
2081 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2082 /* frsp */
2083 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2084 #if defined(TARGET_PPC64)
2085 /* fcfid */
2086 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2087 /* fctid */
2088 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2089 /* fctidz */
2090 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2091 #endif
2092
2093 /* frin */
2094 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2095 /* friz */
2096 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2097 /* frip */
2098 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2099 /* frim */
2100 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2101
2102 /*** Floating-Point compare ***/
2103
2104 /* fcmpo */
2105 static void gen_fcmpo(DisasContext *ctx)
2106 {
2107 TCGv_i32 crf;
2108 if (unlikely(!ctx->fpu_enabled)) {
2109 gen_exception(ctx, POWERPC_EXCP_FPU);
2110 return;
2111 }
2112 /* NIP cannot be restored if the memory exception comes from an helper */
2113 gen_update_nip(ctx, ctx->nip - 4);
2114 gen_reset_fpstatus();
2115 crf = tcg_const_i32(crfD(ctx->opcode));
2116 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2117 cpu_fpr[rB(ctx->opcode)], crf);
2118 tcg_temp_free_i32(crf);
2119 gen_helper_float_check_status(cpu_env);
2120 }
2121
2122 /* fcmpu */
2123 static void gen_fcmpu(DisasContext *ctx)
2124 {
2125 TCGv_i32 crf;
2126 if (unlikely(!ctx->fpu_enabled)) {
2127 gen_exception(ctx, POWERPC_EXCP_FPU);
2128 return;
2129 }
2130 /* NIP cannot be restored if the memory exception comes from an helper */
2131 gen_update_nip(ctx, ctx->nip - 4);
2132 gen_reset_fpstatus();
2133 crf = tcg_const_i32(crfD(ctx->opcode));
2134 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2135 cpu_fpr[rB(ctx->opcode)], crf);
2136 tcg_temp_free_i32(crf);
2137 gen_helper_float_check_status(cpu_env);
2138 }
2139
2140 /*** Floating-point move ***/
2141 /* fabs */
2142 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2143 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT);
2144
2145 /* fmr - fmr. */
2146 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2147 static void gen_fmr(DisasContext *ctx)
2148 {
2149 if (unlikely(!ctx->fpu_enabled)) {
2150 gen_exception(ctx, POWERPC_EXCP_FPU);
2151 return;
2152 }
2153 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2154 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2155 }
2156
2157 /* fnabs */
2158 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2159 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT);
2160 /* fneg */
2161 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2162 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT);
2163
2164 /*** Floating-Point status & ctrl register ***/
2165
2166 /* mcrfs */
2167 static void gen_mcrfs(DisasContext *ctx)
2168 {
2169 TCGv tmp = tcg_temp_new();
2170 int bfa;
2171
2172 if (unlikely(!ctx->fpu_enabled)) {
2173 gen_exception(ctx, POWERPC_EXCP_FPU);
2174 return;
2175 }
2176 bfa = 4 * (7 - crfS(ctx->opcode));
2177 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2178 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2179 tcg_temp_free(tmp);
2180 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2181 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2182 }
2183
2184 /* mffs */
2185 static void gen_mffs(DisasContext *ctx)
2186 {
2187 if (unlikely(!ctx->fpu_enabled)) {
2188 gen_exception(ctx, POWERPC_EXCP_FPU);
2189 return;
2190 }
2191 gen_reset_fpstatus();
2192 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2193 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2194 }
2195
2196 /* mtfsb0 */
2197 static void gen_mtfsb0(DisasContext *ctx)
2198 {
2199 uint8_t crb;
2200
2201 if (unlikely(!ctx->fpu_enabled)) {
2202 gen_exception(ctx, POWERPC_EXCP_FPU);
2203 return;
2204 }
2205 crb = 31 - crbD(ctx->opcode);
2206 gen_reset_fpstatus();
2207 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2208 TCGv_i32 t0;
2209 /* NIP cannot be restored if the memory exception comes from an helper */
2210 gen_update_nip(ctx, ctx->nip - 4);
2211 t0 = tcg_const_i32(crb);
2212 gen_helper_fpscr_clrbit(cpu_env, t0);
2213 tcg_temp_free_i32(t0);
2214 }
2215 if (unlikely(Rc(ctx->opcode) != 0)) {
2216 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2217 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2218 }
2219 }
2220
2221 /* mtfsb1 */
2222 static void gen_mtfsb1(DisasContext *ctx)
2223 {
2224 uint8_t crb;
2225
2226 if (unlikely(!ctx->fpu_enabled)) {
2227 gen_exception(ctx, POWERPC_EXCP_FPU);
2228 return;
2229 }
2230 crb = 31 - crbD(ctx->opcode);
2231 gen_reset_fpstatus();
2232 /* XXX: we pretend we can only do IEEE floating-point computations */
2233 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2234 TCGv_i32 t0;
2235 /* NIP cannot be restored if the memory exception comes from an helper */
2236 gen_update_nip(ctx, ctx->nip - 4);
2237 t0 = tcg_const_i32(crb);
2238 gen_helper_fpscr_setbit(cpu_env, t0);
2239 tcg_temp_free_i32(t0);
2240 }
2241 if (unlikely(Rc(ctx->opcode) != 0)) {
2242 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2243 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2244 }
2245 /* We can raise a differed exception */
2246 gen_helper_float_check_status(cpu_env);
2247 }
2248
2249 /* mtfsf */
2250 static void gen_mtfsf(DisasContext *ctx)
2251 {
2252 TCGv_i32 t0;
2253 int L = ctx->opcode & 0x02000000;
2254
2255 if (unlikely(!ctx->fpu_enabled)) {
2256 gen_exception(ctx, POWERPC_EXCP_FPU);
2257 return;
2258 }
2259 /* NIP cannot be restored if the memory exception comes from an helper */
2260 gen_update_nip(ctx, ctx->nip - 4);
2261 gen_reset_fpstatus();
2262 if (L)
2263 t0 = tcg_const_i32(0xff);
2264 else
2265 t0 = tcg_const_i32(FM(ctx->opcode));
2266 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2267 tcg_temp_free_i32(t0);
2268 if (unlikely(Rc(ctx->opcode) != 0)) {
2269 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2270 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2271 }
2272 /* We can raise a differed exception */
2273 gen_helper_float_check_status(cpu_env);
2274 }
2275
2276 /* mtfsfi */
2277 static void gen_mtfsfi(DisasContext *ctx)
2278 {
2279 int bf, sh;
2280 TCGv_i64 t0;
2281 TCGv_i32 t1;
2282
2283 if (unlikely(!ctx->fpu_enabled)) {
2284 gen_exception(ctx, POWERPC_EXCP_FPU);
2285 return;
2286 }
2287 bf = crbD(ctx->opcode) >> 2;
2288 sh = 7 - bf;
2289 /* NIP cannot be restored if the memory exception comes from an helper */
2290 gen_update_nip(ctx, ctx->nip - 4);
2291 gen_reset_fpstatus();
2292 t0 = tcg_const_i64(FPIMM(ctx->opcode) << (4 * sh));
2293 t1 = tcg_const_i32(1 << sh);
2294 gen_helper_store_fpscr(cpu_env, t0, t1);
2295 tcg_temp_free_i64(t0);
2296 tcg_temp_free_i32(t1);
2297 if (unlikely(Rc(ctx->opcode) != 0)) {
2298 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2299 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2300 }
2301 /* We can raise a differed exception */
2302 gen_helper_float_check_status(cpu_env);
2303 }
2304
2305 /*** Addressing modes ***/
2306 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2307 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2308 target_long maskl)
2309 {
2310 target_long simm = SIMM(ctx->opcode);
2311
2312 simm &= ~maskl;
2313 if (rA(ctx->opcode) == 0) {
2314 #if defined(TARGET_PPC64)
2315 if (!ctx->sf_mode) {
2316 tcg_gen_movi_tl(EA, (uint32_t)simm);
2317 } else
2318 #endif
2319 tcg_gen_movi_tl(EA, simm);
2320 } else if (likely(simm != 0)) {
2321 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2322 #if defined(TARGET_PPC64)
2323 if (!ctx->sf_mode) {
2324 tcg_gen_ext32u_tl(EA, EA);
2325 }
2326 #endif
2327 } else {
2328 #if defined(TARGET_PPC64)
2329 if (!ctx->sf_mode) {
2330 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2331 } else
2332 #endif
2333 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2334 }
2335 }
2336
2337 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2338 {
2339 if (rA(ctx->opcode) == 0) {
2340 #if defined(TARGET_PPC64)
2341 if (!ctx->sf_mode) {
2342 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2343 } else
2344 #endif
2345 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2346 } else {
2347 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2348 #if defined(TARGET_PPC64)
2349 if (!ctx->sf_mode) {
2350 tcg_gen_ext32u_tl(EA, EA);
2351 }
2352 #endif
2353 }
2354 }
2355
2356 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2357 {
2358 if (rA(ctx->opcode) == 0) {
2359 tcg_gen_movi_tl(EA, 0);
2360 } else {
2361 #if defined(TARGET_PPC64)
2362 if (!ctx->sf_mode) {
2363 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2364 } else
2365 #endif
2366 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2367 }
2368 }
2369
2370 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2371 target_long val)
2372 {
2373 tcg_gen_addi_tl(ret, arg1, val);
2374 #if defined(TARGET_PPC64)
2375 if (!ctx->sf_mode) {
2376 tcg_gen_ext32u_tl(ret, ret);
2377 }
2378 #endif
2379 }
2380
2381 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2382 {
2383 int l1 = gen_new_label();
2384 TCGv t0 = tcg_temp_new();
2385 TCGv_i32 t1, t2;
2386 /* NIP cannot be restored if the memory exception comes from an helper */
2387 gen_update_nip(ctx, ctx->nip - 4);
2388 tcg_gen_andi_tl(t0, EA, mask);
2389 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2390 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2391 t2 = tcg_const_i32(0);
2392 gen_helper_raise_exception_err(cpu_env, t1, t2);
2393 tcg_temp_free_i32(t1);
2394 tcg_temp_free_i32(t2);
2395 gen_set_label(l1);
2396 tcg_temp_free(t0);
2397 }
2398
2399 /*** Integer load ***/
2400 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2401 {
2402 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2403 }
2404
2405 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2406 {
2407 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2408 }
2409
2410 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2411 {
2412 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2413 if (unlikely(ctx->le_mode)) {
2414 tcg_gen_bswap16_tl(arg1, arg1);
2415 }
2416 }
2417
2418 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2419 {
2420 if (unlikely(ctx->le_mode)) {
2421 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2422 tcg_gen_bswap16_tl(arg1, arg1);
2423 tcg_gen_ext16s_tl(arg1, arg1);
2424 } else {
2425 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2426 }
2427 }
2428
2429 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2430 {
2431 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2432 if (unlikely(ctx->le_mode)) {
2433 tcg_gen_bswap32_tl(arg1, arg1);
2434 }
2435 }
2436
2437 #if defined(TARGET_PPC64)
2438 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2439 {
2440 if (unlikely(ctx->le_mode)) {
2441 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2442 tcg_gen_bswap32_tl(arg1, arg1);
2443 tcg_gen_ext32s_tl(arg1, arg1);
2444 } else
2445 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2446 }
2447 #endif
2448
2449 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2450 {
2451 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2452 if (unlikely(ctx->le_mode)) {
2453 tcg_gen_bswap64_i64(arg1, arg1);
2454 }
2455 }
2456
2457 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2458 {
2459 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2460 }
2461
2462 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2463 {
2464 if (unlikely(ctx->le_mode)) {
2465 TCGv t0 = tcg_temp_new();
2466 tcg_gen_ext16u_tl(t0, arg1);
2467 tcg_gen_bswap16_tl(t0, t0);
2468 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2469 tcg_temp_free(t0);
2470 } else {
2471 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2472 }
2473 }
2474
2475 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2476 {
2477 if (unlikely(ctx->le_mode)) {
2478 TCGv t0 = tcg_temp_new();
2479 tcg_gen_ext32u_tl(t0, arg1);
2480 tcg_gen_bswap32_tl(t0, t0);
2481 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2482 tcg_temp_free(t0);
2483 } else {
2484 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2485 }
2486 }
2487
2488 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2489 {
2490 if (unlikely(ctx->le_mode)) {
2491 TCGv_i64 t0 = tcg_temp_new_i64();
2492 tcg_gen_bswap64_i64(t0, arg1);
2493 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2494 tcg_temp_free_i64(t0);
2495 } else
2496 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2497 }
2498
2499 #define GEN_LD(name, ldop, opc, type) \
2500 static void glue(gen_, name)(DisasContext *ctx) \
2501 { \
2502 TCGv EA; \
2503 gen_set_access_type(ctx, ACCESS_INT); \
2504 EA = tcg_temp_new(); \
2505 gen_addr_imm_index(ctx, EA, 0); \
2506 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2507 tcg_temp_free(EA); \
2508 }
2509
2510 #define GEN_LDU(name, ldop, opc, type) \
2511 static void glue(gen_, name##u)(DisasContext *ctx) \
2512 { \
2513 TCGv EA; \
2514 if (unlikely(rA(ctx->opcode) == 0 || \
2515 rA(ctx->opcode) == rD(ctx->opcode))) { \
2516 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2517 return; \
2518 } \
2519 gen_set_access_type(ctx, ACCESS_INT); \
2520 EA = tcg_temp_new(); \
2521 if (type == PPC_64B) \
2522 gen_addr_imm_index(ctx, EA, 0x03); \
2523 else \
2524 gen_addr_imm_index(ctx, EA, 0); \
2525 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2526 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2527 tcg_temp_free(EA); \
2528 }
2529
2530 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2531 static void glue(gen_, name##ux)(DisasContext *ctx) \
2532 { \
2533 TCGv EA; \
2534 if (unlikely(rA(ctx->opcode) == 0 || \
2535 rA(ctx->opcode) == rD(ctx->opcode))) { \
2536 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2537 return; \
2538 } \
2539 gen_set_access_type(ctx, ACCESS_INT); \
2540 EA = tcg_temp_new(); \
2541 gen_addr_reg_index(ctx, EA); \
2542 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2543 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2544 tcg_temp_free(EA); \
2545 }
2546
2547 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2548 static void glue(gen_, name##x)(DisasContext *ctx) \
2549 { \
2550 TCGv EA; \
2551 gen_set_access_type(ctx, ACCESS_INT); \
2552 EA = tcg_temp_new(); \
2553 gen_addr_reg_index(ctx, EA); \
2554 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2555 tcg_temp_free(EA); \
2556 }
2557 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2558 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2559
2560 #define GEN_LDS(name, ldop, op, type) \
2561 GEN_LD(name, ldop, op | 0x20, type); \
2562 GEN_LDU(name, ldop, op | 0x21, type); \
2563 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2564 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2565
2566 /* lbz lbzu lbzux lbzx */
2567 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2568 /* lha lhau lhaux lhax */
2569 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2570 /* lhz lhzu lhzux lhzx */
2571 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2572 /* lwz lwzu lwzux lwzx */
2573 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2574 #if defined(TARGET_PPC64)
2575 /* lwaux */
2576 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2577 /* lwax */
2578 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2579 /* ldux */
2580 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2581 /* ldx */
2582 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2583
2584 static void gen_ld(DisasContext *ctx)
2585 {
2586 TCGv EA;
2587 if (Rc(ctx->opcode)) {
2588 if (unlikely(rA(ctx->opcode) == 0 ||
2589 rA(ctx->opcode) == rD(ctx->opcode))) {
2590 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2591 return;
2592 }
2593 }
2594 gen_set_access_type(ctx, ACCESS_INT);
2595 EA = tcg_temp_new();
2596 gen_addr_imm_index(ctx, EA, 0x03);
2597 if (ctx->opcode & 0x02) {
2598 /* lwa (lwau is undefined) */
2599 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2600 } else {
2601 /* ld - ldu */
2602 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2603 }
2604 if (Rc(ctx->opcode))
2605 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2606 tcg_temp_free(EA);
2607 }
2608
2609 /* lq */
2610 static void gen_lq(DisasContext *ctx)
2611 {
2612 #if defined(CONFIG_USER_ONLY)
2613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2614 #else
2615 int ra, rd;
2616 TCGv EA;
2617
2618 /* Restore CPU state */
2619 if (unlikely(ctx->mem_idx == 0)) {
2620 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2621 return;
2622 }
2623 ra = rA(ctx->opcode);
2624 rd = rD(ctx->opcode);
2625 if (unlikely((rd & 1) || rd == ra)) {
2626 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2627 return;
2628 }
2629 if (unlikely(ctx->le_mode)) {
2630 /* Little-endian mode is not handled */
2631 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2632 return;
2633 }
2634 gen_set_access_type(ctx, ACCESS_INT);
2635 EA = tcg_temp_new();
2636 gen_addr_imm_index(ctx, EA, 0x0F);
2637 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2638 gen_addr_add(ctx, EA, EA, 8);
2639 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2640 tcg_temp_free(EA);
2641 #endif
2642 }
2643 #endif
2644
2645 /*** Integer store ***/
2646 #define GEN_ST(name, stop, opc, type) \
2647 static void glue(gen_, name)(DisasContext *ctx) \
2648 { \
2649 TCGv EA; \
2650 gen_set_access_type(ctx, ACCESS_INT); \
2651 EA = tcg_temp_new(); \
2652 gen_addr_imm_index(ctx, EA, 0); \
2653 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2654 tcg_temp_free(EA); \
2655 }
2656
2657 #define GEN_STU(name, stop, opc, type) \
2658 static void glue(gen_, stop##u)(DisasContext *ctx) \
2659 { \
2660 TCGv EA; \
2661 if (unlikely(rA(ctx->opcode) == 0)) { \
2662 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2663 return; \
2664 } \
2665 gen_set_access_type(ctx, ACCESS_INT); \
2666 EA = tcg_temp_new(); \
2667 if (type == PPC_64B) \
2668 gen_addr_imm_index(ctx, EA, 0x03); \
2669 else \
2670 gen_addr_imm_index(ctx, EA, 0); \
2671 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2672 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2673 tcg_temp_free(EA); \
2674 }
2675
2676 #define GEN_STUX(name, stop, opc2, opc3, type) \
2677 static void glue(gen_, name##ux)(DisasContext *ctx) \
2678 { \
2679 TCGv EA; \
2680 if (unlikely(rA(ctx->opcode) == 0)) { \
2681 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2682 return; \
2683 } \
2684 gen_set_access_type(ctx, ACCESS_INT); \
2685 EA = tcg_temp_new(); \
2686 gen_addr_reg_index(ctx, EA); \
2687 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2688 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2689 tcg_temp_free(EA); \
2690 }
2691
2692 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2693 static void glue(gen_, name##x)(DisasContext *ctx) \
2694 { \
2695 TCGv EA; \
2696 gen_set_access_type(ctx, ACCESS_INT); \
2697 EA = tcg_temp_new(); \
2698 gen_addr_reg_index(ctx, EA); \
2699 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2700 tcg_temp_free(EA); \
2701 }
2702 #define GEN_STX(name, stop, opc2, opc3, type) \
2703 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2704
2705 #define GEN_STS(name, stop, op, type) \
2706 GEN_ST(name, stop, op | 0x20, type); \
2707 GEN_STU(name, stop, op | 0x21, type); \
2708 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2709 GEN_STX(name, stop, 0x17, op | 0x00, type)
2710
2711 /* stb stbu stbux stbx */
2712 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2713 /* sth sthu sthux sthx */
2714 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2715 /* stw stwu stwux stwx */
2716 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2717 #if defined(TARGET_PPC64)
2718 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2719 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2720
2721 static void gen_std(DisasContext *ctx)
2722 {
2723 int rs;
2724 TCGv EA;
2725
2726 rs = rS(ctx->opcode);
2727 if ((ctx->opcode & 0x3) == 0x2) {
2728 #if defined(CONFIG_USER_ONLY)
2729 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2730 #else
2731 /* stq */
2732 if (unlikely(ctx->mem_idx == 0)) {
2733 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2734 return;
2735 }
2736 if (unlikely(rs & 1)) {
2737 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2738 return;
2739 }
2740 if (unlikely(ctx->le_mode)) {
2741 /* Little-endian mode is not handled */
2742 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2743 return;
2744 }
2745 gen_set_access_type(ctx, ACCESS_INT);
2746 EA = tcg_temp_new();
2747 gen_addr_imm_index(ctx, EA, 0x03);
2748 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2749 gen_addr_add(ctx, EA, EA, 8);
2750 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
2751 tcg_temp_free(EA);
2752 #endif
2753 } else {
2754 /* std / stdu */
2755 if (Rc(ctx->opcode)) {
2756 if (unlikely(rA(ctx->opcode) == 0)) {
2757 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2758 return;
2759 }
2760 }
2761 gen_set_access_type(ctx, ACCESS_INT);
2762 EA = tcg_temp_new();
2763 gen_addr_imm_index(ctx, EA, 0x03);
2764 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2765 if (Rc(ctx->opcode))
2766 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2767 tcg_temp_free(EA);
2768 }
2769 }
2770 #endif
2771 /*** Integer load and store with byte reverse ***/
2772 /* lhbrx */
2773 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2774 {
2775 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2776 if (likely(!ctx->le_mode)) {
2777 tcg_gen_bswap16_tl(arg1, arg1);
2778 }
2779 }
2780 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
2781
2782 /* lwbrx */
2783 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2784 {
2785 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2786 if (likely(!ctx->le_mode)) {
2787 tcg_gen_bswap32_tl(arg1, arg1);
2788 }
2789 }
2790 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
2791
2792 #if defined(TARGET_PPC64)
2793 /* ldbrx */
2794 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
2795 {
2796 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2797 if (likely(!ctx->le_mode)) {
2798 tcg_gen_bswap64_tl(arg1, arg1);
2799 }
2800 }
2801 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
2802 #endif /* TARGET_PPC64 */
2803
2804 /* sthbrx */
2805 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2806 {
2807 if (likely(!ctx->le_mode)) {
2808 TCGv t0 = tcg_temp_new();
2809 tcg_gen_ext16u_tl(t0, arg1);
2810 tcg_gen_bswap16_tl(t0, t0);
2811 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2812 tcg_temp_free(t0);
2813 } else {
2814 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2815 }
2816 }
2817 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
2818
2819 /* stwbrx */
2820 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2821 {
2822 if (likely(!ctx->le_mode)) {
2823 TCGv t0 = tcg_temp_new();
2824 tcg_gen_ext32u_tl(t0, arg1);
2825 tcg_gen_bswap32_tl(t0, t0);
2826 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2827 tcg_temp_free(t0);
2828 } else {
2829 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2830 }
2831 }
2832 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
2833
2834 #if defined(TARGET_PPC64)
2835 /* stdbrx */
2836 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
2837 {
2838 if (likely(!ctx->le_mode)) {
2839 TCGv t0 = tcg_temp_new();
2840 tcg_gen_bswap64_tl(t0, arg1);
2841 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2842 tcg_temp_free(t0);
2843 } else {
2844 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2845 }
2846 }
2847 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
2848 #endif /* TARGET_PPC64 */
2849
2850 /*** Integer load and store multiple ***/
2851
2852 /* lmw */
2853 static void gen_lmw(DisasContext *ctx)
2854 {
2855 TCGv t0;
2856 TCGv_i32 t1;
2857 gen_set_access_type(ctx, ACCESS_INT);
2858 /* NIP cannot be restored if the memory exception comes from an helper */
2859 gen_update_nip(ctx, ctx->nip - 4);
2860 t0 = tcg_temp_new();
2861 t1 = tcg_const_i32(rD(ctx->opcode));
2862 gen_addr_imm_index(ctx, t0, 0);
2863 gen_helper_lmw(cpu_env, t0, t1);
2864 tcg_temp_free(t0);
2865 tcg_temp_free_i32(t1);
2866 }
2867
2868 /* stmw */
2869 static void gen_stmw(DisasContext *ctx)
2870 {
2871 TCGv t0;
2872 TCGv_i32 t1;
2873 gen_set_access_type(ctx, ACCESS_INT);
2874 /* NIP cannot be restored if the memory exception comes from an helper */
2875 gen_update_nip(ctx, ctx->nip - 4);
2876 t0 = tcg_temp_new();
2877 t1 = tcg_const_i32(rS(ctx->opcode));
2878 gen_addr_imm_index(ctx, t0, 0);
2879 gen_helper_stmw(cpu_env, t0, t1);
2880 tcg_temp_free(t0);
2881 tcg_temp_free_i32(t1);
2882 }
2883
2884 /*** Integer load and store strings ***/
2885
2886 /* lswi */
2887 /* PowerPC32 specification says we must generate an exception if
2888 * rA is in the range of registers to be loaded.
2889 * In an other hand, IBM says this is valid, but rA won't be loaded.
2890 * For now, I'll follow the spec...
2891 */
2892 static void gen_lswi(DisasContext *ctx)
2893 {
2894 TCGv t0;
2895 TCGv_i32 t1, t2;
2896 int nb = NB(ctx->opcode);
2897 int start = rD(ctx->opcode);
2898 int ra = rA(ctx->opcode);
2899 int nr;
2900
2901 if (nb == 0)
2902 nb = 32;
2903 nr = nb / 4;
2904 if (unlikely(((start + nr) > 32 &&
2905 start <= ra && (start + nr - 32) > ra) ||
2906 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
2907 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
2908 return;
2909 }
2910 gen_set_access_type(ctx, ACCESS_INT);
2911 /* NIP cannot be restored if the memory exception comes from an helper */
2912 gen_update_nip(ctx, ctx->nip - 4);
2913 t0 = tcg_temp_new();
2914 gen_addr_register(ctx, t0);
2915 t1 = tcg_const_i32(nb);
2916 t2 = tcg_const_i32(start);
2917 gen_helper_lsw(cpu_env, t0, t1, t2);
2918 tcg_temp_free(t0);
2919 tcg_temp_free_i32(t1);
2920 tcg_temp_free_i32(t2);
2921 }
2922
2923 /* lswx */
2924 static void gen_lswx(DisasContext *ctx)
2925 {
2926 TCGv t0;
2927 TCGv_i32 t1, t2, t3;
2928 gen_set_access_type(ctx, ACCESS_INT);
2929 /* NIP cannot be restored if the memory exception comes from an helper */
2930 gen_update_nip(ctx, ctx->nip - 4);
2931 t0 = tcg_temp_new();
2932 gen_addr_reg_index(ctx, t0);
2933 t1 = tcg_const_i32(rD(ctx->opcode));
2934 t2 = tcg_const_i32(rA(ctx->opcode));
2935 t3 = tcg_const_i32(rB(ctx->opcode));
2936 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
2937 tcg_temp_free(t0);
2938 tcg_temp_free_i32(t1);
2939 tcg_temp_free_i32(t2);
2940 tcg_temp_free_i32(t3);
2941 }
2942
2943 /* stswi */
2944 static void gen_stswi(DisasContext *ctx)
2945 {
2946 TCGv t0;
2947 TCGv_i32 t1, t2;
2948 int nb = NB(ctx->opcode);
2949 gen_set_access_type(ctx, ACCESS_INT);
2950 /* NIP cannot be restored if the memory exception comes from an helper */
2951 gen_update_nip(ctx, ctx->nip - 4);
2952 t0 = tcg_temp_new();
2953 gen_addr_register(ctx, t0);
2954 if (nb == 0)
2955 nb = 32;
2956 t1 = tcg_const_i32(nb);
2957 t2 = tcg_const_i32(rS(ctx->opcode));
2958 gen_helper_stsw(cpu_env, t0, t1, t2);
2959 tcg_temp_free(t0);
2960 tcg_temp_free_i32(t1);
2961 tcg_temp_free_i32(t2);
2962 }
2963
2964 /* stswx */
2965 static void gen_stswx(DisasContext *ctx)
2966 {
2967 TCGv t0;
2968 TCGv_i32 t1, t2;
2969 gen_set_access_type(ctx, ACCESS_INT);
2970 /* NIP cannot be restored if the memory exception comes from an helper */
2971 gen_update_nip(ctx, ctx->nip - 4);
2972 t0 = tcg_temp_new();
2973 gen_addr_reg_index(ctx, t0);
2974 t1 = tcg_temp_new_i32();
2975 tcg_gen_trunc_tl_i32(t1, cpu_xer);
2976 tcg_gen_andi_i32(t1, t1, 0x7F);
2977 t2 = tcg_const_i32(rS(ctx->opcode));
2978 gen_helper_stsw(cpu_env, t0, t1, t2);
2979 tcg_temp_free(t0);
2980 tcg_temp_free_i32(t1);
2981 tcg_temp_free_i32(t2);
2982 }
2983
2984 /*** Memory synchronisation ***/
2985 /* eieio */
2986 static void gen_eieio(DisasContext *ctx)
2987 {
2988 }
2989
2990 /* isync */
2991 static void gen_isync(DisasContext *ctx)
2992 {
2993 gen_stop_exception(ctx);
2994 }
2995
2996 /* lwarx */
2997 static void gen_lwarx(DisasContext *ctx)
2998 {
2999 TCGv t0;
3000 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3001 gen_set_access_type(ctx, ACCESS_RES);
3002 t0 = tcg_temp_local_new();
3003 gen_addr_reg_index(ctx, t0);
3004 gen_check_align(ctx, t0, 0x03);
3005 gen_qemu_ld32u(ctx, gpr, t0);
3006 tcg_gen_mov_tl(cpu_reserve, t0);
3007 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3008 tcg_temp_free(t0);
3009 }
3010
3011 #if defined(CONFIG_USER_ONLY)
3012 static void gen_conditional_store (DisasContext *ctx, TCGv EA,
3013 int reg, int size)
3014 {
3015 TCGv t0 = tcg_temp_new();
3016 uint32_t save_exception = ctx->exception;
3017
3018 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3019 tcg_gen_movi_tl(t0, (size << 5) | reg);
3020 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3021 tcg_temp_free(t0);
3022 gen_update_nip(ctx, ctx->nip-4);
3023 ctx->exception = POWERPC_EXCP_BRANCH;
3024 gen_exception(ctx, POWERPC_EXCP_STCX);
3025 ctx->exception = save_exception;
3026 }
3027 #endif
3028
3029 /* stwcx. */
3030 static void gen_stwcx_(DisasContext *ctx)
3031 {
3032 TCGv t0;
3033 gen_set_access_type(ctx, ACCESS_RES);
3034 t0 = tcg_temp_local_new();
3035 gen_addr_reg_index(ctx, t0);
3036 gen_check_align(ctx, t0, 0x03);
3037 #if defined(CONFIG_USER_ONLY)
3038 gen_conditional_store(ctx, t0, rS(ctx->opcode), 4);
3039 #else
3040 {
3041 int l1;
3042
3043 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3044 l1 = gen_new_label();
3045 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3046 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3047 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3048 gen_set_label(l1);
3049 tcg_gen_movi_tl(cpu_reserve, -1);
3050 }
3051 #endif
3052 tcg_temp_free(t0);
3053 }
3054
3055 #if defined(TARGET_PPC64)
3056 /* ldarx */
3057 static void gen_ldarx(DisasContext *ctx)
3058 {
3059 TCGv t0;
3060 TCGv gpr = cpu_gpr[rD(ctx->opcode)];
3061 gen_set_access_type(ctx, ACCESS_RES);
3062 t0 = tcg_temp_local_new();
3063 gen_addr_reg_index(ctx, t0);
3064 gen_check_align(ctx, t0, 0x07);
3065 gen_qemu_ld64(ctx, gpr, t0);
3066 tcg_gen_mov_tl(cpu_reserve, t0);
3067 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val));
3068 tcg_temp_free(t0);
3069 }
3070
3071 /* stdcx. */
3072 static void gen_stdcx_(DisasContext *ctx)
3073 {
3074 TCGv t0;
3075 gen_set_access_type(ctx, ACCESS_RES);
3076 t0 = tcg_temp_local_new();
3077 gen_addr_reg_index(ctx, t0);
3078 gen_check_align(ctx, t0, 0x07);
3079 #if defined(CONFIG_USER_ONLY)
3080 gen_conditional_store(ctx, t0, rS(ctx->opcode), 8);
3081 #else
3082 {
3083 int l1;
3084 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3085 l1 = gen_new_label();
3086 tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
3087 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3088 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], t0);
3089 gen_set_label(l1);
3090 tcg_gen_movi_tl(cpu_reserve, -1);
3091 }
3092 #endif
3093 tcg_temp_free(t0);
3094 }
3095 #endif /* defined(TARGET_PPC64) */
3096
3097 /* sync */
3098 static void gen_sync(DisasContext *ctx)
3099 {
3100 }
3101
3102 /* wait */
3103 static void gen_wait(DisasContext *ctx)
3104 {
3105 TCGv_i32 t0 = tcg_temp_new_i32();
3106 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, halted));
3107 tcg_temp_free_i32(t0);
3108 /* Stop translation, as the CPU is supposed to sleep from now */
3109 gen_exception_err(ctx, EXCP_HLT, 1);
3110 }
3111
3112 /*** Floating-point load ***/
3113 #define GEN_LDF(name, ldop, opc, type) \
3114 static void glue(gen_, name)(DisasContext *ctx) \
3115 { \
3116 TCGv EA; \
3117 if (unlikely(!ctx->fpu_enabled)) { \
3118 gen_exception(ctx, POWERPC_EXCP_FPU); \
3119 return; \
3120 } \
3121 gen_set_access_type(ctx, ACCESS_FLOAT); \
3122 EA = tcg_temp_new(); \
3123 gen_addr_imm_index(ctx, EA, 0); \
3124 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3125 tcg_temp_free(EA); \
3126 }
3127
3128 #define GEN_LDUF(name, ldop, opc, type) \
3129 static void glue(gen_, name##u)(DisasContext *ctx) \
3130 { \
3131 TCGv EA; \
3132 if (unlikely(!ctx->fpu_enabled)) { \
3133 gen_exception(ctx, POWERPC_EXCP_FPU); \
3134 return; \
3135 } \
3136 if (unlikely(rA(ctx->opcode) == 0)) { \
3137 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3138 return; \
3139 } \
3140 gen_set_access_type(ctx, ACCESS_FLOAT); \
3141 EA = tcg_temp_new(); \
3142 gen_addr_imm_index(ctx, EA, 0); \
3143 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3144 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3145 tcg_temp_free(EA); \
3146 }
3147
3148 #define GEN_LDUXF(name, ldop, opc, type) \
3149 static void glue(gen_, name##ux)(DisasContext *ctx) \
3150 { \
3151 TCGv EA; \
3152 if (unlikely(!ctx->fpu_enabled)) { \
3153 gen_exception(ctx, POWERPC_EXCP_FPU); \
3154 return; \
3155 } \
3156 if (unlikely(rA(ctx->opcode) == 0)) { \
3157 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3158 return; \
3159 } \
3160 gen_set_access_type(ctx, ACCESS_FLOAT); \
3161 EA = tcg_temp_new(); \
3162 gen_addr_reg_index(ctx, EA); \
3163 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3164 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3165 tcg_temp_free(EA); \
3166 }
3167
3168 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3169 static void glue(gen_, name##x)(DisasContext *ctx) \
3170 { \
3171 TCGv EA; \
3172 if (unlikely(!ctx->fpu_enabled)) { \
3173 gen_exception(ctx, POWERPC_EXCP_FPU); \
3174 return; \
3175 } \
3176 gen_set_access_type(ctx, ACCESS_FLOAT); \
3177 EA = tcg_temp_new(); \
3178 gen_addr_reg_index(ctx, EA); \
3179 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3180 tcg_temp_free(EA); \
3181 }
3182
3183 #define GEN_LDFS(name, ldop, op, type) \
3184 GEN_LDF(name, ldop, op | 0x20, type); \
3185 GEN_LDUF(name, ldop, op | 0x21, type); \
3186 GEN_LDUXF(name, ldop, op | 0x01, type); \
3187 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3188
3189 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3190 {
3191 TCGv t0 = tcg_temp_new();
3192 TCGv_i32 t1 = tcg_temp_new_i32();
3193 gen_qemu_ld32u(ctx, t0, arg2);
3194 tcg_gen_trunc_tl_i32(t1, t0);
3195 tcg_temp_free(t0);
3196 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3197 tcg_temp_free_i32(t1);
3198 }
3199
3200 /* lfd lfdu lfdux lfdx */
3201 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3202 /* lfs lfsu lfsux lfsx */
3203 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3204
3205 /*** Floating-point store ***/
3206 #define GEN_STF(name, stop, opc, type) \
3207 static void glue(gen_, name)(DisasContext *ctx) \
3208 { \
3209 TCGv EA; \
3210 if (unlikely(!ctx->fpu_enabled)) { \
3211 gen_exception(ctx, POWERPC_EXCP_FPU); \
3212 return; \
3213 } \
3214 gen_set_access_type(ctx, ACCESS_FLOAT); \
3215 EA = tcg_temp_new(); \
3216 gen_addr_imm_index(ctx, EA, 0); \
3217 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3218 tcg_temp_free(EA); \
3219 }
3220
3221 #define GEN_STUF(name, stop, opc, type) \
3222 static void glue(gen_, name##u)(DisasContext *ctx) \
3223 { \
3224 TCGv EA; \
3225 if (unlikely(!ctx->fpu_enabled)) { \
3226 gen_exception(ctx, POWERPC_EXCP_FPU); \
3227 return; \
3228 } \
3229 if (unlikely(rA(ctx->opcode) == 0)) { \
3230 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3231 return; \
3232 } \
3233 gen_set_access_type(ctx, ACCESS_FLOAT); \
3234 EA = tcg_temp_new(); \
3235 gen_addr_imm_index(ctx, EA, 0); \
3236 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3237 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3238 tcg_temp_free(EA); \
3239 }
3240
3241 #define GEN_STUXF(name, stop, opc, type) \
3242 static void glue(gen_, name##ux)(DisasContext *ctx) \
3243 { \
3244 TCGv EA; \
3245 if (unlikely(!ctx->fpu_enabled)) { \
3246 gen_exception(ctx, POWERPC_EXCP_FPU); \
3247 return; \
3248 } \
3249 if (unlikely(rA(ctx->opcode) == 0)) { \
3250 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3251 return; \
3252 } \
3253 gen_set_access_type(ctx, ACCESS_FLOAT); \
3254 EA = tcg_temp_new(); \
3255 gen_addr_reg_index(ctx, EA); \
3256 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3257 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3258 tcg_temp_free(EA); \
3259 }
3260
3261 #define GEN_STXF(name, stop, opc2, opc3, type) \
3262 static void glue(gen_, name##x)(DisasContext *ctx) \
3263 { \
3264 TCGv EA; \
3265 if (unlikely(!ctx->fpu_enabled)) { \
3266 gen_exception(ctx, POWERPC_EXCP_FPU); \
3267 return; \
3268 } \
3269 gen_set_access_type(ctx, ACCESS_FLOAT); \
3270 EA = tcg_temp_new(); \
3271 gen_addr_reg_index(ctx, EA); \
3272 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3273 tcg_temp_free(EA); \
3274 }
3275
3276 #define GEN_STFS(name, stop, op, type) \
3277 GEN_STF(name, stop, op | 0x20, type); \
3278 GEN_STUF(name, stop, op | 0x21, type); \
3279 GEN_STUXF(name, stop, op | 0x01, type); \
3280 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3281
3282 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3283 {
3284 TCGv_i32 t0 = tcg_temp_new_i32();
3285 TCGv t1 = tcg_temp_new();
3286 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3287 tcg_gen_extu_i32_tl(t1, t0);
3288 tcg_temp_free_i32(t0);
3289 gen_qemu_st32(ctx, t1, arg2);
3290 tcg_temp_free(t1);
3291 }
3292
3293 /* stfd stfdu stfdux stfdx */
3294 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3295 /* stfs stfsu stfsux stfsx */
3296 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3297
3298 /* Optional: */
3299 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3300 {
3301 TCGv t0 = tcg_temp_new();
3302 tcg_gen_trunc_i64_tl(t0, arg1),
3303 gen_qemu_st32(ctx, t0, arg2);
3304 tcg_temp_free(t0);
3305 }
3306 /* stfiwx */
3307 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3308
3309 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3310 {
3311 #if defined(TARGET_PPC64)
3312 if (ctx->has_cfar)
3313 tcg_gen_movi_tl(cpu_cfar, nip);
3314 #endif
3315 }
3316
3317 /*** Branch ***/
3318 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3319 {
3320 TranslationBlock *tb;
3321 tb = ctx->tb;
3322 #if defined(TARGET_PPC64)
3323 if (!ctx->sf_mode)
3324 dest = (uint32_t) dest;
3325 #endif
3326 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3327 likely(!ctx->singlestep_enabled)) {
3328 tcg_gen_goto_tb(n);
3329 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3330 tcg_gen_exit_tb((tcg_target_long)tb + n);
3331 } else {
3332 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3333 if (unlikely(ctx->singlestep_enabled)) {
3334 if ((ctx->singlestep_enabled &
3335 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3336 (ctx->exception == POWERPC_EXCP_BRANCH ||
3337 ctx->exception == POWERPC_EXCP_TRACE)) {
3338 target_ulong tmp = ctx->nip;
3339 ctx->nip = dest;
3340 gen_exception(ctx, POWERPC_EXCP_TRACE);
3341 ctx->nip = tmp;
3342 }
3343 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3344 gen_debug_exception(ctx);
3345 }
3346 }
3347 tcg_gen_exit_tb(0);
3348 }
3349 }
3350
3351 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3352 {
3353 #if defined(TARGET_PPC64)
3354 if (ctx->sf_mode == 0)
3355 tcg_gen_movi_tl(cpu_lr, (uint32_t)nip);
3356 else
3357 #endif
3358 tcg_gen_movi_tl(cpu_lr, nip);
3359 }
3360
3361 /* b ba bl bla */
3362 static void gen_b(DisasContext *ctx)
3363 {
3364 target_ulong li, target;
3365
3366 ctx->exception = POWERPC_EXCP_BRANCH;
3367 /* sign extend LI */
3368 #if defined(TARGET_PPC64)
3369 if (ctx->sf_mode)
3370 li = ((int64_t)LI(ctx->opcode) << 38) >> 38;
3371 else
3372 #endif
3373 li = ((int32_t)LI(ctx->opcode) << 6) >> 6;
3374 if (likely(AA(ctx->opcode) == 0))
3375 target = ctx->nip + li - 4;
3376 else
3377 target = li;
3378 if (LK(ctx->opcode))
3379 gen_setlr(ctx, ctx->nip);
3380 gen_update_cfar(ctx, ctx->nip);
3381 gen_goto_tb(ctx, 0, target);
3382 }
3383
3384 #define BCOND_IM 0
3385 #define BCOND_LR 1
3386 #define BCOND_CTR 2
3387
3388 static inline void gen_bcond(DisasContext *ctx, int type)
3389 {
3390 uint32_t bo = BO(ctx->opcode);
3391 int l1;
3392 TCGv target;
3393
3394 ctx->exception = POWERPC_EXCP_BRANCH;
3395 if (type == BCOND_LR || type == BCOND_CTR) {
3396 target = tcg_temp_local_new();
3397 if (type == BCOND_CTR)
3398 tcg_gen_mov_tl(target, cpu_ctr);
3399 else
3400 tcg_gen_mov_tl(target, cpu_lr);
3401 } else {
3402 TCGV_UNUSED(target);
3403 }
3404 if (LK(ctx->opcode))
3405 gen_setlr(ctx, ctx->nip);
3406 l1 = gen_new_label();
3407 if ((bo & 0x4) == 0) {
3408 /* Decrement and test CTR */
3409 TCGv temp = tcg_temp_new();
3410 if (unlikely(type == BCOND_CTR)) {
3411 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3412 return;
3413 }
3414 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3415 #if defined(TARGET_PPC64)
3416 if (!ctx->sf_mode)
3417 tcg_gen_ext32u_tl(temp, cpu_ctr);
3418 else
3419 #endif
3420 tcg_gen_mov_tl(temp, cpu_ctr);
3421 if (bo & 0x2) {
3422 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3423 } else {
3424 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3425 }
3426 tcg_temp_free(temp);
3427 }
3428 if ((bo & 0x10) == 0) {
3429 /* Test CR */
3430 uint32_t bi = BI(ctx->opcode);
3431 uint32_t mask = 1 << (3 - (bi & 0x03));
3432 TCGv_i32 temp = tcg_temp_new_i32();
3433
3434 if (bo & 0x8) {
3435 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3436 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3437 } else {
3438 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3439 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3440 }
3441 tcg_temp_free_i32(temp);
3442 }
3443 gen_update_cfar(ctx, ctx->nip);
3444 if (type == BCOND_IM) {
3445 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3446 if (likely(AA(ctx->opcode) == 0)) {
3447 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3448 } else {
3449 gen_goto_tb(ctx, 0, li);
3450 }
3451 gen_set_label(l1);
3452 gen_goto_tb(ctx, 1, ctx->nip);
3453 } else {
3454 #if defined(TARGET_PPC64)
3455 if (!(ctx->sf_mode))
3456 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3457 else
3458 #endif
3459 tcg_gen_andi_tl(cpu_nip, target, ~3);
3460 tcg_gen_exit_tb(0);
3461 gen_set_label(l1);
3462 #if defined(TARGET_PPC64)
3463 if (!(ctx->sf_mode))
3464 tcg_gen_movi_tl(cpu_nip, (uint32_t)ctx->nip);
3465 else
3466 #endif
3467 tcg_gen_movi_tl(cpu_nip, ctx->nip);
3468 tcg_gen_exit_tb(0);
3469 }
3470 }
3471
3472 static void gen_bc(DisasContext *ctx)
3473 {
3474 gen_bcond(ctx, BCOND_IM);
3475 }
3476
3477 static void gen_bcctr(DisasContext *ctx)
3478 {
3479 gen_bcond(ctx, BCOND_CTR);
3480 }
3481
3482 static void gen_bclr(DisasContext *ctx)
3483 {
3484 gen_bcond(ctx, BCOND_LR);
3485 }
3486
3487 /*** Condition register logical ***/
3488 #define GEN_CRLOGIC(name, tcg_op, opc) \
3489 static void glue(gen_, name)(DisasContext *ctx) \
3490 { \
3491 uint8_t bitmask; \
3492 int sh; \
3493 TCGv_i32 t0, t1; \
3494 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3495 t0 = tcg_temp_new_i32(); \
3496 if (sh > 0) \
3497 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3498 else if (sh < 0) \
3499 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3500 else \
3501 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3502 t1 = tcg_temp_new_i32(); \
3503 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3504 if (sh > 0) \
3505 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3506 else if (sh < 0) \
3507 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3508 else \
3509 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3510 tcg_op(t0, t0, t1); \
3511 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3512 tcg_gen_andi_i32(t0, t0, bitmask); \
3513 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3514 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3515 tcg_temp_free_i32(t0); \
3516 tcg_temp_free_i32(t1); \
3517 }
3518
3519 /* crand */
3520 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3521 /* crandc */
3522 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3523 /* creqv */
3524 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3525 /* crnand */
3526 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3527 /* crnor */
3528 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3529 /* cror */
3530 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3531 /* crorc */
3532 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3533 /* crxor */
3534 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3535
3536 /* mcrf */
3537 static void gen_mcrf(DisasContext *ctx)
3538 {
3539 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3540 }
3541
3542 /*** System linkage ***/
3543
3544 /* rfi (mem_idx only) */
3545 static void gen_rfi(DisasContext *ctx)
3546 {
3547 #if defined(CONFIG_USER_ONLY)
3548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3549 #else
3550 /* Restore CPU state */
3551 if (unlikely(!ctx->mem_idx)) {
3552 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3553 return;
3554 }
3555 gen_update_cfar(ctx, ctx->nip);
3556 gen_helper_rfi(cpu_env);
3557 gen_sync_exception(ctx);
3558 #endif
3559 }
3560
3561 #if defined(TARGET_PPC64)
3562 static void gen_rfid(DisasContext *ctx)
3563 {
3564 #if defined(CONFIG_USER_ONLY)
3565 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3566 #else
3567 /* Restore CPU state */
3568 if (unlikely(!ctx->mem_idx)) {
3569 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3570 return;
3571 }
3572 gen_update_cfar(ctx, ctx->nip);
3573 gen_helper_rfid(cpu_env);
3574 gen_sync_exception(ctx);
3575 #endif
3576 }
3577
3578 static void gen_hrfid(DisasContext *ctx)
3579 {
3580 #if defined(CONFIG_USER_ONLY)
3581 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3582 #else
3583 /* Restore CPU state */
3584 if (unlikely(ctx->mem_idx <= 1)) {
3585 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3586 return;
3587 }
3588 gen_helper_hrfid(cpu_env);
3589 gen_sync_exception(ctx);
3590 #endif
3591 }
3592 #endif
3593
3594 /* sc */
3595 #if defined(CONFIG_USER_ONLY)
3596 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3597 #else
3598 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3599 #endif
3600 static void gen_sc(DisasContext *ctx)
3601 {
3602 uint32_t lev;
3603
3604 lev = (ctx->opcode >> 5) & 0x7F;
3605 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3606 }
3607
3608 /*** Trap ***/
3609
3610 /* tw */
3611 static void gen_tw(DisasContext *ctx)
3612 {
3613 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3614 /* Update the nip since this might generate a trap exception */
3615 gen_update_nip(ctx, ctx->nip);
3616 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3617 t0);
3618 tcg_temp_free_i32(t0);
3619 }
3620
3621 /* twi */
3622 static void gen_twi(DisasContext *ctx)
3623 {
3624 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3625 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3626 /* Update the nip since this might generate a trap exception */
3627 gen_update_nip(ctx, ctx->nip);
3628 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3629 tcg_temp_free(t0);
3630 tcg_temp_free_i32(t1);
3631 }
3632
3633 #if defined(TARGET_PPC64)
3634 /* td */
3635 static void gen_td(DisasContext *ctx)
3636 {
3637 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3638 /* Update the nip since this might generate a trap exception */
3639 gen_update_nip(ctx, ctx->nip);
3640 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3641 t0);
3642 tcg_temp_free_i32(t0);
3643 }
3644
3645 /* tdi */
3646 static void gen_tdi(DisasContext *ctx)
3647 {
3648 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3649 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3650 /* Update the nip since this might generate a trap exception */
3651 gen_update_nip(ctx, ctx->nip);
3652 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3653 tcg_temp_free(t0);
3654 tcg_temp_free_i32(t1);
3655 }
3656 #endif
3657
3658 /*** Processor control ***/
3659
3660 static void gen_read_xer(TCGv dst)
3661 {
3662 TCGv t0 = tcg_temp_new();
3663 TCGv t1 = tcg_temp_new();
3664 TCGv t2 = tcg_temp_new();
3665 tcg_gen_mov_tl(dst, cpu_xer);
3666 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
3667 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
3668 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
3669 tcg_gen_or_tl(t0, t0, t1);
3670 tcg_gen_or_tl(dst, dst, t2);
3671 tcg_gen_or_tl(dst, dst, t0);
3672 tcg_temp_free(t0);
3673 tcg_temp_free(t1);
3674 tcg_temp_free(t2);
3675 }
3676
3677 static void gen_write_xer(TCGv src)
3678 {
3679 tcg_gen_andi_tl(cpu_xer, src,
3680 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
3681 tcg_gen_shri_tl(cpu_so, src, XER_SO);
3682 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
3683 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
3684 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
3685 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
3686 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
3687 }
3688
3689 /* mcrxr */
3690 static void gen_mcrxr(DisasContext *ctx)
3691 {
3692 TCGv_i32 t0 = tcg_temp_new_i32();
3693 TCGv_i32 t1 = tcg_temp_new_i32();
3694 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
3695
3696 tcg_gen_trunc_tl_i32(t0, cpu_so);
3697 tcg_gen_trunc_tl_i32(t1, cpu_ov);
3698 tcg_gen_trunc_tl_i32(dst, cpu_ca);
3699 tcg_gen_shri_i32(t0, t0, 2);
3700 tcg_gen_shri_i32(t1, t1, 1);
3701 tcg_gen_or_i32(dst, dst, t0);
3702 tcg_gen_or_i32(dst, dst, t1);
3703 tcg_temp_free_i32(t0);
3704 tcg_temp_free_i32(t1);
3705
3706 tcg_gen_movi_tl(cpu_so, 0);
3707 tcg_gen_movi_tl(cpu_ov, 0);
3708 tcg_gen_movi_tl(cpu_ca, 0);
3709 }
3710
3711 /* mfcr mfocrf */
3712 static void gen_mfcr(DisasContext *ctx)
3713 {
3714 uint32_t crm, crn;
3715
3716 if (likely(ctx->opcode & 0x00100000)) {
3717 crm = CRM(ctx->opcode);
3718 if (likely(crm && ((crm & (crm - 1)) == 0))) {
3719 crn = ctz32 (crm);
3720 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
3721 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
3722 cpu_gpr[rD(ctx->opcode)], crn * 4);
3723 }
3724 } else {
3725 TCGv_i32 t0 = tcg_temp_new_i32();
3726 tcg_gen_mov_i32(t0, cpu_crf[0]);
3727 tcg_gen_shli_i32(t0, t0, 4);
3728 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
3729 tcg_gen_shli_i32(t0, t0, 4);
3730 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
3731 tcg_gen_shli_i32(t0, t0, 4);
3732 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
3733 tcg_gen_shli_i32(t0, t0, 4);
3734 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
3735 tcg_gen_shli_i32(t0, t0, 4);
3736 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
3737 tcg_gen_shli_i32(t0, t0, 4);
3738 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
3739 tcg_gen_shli_i32(t0, t0, 4);
3740 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
3741 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
3742 tcg_temp_free_i32(t0);
3743 }
3744 }
3745
3746 /* mfmsr */
3747 static void gen_mfmsr(DisasContext *ctx)
3748 {
3749 #if defined(CONFIG_USER_ONLY)
3750 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3751 #else
3752 if (unlikely(!ctx->mem_idx)) {
3753 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3754 return;
3755 }
3756 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
3757 #endif
3758 }
3759
3760 static void spr_noaccess(void *opaque, int gprn, int sprn)
3761 {
3762 #if 0
3763 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
3764 printf("ERROR: try to access SPR %d !\n", sprn);
3765 #endif
3766 }
3767 #define SPR_NOACCESS (&spr_noaccess)
3768
3769 /* mfspr */
3770 static inline void gen_op_mfspr(DisasContext *ctx)
3771 {
3772 void (*read_cb)(void *opaque, int gprn, int sprn);
3773 uint32_t sprn = SPR(ctx->opcode);
3774
3775 #if !defined(CONFIG_USER_ONLY)
3776 if (ctx->mem_idx == 2)
3777 read_cb = ctx->spr_cb[sprn].hea_read;
3778 else if (ctx->mem_idx)
3779 read_cb = ctx->spr_cb[sprn].oea_read;
3780 else
3781 #endif
3782 read_cb = ctx->spr_cb[sprn].uea_read;
3783 if (likely(read_cb != NULL)) {
3784 if (likely(read_cb != SPR_NOACCESS)) {
3785 (*read_cb)(ctx, rD(ctx->opcode), sprn);
3786 } else {
3787 /* Privilege exception */
3788 /* This is a hack to avoid warnings when running Linux:
3789 * this OS breaks the PowerPC virtualisation model,
3790 * allowing userland application to read the PVR
3791 */
3792 if (sprn != SPR_PVR) {
3793 qemu_log("Trying to read privileged spr %d %03x at "
3794 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3795 printf("Trying to read privileged spr %d %03x at "
3796 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3797 }
3798 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3799 }
3800 } else {
3801 /* Not defined */
3802 qemu_log("Trying to read invalid spr %d %03x at "
3803 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3804 printf("Trying to read invalid spr %d %03x at " TARGET_FMT_lx "\n",
3805 sprn, sprn, ctx->nip);
3806 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3807 }
3808 }
3809
3810 static void gen_mfspr(DisasContext *ctx)
3811 {
3812 gen_op_mfspr(ctx);
3813 }
3814
3815 /* mftb */
3816 static void gen_mftb(DisasContext *ctx)
3817 {
3818 gen_op_mfspr(ctx);
3819 }
3820
3821 /* mtcrf mtocrf*/
3822 static void gen_mtcrf(DisasContext *ctx)
3823 {
3824 uint32_t crm, crn;
3825
3826 crm = CRM(ctx->opcode);
3827 if (likely((ctx->opcode & 0x00100000))) {
3828 if (crm && ((crm & (crm - 1)) == 0)) {
3829 TCGv_i32 temp = tcg_temp_new_i32();
3830 crn = ctz32 (crm);
3831 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3832 tcg_gen_shri_i32(temp, temp, crn * 4);
3833 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
3834 tcg_temp_free_i32(temp);
3835 }
3836 } else {
3837 TCGv_i32 temp = tcg_temp_new_i32();
3838 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
3839 for (crn = 0 ; crn < 8 ; crn++) {
3840 if (crm & (1 << crn)) {
3841 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
3842 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
3843 }
3844 }
3845 tcg_temp_free_i32(temp);
3846 }
3847 }
3848
3849 /* mtmsr */
3850 #if defined(TARGET_PPC64)
3851 static void gen_mtmsrd(DisasContext *ctx)
3852 {
3853 #if defined(CONFIG_USER_ONLY)
3854 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3855 #else
3856 if (unlikely(!ctx->mem_idx)) {
3857 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3858 return;
3859 }
3860 if (ctx->opcode & 0x00010000) {
3861 /* Special form that does not need any synchronisation */
3862 TCGv t0 = tcg_temp_new();
3863 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3864 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3865 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3866 tcg_temp_free(t0);
3867 } else {
3868 /* XXX: we need to update nip before the store
3869 * if we enter power saving mode, we will exit the loop
3870 * directly from ppc_store_msr
3871 */
3872 gen_update_nip(ctx, ctx->nip);
3873 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
3874 /* Must stop the translation as machine state (may have) changed */
3875 /* Note that mtmsr is not always defined as context-synchronizing */
3876 gen_stop_exception(ctx);
3877 }
3878 #endif
3879 }
3880 #endif
3881
3882 static void gen_mtmsr(DisasContext *ctx)
3883 {
3884 #if defined(CONFIG_USER_ONLY)
3885 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3886 #else
3887 if (unlikely(!ctx->mem_idx)) {
3888 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3889 return;
3890 }
3891 if (ctx->opcode & 0x00010000) {
3892 /* Special form that does not need any synchronisation */
3893 TCGv t0 = tcg_temp_new();
3894 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
3895 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
3896 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
3897 tcg_temp_free(t0);
3898 } else {
3899 TCGv msr = tcg_temp_new();
3900
3901 /* XXX: we need to update nip before the store
3902 * if we enter power saving mode, we will exit the loop
3903 * directly from ppc_store_msr
3904 */
3905 gen_update_nip(ctx, ctx->nip);
3906 #if defined(TARGET_PPC64)
3907 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
3908 #else
3909 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
3910 #endif
3911 gen_helper_store_msr(cpu_env, msr);
3912 /* Must stop the translation as machine state (may have) changed */
3913 /* Note that mtmsr is not always defined as context-synchronizing */
3914 gen_stop_exception(ctx);
3915 }
3916 #endif
3917 }
3918
3919 /* mtspr */
3920 static void gen_mtspr(DisasContext *ctx)
3921 {
3922 void (*write_cb)(void *opaque, int sprn, int gprn);
3923 uint32_t sprn = SPR(ctx->opcode);
3924
3925 #if !defined(CONFIG_USER_ONLY)
3926 if (ctx->mem_idx == 2)
3927 write_cb = ctx->spr_cb[sprn].hea_write;
3928 else if (ctx->mem_idx)
3929 write_cb = ctx->spr_cb[sprn].oea_write;
3930 else
3931 #endif
3932 write_cb = ctx->spr_cb[sprn].uea_write;
3933 if (likely(write_cb != NULL)) {
3934 if (likely(write_cb != SPR_NOACCESS)) {
3935 (*write_cb)(ctx, sprn, rS(ctx->opcode));
3936 } else {
3937 /* Privilege exception */
3938 qemu_log("Trying to write privileged spr %d %03x at "
3939 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3940 printf("Trying to write privileged spr %d %03x at " TARGET_FMT_lx
3941 "\n", sprn, sprn, ctx->nip);
3942 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
3943 }
3944 } else {
3945 /* Not defined */
3946 qemu_log("Trying to write invalid spr %d %03x at "
3947 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip);
3948 printf("Trying to write invalid spr %d %03x at " TARGET_FMT_lx "\n",
3949 sprn, sprn, ctx->nip);
3950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
3951 }
3952 }
3953
3954 /*** Cache management ***/
3955
3956 /* dcbf */
3957 static void gen_dcbf(DisasContext *ctx)
3958 {
3959 /* XXX: specification says this is treated as a load by the MMU */
3960 TCGv t0;
3961 gen_set_access_type(ctx, ACCESS_CACHE);
3962 t0 = tcg_temp_new();
3963 gen_addr_reg_index(ctx, t0);
3964 gen_qemu_ld8u(ctx, t0, t0);
3965 tcg_temp_free(t0);
3966 }
3967
3968 /* dcbi (Supervisor only) */
3969 static void gen_dcbi(DisasContext *ctx)
3970 {
3971 #if defined(CONFIG_USER_ONLY)
3972 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3973 #else
3974 TCGv EA, val;
3975 if (unlikely(!ctx->mem_idx)) {
3976 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3977 return;
3978 }
3979 EA = tcg_temp_new();
3980 gen_set_access_type(ctx, ACCESS_CACHE);
3981 gen_addr_reg_index(ctx, EA);
3982 val = tcg_temp_new();
3983 /* XXX: specification says this should be treated as a store by the MMU */
3984 gen_qemu_ld8u(ctx, val, EA);
3985 gen_qemu_st8(ctx, val, EA);
3986 tcg_temp_free(val);
3987 tcg_temp_free(EA);
3988 #endif
3989 }
3990
3991 /* dcdst */
3992 static void gen_dcbst(DisasContext *ctx)
3993 {
3994 /* XXX: specification say this is treated as a load by the MMU */
3995 TCGv t0;
3996 gen_set_access_type(ctx, ACCESS_CACHE);
3997 t0 = tcg_temp_new();
3998 gen_addr_reg_index(ctx, t0);
3999 gen_qemu_ld8u(ctx, t0, t0);
4000 tcg_temp_free(t0);
4001 }
4002
4003 /* dcbt */
4004 static void gen_dcbt(DisasContext *ctx)
4005 {
4006 /* interpreted as no-op */
4007 /* XXX: specification say this is treated as a load by the MMU
4008 * but does not generate any exception
4009 */
4010 }
4011
4012 /* dcbtst */
4013 static void gen_dcbtst(DisasContext *ctx)
4014 {
4015 /* interpreted as no-op */
4016 /* XXX: specification say this is treated as a load by the MMU
4017 * but does not generate any exception
4018 */
4019 }
4020
4021 /* dcbz */
4022 static void gen_dcbz(DisasContext *ctx)
4023 {
4024 TCGv tcgv_addr;
4025 TCGv_i32 tcgv_is_dcbzl;
4026 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4027
4028 gen_set_access_type(ctx, ACCESS_CACHE);
4029 /* NIP cannot be restored if the memory exception comes from an helper */
4030 gen_update_nip(ctx, ctx->nip - 4);
4031 tcgv_addr = tcg_temp_new();
4032 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4033
4034 gen_addr_reg_index(ctx, tcgv_addr);
4035 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4036
4037 tcg_temp_free(tcgv_addr);
4038 tcg_temp_free_i32(tcgv_is_dcbzl);
4039 }
4040
4041 /* dst / dstt */
4042 static void gen_dst(DisasContext *ctx)
4043 {
4044 if (rA(ctx->opcode) == 0) {
4045 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4046 } else {
4047 /* interpreted as no-op */
4048 }
4049 }
4050
4051 /* dstst /dststt */
4052 static void gen_dstst(DisasContext *ctx)
4053 {
4054 if (rA(ctx->opcode) == 0) {
4055 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4056 } else {
4057 /* interpreted as no-op */
4058 }
4059
4060 }
4061
4062 /* dss / dssall */
4063 static void gen_dss(DisasContext *ctx)
4064 {
4065 /* interpreted as no-op */
4066 }
4067
4068 /* icbi */
4069 static void gen_icbi(DisasContext *ctx)
4070 {
4071 TCGv t0;
4072 gen_set_access_type(ctx, ACCESS_CACHE);
4073 /* NIP cannot be restored if the memory exception comes from an helper */
4074 gen_update_nip(ctx, ctx->nip - 4);
4075 t0 = tcg_temp_new();
4076 gen_addr_reg_index(ctx, t0);
4077 gen_helper_icbi(cpu_env, t0);
4078 tcg_temp_free(t0);
4079 }
4080
4081 /* Optional: */
4082 /* dcba */
4083 static void gen_dcba(DisasContext *ctx)
4084 {
4085 /* interpreted as no-op */
4086 /* XXX: specification say this is treated as a store by the MMU
4087 * but does not generate any exception
4088 */
4089 }
4090
4091 /*** Segment register manipulation ***/
4092 /* Supervisor only: */
4093
4094 /* mfsr */
4095 static void gen_mfsr(DisasContext *ctx)
4096 {
4097 #if defined(CONFIG_USER_ONLY)
4098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4099 #else
4100 TCGv t0;
4101 if (unlikely(!ctx->mem_idx)) {
4102 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4103 return;
4104 }
4105 t0 = tcg_const_tl(SR(ctx->opcode));
4106 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4107 tcg_temp_free(t0);
4108 #endif
4109 }
4110
4111 /* mfsrin */
4112 static void gen_mfsrin(DisasContext *ctx)
4113 {
4114 #if defined(CONFIG_USER_ONLY)
4115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4116 #else
4117 TCGv t0;
4118 if (unlikely(!ctx->mem_idx)) {
4119 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4120 return;
4121 }
4122 t0 = tcg_temp_new();
4123 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4124 tcg_gen_andi_tl(t0, t0, 0xF);
4125 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4126 tcg_temp_free(t0);
4127 #endif
4128 }
4129
4130 /* mtsr */
4131 static void gen_mtsr(DisasContext *ctx)
4132 {
4133 #if defined(CONFIG_USER_ONLY)
4134 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4135 #else
4136 TCGv t0;
4137 if (unlikely(!ctx->mem_idx)) {
4138 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4139 return;
4140 }
4141 t0 = tcg_const_tl(SR(ctx->opcode));
4142 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4143 tcg_temp_free(t0);
4144 #endif
4145 }
4146
4147 /* mtsrin */
4148 static void gen_mtsrin(DisasContext *ctx)
4149 {
4150 #if defined(CONFIG_USER_ONLY)
4151 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4152 #else
4153 TCGv t0;
4154 if (unlikely(!ctx->mem_idx)) {
4155 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4156 return;
4157 }
4158 t0 = tcg_temp_new();
4159 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4160 tcg_gen_andi_tl(t0, t0, 0xF);
4161 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4162 tcg_temp_free(t0);
4163 #endif
4164 }
4165
4166 #if defined(TARGET_PPC64)
4167 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4168
4169 /* mfsr */
4170 static void gen_mfsr_64b(DisasContext *ctx)
4171 {
4172 #if defined(CONFIG_USER_ONLY)
4173 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4174 #else
4175 TCGv t0;
4176 if (unlikely(!ctx->mem_idx)) {
4177 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4178 return;
4179 }
4180 t0 = tcg_const_tl(SR(ctx->opcode));
4181 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4182 tcg_temp_free(t0);
4183 #endif
4184 }
4185
4186 /* mfsrin */
4187 static void gen_mfsrin_64b(DisasContext *ctx)
4188 {
4189 #if defined(CONFIG_USER_ONLY)
4190 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4191 #else
4192 TCGv t0;
4193 if (unlikely(!ctx->mem_idx)) {
4194 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4195 return;
4196 }
4197 t0 = tcg_temp_new();
4198 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4199 tcg_gen_andi_tl(t0, t0, 0xF);
4200 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4201 tcg_temp_free(t0);
4202 #endif
4203 }
4204
4205 /* mtsr */
4206 static void gen_mtsr_64b(DisasContext *ctx)
4207 {
4208 #if defined(CONFIG_USER_ONLY)
4209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4210 #else
4211 TCGv t0;
4212 if (unlikely(!ctx->mem_idx)) {
4213 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4214 return;
4215 }
4216 t0 = tcg_const_tl(SR(ctx->opcode));
4217 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4218 tcg_temp_free(t0);
4219 #endif
4220 }
4221
4222 /* mtsrin */
4223 static void gen_mtsrin_64b(DisasContext *ctx)
4224 {
4225 #if defined(CONFIG_USER_ONLY)
4226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4227 #else
4228 TCGv t0;
4229 if (unlikely(!ctx->mem_idx)) {
4230 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4231 return;
4232 }
4233 t0 = tcg_temp_new();
4234 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4235 tcg_gen_andi_tl(t0, t0, 0xF);
4236 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4237 tcg_temp_free(t0);
4238 #endif
4239 }
4240
4241 /* slbmte */
4242 static void gen_slbmte(DisasContext *ctx)
4243 {
4244 #if defined(CONFIG_USER_ONLY)
4245 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4246 #else
4247 if (unlikely(!ctx->mem_idx)) {
4248 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4249 return;
4250 }
4251 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4252 cpu_gpr[rS(ctx->opcode)]);
4253 #endif
4254 }
4255
4256 static void gen_slbmfee(DisasContext *ctx)
4257 {
4258 #if defined(CONFIG_USER_ONLY)
4259 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4260 #else
4261 if (unlikely(!ctx->mem_idx)) {
4262 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4263 return;
4264 }
4265 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4266 cpu_gpr[rB(ctx->opcode)]);
4267 #endif
4268 }
4269
4270 static void gen_slbmfev(DisasContext *ctx)
4271 {
4272 #if defined(CONFIG_USER_ONLY)
4273 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4274 #else
4275 if (unlikely(!ctx->mem_idx)) {
4276 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4277 return;
4278 }
4279 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4280 cpu_gpr[rB(ctx->opcode)]);
4281 #endif
4282 }
4283 #endif /* defined(TARGET_PPC64) */
4284
4285 /*** Lookaside buffer management ***/
4286 /* Optional & mem_idx only: */
4287
4288 /* tlbia */
4289 static void gen_tlbia(DisasContext *ctx)
4290 {
4291 #if defined(CONFIG_USER_ONLY)
4292 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4293 #else
4294 if (unlikely(!ctx->mem_idx)) {
4295 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4296 return;
4297 }
4298 gen_helper_tlbia(cpu_env);
4299 #endif
4300 }
4301
4302 /* tlbiel */
4303 static void gen_tlbiel(DisasContext *ctx)
4304 {
4305 #if defined(CONFIG_USER_ONLY)
4306 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4307 #else
4308 if (unlikely(!ctx->mem_idx)) {
4309 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4310 return;
4311 }
4312 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4313 #endif
4314 }
4315
4316 /* tlbie */
4317 static void gen_tlbie(DisasContext *ctx)
4318 {
4319 #if defined(CONFIG_USER_ONLY)
4320 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4321 #else
4322 if (unlikely(!ctx->mem_idx)) {
4323 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4324 return;
4325 }
4326 #if defined(TARGET_PPC64)
4327 if (!ctx->sf_mode) {
4328 TCGv t0 = tcg_temp_new();
4329 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4330 gen_helper_tlbie(cpu_env, t0);
4331 tcg_temp_free(t0);
4332 } else
4333 #endif
4334 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4335 #endif
4336 }
4337
4338 /* tlbsync */
4339 static void gen_tlbsync(DisasContext *ctx)
4340 {
4341 #if defined(CONFIG_USER_ONLY)
4342 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4343 #else
4344 if (unlikely(!ctx->mem_idx)) {
4345 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4346 return;
4347 }
4348 /* This has no effect: it should ensure that all previous
4349 * tlbie have completed
4350 */
4351 gen_stop_exception(ctx);
4352 #endif
4353 }
4354
4355 #if defined(TARGET_PPC64)
4356 /* slbia */
4357 static void gen_slbia(DisasContext *ctx)
4358 {
4359 #if defined(CONFIG_USER_ONLY)
4360 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4361 #else
4362 if (unlikely(!ctx->mem_idx)) {
4363 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4364 return;
4365 }
4366 gen_helper_slbia(cpu_env);
4367 #endif
4368 }
4369
4370 /* slbie */
4371 static void gen_slbie(DisasContext *ctx)
4372 {
4373 #if defined(CONFIG_USER_ONLY)
4374 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4375 #else
4376 if (unlikely(!ctx->mem_idx)) {
4377 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4378 return;
4379 }
4380 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4381 #endif
4382 }
4383 #endif
4384
4385 /*** External control ***/
4386 /* Optional: */
4387
4388 /* eciwx */
4389 static void gen_eciwx(DisasContext *ctx)
4390 {
4391 TCGv t0;
4392 /* Should check EAR[E] ! */
4393 gen_set_access_type(ctx, ACCESS_EXT);
4394 t0 = tcg_temp_new();
4395 gen_addr_reg_index(ctx, t0);
4396 gen_check_align(ctx, t0, 0x03);
4397 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4398 tcg_temp_free(t0);
4399 }
4400
4401 /* ecowx */
4402 static void gen_ecowx(DisasContext *ctx)
4403 {
4404 TCGv t0;
4405 /* Should check EAR[E] ! */
4406 gen_set_access_type(ctx, ACCESS_EXT);
4407 t0 = tcg_temp_new();
4408 gen_addr_reg_index(ctx, t0);
4409 gen_check_align(ctx, t0, 0x03);
4410 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4411 tcg_temp_free(t0);
4412 }
4413
4414 /* PowerPC 601 specific instructions */
4415
4416 /* abs - abs. */
4417 static void gen_abs(DisasContext *ctx)
4418 {
4419 int l1 = gen_new_label();
4420 int l2 = gen_new_label();
4421 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4422 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4423 tcg_gen_br(l2);
4424 gen_set_label(l1);
4425 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4426 gen_set_label(l2);
4427 if (unlikely(Rc(ctx->opcode) != 0))
4428 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4429 }
4430
4431 /* abso - abso. */
4432 static void gen_abso(DisasContext *ctx)
4433 {
4434 int l1 = gen_new_label();
4435 int l2 = gen_new_label();
4436 int l3 = gen_new_label();
4437 /* Start with XER OV disabled, the most likely case */
4438 tcg_gen_movi_tl(cpu_ov, 0);
4439 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4440 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4441 tcg_gen_movi_tl(cpu_ov, 1);
4442 tcg_gen_movi_tl(cpu_so, 1);
4443 tcg_gen_br(l2);
4444 gen_set_label(l1);
4445 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4446 tcg_gen_br(l3);
4447 gen_set_label(l2);
4448 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4449 gen_set_label(l3);
4450 if (unlikely(Rc(ctx->opcode) != 0))
4451 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4452 }
4453
4454 /* clcs */
4455 static void gen_clcs(DisasContext *ctx)
4456 {
4457 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4458 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4459 tcg_temp_free_i32(t0);
4460 /* Rc=1 sets CR0 to an undefined state */
4461 }
4462
4463 /* div - div. */
4464 static void gen_div(DisasContext *ctx)
4465 {
4466 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4467 cpu_gpr[rB(ctx->opcode)]);
4468 if (unlikely(Rc(ctx->opcode) != 0))
4469 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4470 }
4471
4472 /* divo - divo. */
4473 static void gen_divo(DisasContext *ctx)
4474 {
4475 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4476 cpu_gpr[rB(ctx->opcode)]);
4477 if (unlikely(Rc(ctx->opcode) != 0))
4478 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4479 }
4480
4481 /* divs - divs. */
4482 static void gen_divs(DisasContext *ctx)
4483 {
4484 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4485 cpu_gpr[rB(ctx->opcode)]);
4486 if (unlikely(Rc(ctx->opcode) != 0))
4487 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4488 }
4489
4490 /* divso - divso. */
4491 static void gen_divso(DisasContext *ctx)
4492 {
4493 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4494 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4495 if (unlikely(Rc(ctx->opcode) != 0))
4496 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4497 }
4498
4499 /* doz - doz. */
4500 static void gen_doz(DisasContext *ctx)
4501 {
4502 int l1 = gen_new_label();
4503 int l2 = gen_new_label();
4504 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4505 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4506 tcg_gen_br(l2);
4507 gen_set_label(l1);
4508 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4509 gen_set_label(l2);
4510 if (unlikely(Rc(ctx->opcode) != 0))
4511 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4512 }
4513
4514 /* dozo - dozo. */
4515 static void gen_dozo(DisasContext *ctx)
4516 {
4517 int l1 = gen_new_label();
4518 int l2 = gen_new_label();
4519 TCGv t0 = tcg_temp_new();
4520 TCGv t1 = tcg_temp_new();
4521 TCGv t2 = tcg_temp_new();
4522 /* Start with XER OV disabled, the most likely case */
4523 tcg_gen_movi_tl(cpu_ov, 0);
4524 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4525 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4526 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4527 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4528 tcg_gen_andc_tl(t1, t1, t2);
4529 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4530 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4531 tcg_gen_movi_tl(cpu_ov, 1);
4532 tcg_gen_movi_tl(cpu_so, 1);
4533 tcg_gen_br(l2);
4534 gen_set_label(l1);
4535 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4536 gen_set_label(l2);
4537 tcg_temp_free(t0);
4538 tcg_temp_free(t1);
4539 tcg_temp_free(t2);
4540 if (unlikely(Rc(ctx->opcode) != 0))
4541 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4542 }
4543
4544 /* dozi */
4545 static void gen_dozi(DisasContext *ctx)
4546 {
4547 target_long simm = SIMM(ctx->opcode);
4548 int l1 = gen_new_label();
4549 int l2 = gen_new_label();
4550 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4551 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4552 tcg_gen_br(l2);
4553 gen_set_label(l1);
4554 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4555 gen_set_label(l2);
4556 if (unlikely(Rc(ctx->opcode) != 0))
4557 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4558 }
4559
4560 /* lscbx - lscbx. */
4561 static void gen_lscbx(DisasContext *ctx)
4562 {
4563 TCGv t0 = tcg_temp_new();
4564 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4565 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4566 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4567
4568 gen_addr_reg_index(ctx, t0);
4569 /* NIP cannot be restored if the memory exception comes from an helper */
4570 gen_update_nip(ctx, ctx->nip - 4);
4571 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4572 tcg_temp_free_i32(t1);
4573 tcg_temp_free_i32(t2);
4574 tcg_temp_free_i32(t3);
4575 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4576 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4577 if (unlikely(Rc(ctx->opcode) != 0))
4578 gen_set_Rc0(ctx, t0);
4579 tcg_temp_free(t0);
4580 }
4581
4582 /* maskg - maskg. */
4583 static void gen_maskg(DisasContext *ctx)
4584 {
4585 int l1 = gen_new_label();
4586 TCGv t0 = tcg_temp_new();
4587 TCGv t1 = tcg_temp_new();
4588 TCGv t2 = tcg_temp_new();
4589 TCGv t3 = tcg_temp_new();
4590 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4591 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4592 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4593 tcg_gen_addi_tl(t2, t0, 1);
4594 tcg_gen_shr_tl(t2, t3, t2);
4595 tcg_gen_shr_tl(t3, t3, t1);
4596 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4597 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4598 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4599 gen_set_label(l1);
4600 tcg_temp_free(t0);
4601 tcg_temp_free(t1);
4602 tcg_temp_free(t2);
4603 tcg_temp_free(t3);
4604 if (unlikely(Rc(ctx->opcode) != 0))
4605 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4606 }
4607
4608 /* maskir - maskir. */
4609 static void gen_maskir(DisasContext *ctx)
4610 {
4611 TCGv t0 = tcg_temp_new();
4612 TCGv t1 = tcg_temp_new();
4613 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4614 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4615 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4616 tcg_temp_free(t0);
4617 tcg_temp_free(t1);
4618 if (unlikely(Rc(ctx->opcode) != 0))
4619 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4620 }
4621
4622 /* mul - mul. */
4623 static void gen_mul(DisasContext *ctx)
4624 {
4625 TCGv_i64 t0 = tcg_temp_new_i64();
4626 TCGv_i64 t1 = tcg_temp_new_i64();
4627 TCGv t2 = tcg_temp_new();
4628 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4629 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4630 tcg_gen_mul_i64(t0, t0, t1);
4631 tcg_gen_trunc_i64_tl(t2, t0);
4632 gen_store_spr(SPR_MQ, t2);
4633 tcg_gen_shri_i64(t1, t0, 32);
4634 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4635 tcg_temp_free_i64(t0);
4636 tcg_temp_free_i64(t1);
4637 tcg_temp_free(t2);
4638 if (unlikely(Rc(ctx->opcode) != 0))
4639 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4640 }
4641
4642 /* mulo - mulo. */
4643 static void gen_mulo(DisasContext *ctx)
4644 {
4645 int l1 = gen_new_label();
4646 TCGv_i64 t0 = tcg_temp_new_i64();
4647 TCGv_i64 t1 = tcg_temp_new_i64();
4648 TCGv t2 = tcg_temp_new();
4649 /* Start with XER OV disabled, the most likely case */
4650 tcg_gen_movi_tl(cpu_ov, 0);
4651 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4652 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4653 tcg_gen_mul_i64(t0, t0, t1);
4654 tcg_gen_trunc_i64_tl(t2, t0);
4655 gen_store_spr(SPR_MQ, t2);
4656 tcg_gen_shri_i64(t1, t0, 32);
4657 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4658 tcg_gen_ext32s_i64(t1, t0);
4659 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
4660 tcg_gen_movi_tl(cpu_ov, 1);
4661 tcg_gen_movi_tl(cpu_so, 1);
4662 gen_set_label(l1);
4663 tcg_temp_free_i64(t0);
4664 tcg_temp_free_i64(t1);
4665 tcg_temp_free(t2);
4666 if (unlikely(Rc(ctx->opcode) != 0))
4667 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4668 }
4669
4670 /* nabs - nabs. */
4671 static void gen_nabs(DisasContext *ctx)
4672 {
4673 int l1 = gen_new_label();
4674 int l2 = gen_new_label();
4675 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4676 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4677 tcg_gen_br(l2);
4678 gen_set_label(l1);
4679 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4680 gen_set_label(l2);
4681 if (unlikely(Rc(ctx->opcode) != 0))
4682 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4683 }
4684
4685 /* nabso - nabso. */
4686 static void gen_nabso(DisasContext *ctx)
4687 {
4688 int l1 = gen_new_label();
4689 int l2 = gen_new_label();
4690 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
4691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4692 tcg_gen_br(l2);
4693 gen_set_label(l1);
4694 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4695 gen_set_label(l2);
4696 /* nabs never overflows */
4697 tcg_gen_movi_tl(cpu_ov, 0);
4698 if (unlikely(Rc(ctx->opcode) != 0))
4699 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4700 }
4701
4702 /* rlmi - rlmi. */
4703 static void gen_rlmi(DisasContext *ctx)
4704 {
4705 uint32_t mb = MB(ctx->opcode);
4706 uint32_t me = ME(ctx->opcode);
4707 TCGv t0 = tcg_temp_new();
4708 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4709 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4710 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
4711 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
4712 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
4713 tcg_temp_free(t0);
4714 if (unlikely(Rc(ctx->opcode) != 0))
4715 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4716 }
4717
4718 /* rrib - rrib. */
4719 static void gen_rrib(DisasContext *ctx)
4720 {
4721 TCGv t0 = tcg_temp_new();
4722 TCGv t1 = tcg_temp_new();
4723 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4724 tcg_gen_movi_tl(t1, 0x80000000);
4725 tcg_gen_shr_tl(t1, t1, t0);
4726 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4727 tcg_gen_and_tl(t0, t0, t1);
4728 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
4729 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4730 tcg_temp_free(t0);
4731 tcg_temp_free(t1);
4732 if (unlikely(Rc(ctx->opcode) != 0))
4733 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4734 }
4735
4736 /* sle - sle. */
4737 static void gen_sle(DisasContext *ctx)
4738 {
4739 TCGv t0 = tcg_temp_new();
4740 TCGv t1 = tcg_temp_new();
4741 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4742 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4743 tcg_gen_subfi_tl(t1, 32, t1);
4744 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4745 tcg_gen_or_tl(t1, t0, t1);
4746 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4747 gen_store_spr(SPR_MQ, t1);
4748 tcg_temp_free(t0);
4749 tcg_temp_free(t1);
4750 if (unlikely(Rc(ctx->opcode) != 0))
4751 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4752 }
4753
4754 /* sleq - sleq. */
4755 static void gen_sleq(DisasContext *ctx)
4756 {
4757 TCGv t0 = tcg_temp_new();
4758 TCGv t1 = tcg_temp_new();
4759 TCGv t2 = tcg_temp_new();
4760 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4761 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
4762 tcg_gen_shl_tl(t2, t2, t0);
4763 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4764 gen_load_spr(t1, SPR_MQ);
4765 gen_store_spr(SPR_MQ, t0);
4766 tcg_gen_and_tl(t0, t0, t2);
4767 tcg_gen_andc_tl(t1, t1, t2);
4768 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4769 tcg_temp_free(t0);
4770 tcg_temp_free(t1);
4771 tcg_temp_free(t2);
4772 if (unlikely(Rc(ctx->opcode) != 0))
4773 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4774 }
4775
4776 /* sliq - sliq. */
4777 static void gen_sliq(DisasContext *ctx)
4778 {
4779 int sh = SH(ctx->opcode);
4780 TCGv t0 = tcg_temp_new();
4781 TCGv t1 = tcg_temp_new();
4782 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4783 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4784 tcg_gen_or_tl(t1, t0, t1);
4785 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4786 gen_store_spr(SPR_MQ, t1);
4787 tcg_temp_free(t0);
4788 tcg_temp_free(t1);
4789 if (unlikely(Rc(ctx->opcode) != 0))
4790 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4791 }
4792
4793 /* slliq - slliq. */
4794 static void gen_slliq(DisasContext *ctx)
4795 {
4796 int sh = SH(ctx->opcode);
4797 TCGv t0 = tcg_temp_new();
4798 TCGv t1 = tcg_temp_new();
4799 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4800 gen_load_spr(t1, SPR_MQ);
4801 gen_store_spr(SPR_MQ, t0);
4802 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
4803 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
4804 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4805 tcg_temp_free(t0);
4806 tcg_temp_free(t1);
4807 if (unlikely(Rc(ctx->opcode) != 0))
4808 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4809 }
4810
4811 /* sllq - sllq. */
4812 static void gen_sllq(DisasContext *ctx)
4813 {
4814 int l1 = gen_new_label();
4815 int l2 = gen_new_label();
4816 TCGv t0 = tcg_temp_local_new();
4817 TCGv t1 = tcg_temp_local_new();
4818 TCGv t2 = tcg_temp_local_new();
4819 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4820 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4821 tcg_gen_shl_tl(t1, t1, t2);
4822 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4823 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
4824 gen_load_spr(t0, SPR_MQ);
4825 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4826 tcg_gen_br(l2);
4827 gen_set_label(l1);
4828 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4829 gen_load_spr(t2, SPR_MQ);
4830 tcg_gen_andc_tl(t1, t2, t1);
4831 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4832 gen_set_label(l2);
4833 tcg_temp_free(t0);
4834 tcg_temp_free(t1);
4835 tcg_temp_free(t2);
4836 if (unlikely(Rc(ctx->opcode) != 0))
4837 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4838 }
4839
4840 /* slq - slq. */
4841 static void gen_slq(DisasContext *ctx)
4842 {
4843 int l1 = gen_new_label();
4844 TCGv t0 = tcg_temp_new();
4845 TCGv t1 = tcg_temp_new();
4846 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4847 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4848 tcg_gen_subfi_tl(t1, 32, t1);
4849 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4850 tcg_gen_or_tl(t1, t0, t1);
4851 gen_store_spr(SPR_MQ, t1);
4852 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
4853 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4854 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4855 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
4856 gen_set_label(l1);
4857 tcg_temp_free(t0);
4858 tcg_temp_free(t1);
4859 if (unlikely(Rc(ctx->opcode) != 0))
4860 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4861 }
4862
4863 /* sraiq - sraiq. */
4864 static void gen_sraiq(DisasContext *ctx)
4865 {
4866 int sh = SH(ctx->opcode);
4867 int l1 = gen_new_label();
4868 TCGv t0 = tcg_temp_new();
4869 TCGv t1 = tcg_temp_new();
4870 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4871 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4872 tcg_gen_or_tl(t0, t0, t1);
4873 gen_store_spr(SPR_MQ, t0);
4874 tcg_gen_movi_tl(cpu_ca, 0);
4875 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
4876 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
4877 tcg_gen_movi_tl(cpu_ca, 1);
4878 gen_set_label(l1);
4879 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
4880 tcg_temp_free(t0);
4881 tcg_temp_free(t1);
4882 if (unlikely(Rc(ctx->opcode) != 0))
4883 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4884 }
4885
4886 /* sraq - sraq. */
4887 static void gen_sraq(DisasContext *ctx)
4888 {
4889 int l1 = gen_new_label();
4890 int l2 = gen_new_label();
4891 TCGv t0 = tcg_temp_new();
4892 TCGv t1 = tcg_temp_local_new();
4893 TCGv t2 = tcg_temp_local_new();
4894 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
4895 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
4896 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
4897 tcg_gen_subfi_tl(t2, 32, t2);
4898 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
4899 tcg_gen_or_tl(t0, t0, t2);
4900 gen_store_spr(SPR_MQ, t0);
4901 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
4902 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
4903 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
4904 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
4905 gen_set_label(l1);
4906 tcg_temp_free(t0);
4907 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
4908 tcg_gen_movi_tl(cpu_ca, 0);
4909 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4910 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
4911 tcg_gen_movi_tl(cpu_ca, 1);
4912 gen_set_label(l2);
4913 tcg_temp_free(t1);
4914 tcg_temp_free(t2);
4915 if (unlikely(Rc(ctx->opcode) != 0))
4916 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4917 }
4918
4919 /* sre - sre. */
4920 static void gen_sre(DisasContext *ctx)
4921 {
4922 TCGv t0 = tcg_temp_new();
4923 TCGv t1 = tcg_temp_new();
4924 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4925 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4926 tcg_gen_subfi_tl(t1, 32, t1);
4927 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
4928 tcg_gen_or_tl(t1, t0, t1);
4929 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4930 gen_store_spr(SPR_MQ, t1);
4931 tcg_temp_free(t0);
4932 tcg_temp_free(t1);
4933 if (unlikely(Rc(ctx->opcode) != 0))
4934 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4935 }
4936
4937 /* srea - srea. */
4938 static void gen_srea(DisasContext *ctx)
4939 {
4940 TCGv t0 = tcg_temp_new();
4941 TCGv t1 = tcg_temp_new();
4942 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
4943 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
4944 gen_store_spr(SPR_MQ, t0);
4945 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
4946 tcg_temp_free(t0);
4947 tcg_temp_free(t1);
4948 if (unlikely(Rc(ctx->opcode) != 0))
4949 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4950 }
4951
4952 /* sreq */
4953 static void gen_sreq(DisasContext *ctx)
4954 {
4955 TCGv t0 = tcg_temp_new();
4956 TCGv t1 = tcg_temp_new();
4957 TCGv t2 = tcg_temp_new();
4958 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4959 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
4960 tcg_gen_shr_tl(t1, t1, t0);
4961 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
4962 gen_load_spr(t2, SPR_MQ);
4963 gen_store_spr(SPR_MQ, t0);
4964 tcg_gen_and_tl(t0, t0, t1);
4965 tcg_gen_andc_tl(t2, t2, t1);
4966 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
4967 tcg_temp_free(t0);
4968 tcg_temp_free(t1);
4969 tcg_temp_free(t2);
4970 if (unlikely(Rc(ctx->opcode) != 0))
4971 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4972 }
4973
4974 /* sriq */
4975 static void gen_sriq(DisasContext *ctx)
4976 {
4977 int sh = SH(ctx->opcode);
4978 TCGv t0 = tcg_temp_new();
4979 TCGv t1 = tcg_temp_new();
4980 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4981 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
4982 tcg_gen_or_tl(t1, t0, t1);
4983 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
4984 gen_store_spr(SPR_MQ, t1);
4985 tcg_temp_free(t0);
4986 tcg_temp_free(t1);
4987 if (unlikely(Rc(ctx->opcode) != 0))
4988 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4989 }
4990
4991 /* srliq */
4992 static void gen_srliq(DisasContext *ctx)
4993 {
4994 int sh = SH(ctx->opcode);
4995 TCGv t0 = tcg_temp_new();
4996 TCGv t1 = tcg_temp_new();
4997 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
4998 gen_load_spr(t1, SPR_MQ);
4999 gen_store_spr(SPR_MQ, t0);
5000 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5001 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5002 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5003 tcg_temp_free(t0);
5004 tcg_temp_free(t1);
5005 if (unlikely(Rc(ctx->opcode) != 0))
5006 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5007 }
5008
5009 /* srlq */
5010 static void gen_srlq(DisasContext *ctx)
5011 {
5012 int l1 = gen_new_label();
5013 int l2 = gen_new_label();
5014 TCGv t0 = tcg_temp_local_new();
5015 TCGv t1 = tcg_temp_local_new();
5016 TCGv t2 = tcg_temp_local_new();
5017 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5018 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5019 tcg_gen_shr_tl(t2, t1, t2);
5020 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5021 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5022 gen_load_spr(t0, SPR_MQ);
5023 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5024 tcg_gen_br(l2);
5025 gen_set_label(l1);
5026 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5027 tcg_gen_and_tl(t0, t0, t2);
5028 gen_load_spr(t1, SPR_MQ);
5029 tcg_gen_andc_tl(t1, t1, t2);
5030 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5031 gen_set_label(l2);
5032 tcg_temp_free(t0);
5033 tcg_temp_free(t1);
5034 tcg_temp_free(t2);
5035 if (unlikely(Rc(ctx->opcode) != 0))
5036 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5037 }
5038
5039 /* srq */
5040 static void gen_srq(DisasContext *ctx)
5041 {
5042 int l1 = gen_new_label();
5043 TCGv t0 = tcg_temp_new();
5044 TCGv t1 = tcg_temp_new();
5045 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5046 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5047 tcg_gen_subfi_tl(t1, 32, t1);
5048 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5049 tcg_gen_or_tl(t1, t0, t1);
5050 gen_store_spr(SPR_MQ, t1);
5051 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5052 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5053 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5054 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5055 gen_set_label(l1);
5056 tcg_temp_free(t0);
5057 tcg_temp_free(t1);
5058 if (unlikely(Rc(ctx->opcode) != 0))
5059 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5060 }
5061
5062 /* PowerPC 602 specific instructions */
5063
5064 /* dsa */
5065 static void gen_dsa(DisasContext *ctx)
5066 {
5067 /* XXX: TODO */
5068 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5069 }
5070
5071 /* esa */
5072 static void gen_esa(DisasContext *ctx)
5073 {
5074 /* XXX: TODO */
5075 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5076 }
5077
5078 /* mfrom */
5079 static void gen_mfrom(DisasContext *ctx)
5080 {
5081 #if defined(CONFIG_USER_ONLY)
5082 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5083 #else
5084 if (unlikely(!ctx->mem_idx)) {
5085 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5086 return;
5087 }
5088 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5089 #endif
5090 }
5091
5092 /* 602 - 603 - G2 TLB management */
5093
5094 /* tlbld */
5095 static void gen_tlbld_6xx(DisasContext *ctx)
5096 {
5097 #if defined(CONFIG_USER_ONLY)
5098 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5099 #else
5100 if (unlikely(!ctx->mem_idx)) {
5101 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5102 return;
5103 }
5104 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5105 #endif
5106 }
5107
5108 /* tlbli */
5109 static void gen_tlbli_6xx(DisasContext *ctx)
5110 {
5111 #if defined(CONFIG_USER_ONLY)
5112 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5113 #else
5114 if (unlikely(!ctx->mem_idx)) {
5115 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5116 return;
5117 }
5118 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5119 #endif
5120 }
5121
5122 /* 74xx TLB management */
5123
5124 /* tlbld */
5125 static void gen_tlbld_74xx(DisasContext *ctx)
5126 {
5127 #if defined(CONFIG_USER_ONLY)
5128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5129 #else
5130 if (unlikely(!ctx->mem_idx)) {
5131 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5132 return;
5133 }
5134 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5135 #endif
5136 }
5137
5138 /* tlbli */
5139 static void gen_tlbli_74xx(DisasContext *ctx)
5140 {
5141 #if defined(CONFIG_USER_ONLY)
5142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5143 #else
5144 if (unlikely(!ctx->mem_idx)) {
5145 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5146 return;
5147 }
5148 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5149 #endif
5150 }
5151
5152 /* POWER instructions not in PowerPC 601 */
5153
5154 /* clf */
5155 static void gen_clf(DisasContext *ctx)
5156 {
5157 /* Cache line flush: implemented as no-op */
5158 }
5159
5160 /* cli */
5161 static void gen_cli(DisasContext *ctx)
5162 {
5163 /* Cache line invalidate: privileged and treated as no-op */
5164 #if defined(CONFIG_USER_ONLY)
5165 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5166 #else
5167 if (unlikely(!ctx->mem_idx)) {
5168 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5169 return;
5170 }
5171 #endif
5172 }
5173
5174 /* dclst */
5175 static void gen_dclst(DisasContext *ctx)
5176 {
5177 /* Data cache line store: treated as no-op */
5178 }
5179
5180 static void gen_mfsri(DisasContext *ctx)
5181 {
5182 #if defined(CONFIG_USER_ONLY)
5183 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5184 #else
5185 int ra = rA(ctx->opcode);
5186 int rd = rD(ctx->opcode);
5187 TCGv t0;
5188 if (unlikely(!ctx->mem_idx)) {
5189 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5190 return;
5191 }
5192 t0 = tcg_temp_new();
5193 gen_addr_reg_index(ctx, t0);
5194 tcg_gen_shri_tl(t0, t0, 28);
5195 tcg_gen_andi_tl(t0, t0, 0xF);
5196 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5197 tcg_temp_free(t0);
5198 if (ra != 0 && ra != rd)
5199 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5200 #endif
5201 }
5202
5203 static void gen_rac(DisasContext *ctx)
5204 {
5205 #if defined(CONFIG_USER_ONLY)
5206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5207 #else
5208 TCGv t0;
5209 if (unlikely(!ctx->mem_idx)) {
5210 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5211 return;
5212 }
5213 t0 = tcg_temp_new();
5214 gen_addr_reg_index(ctx, t0);
5215 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5216 tcg_temp_free(t0);
5217 #endif
5218 }
5219
5220 static void gen_rfsvc(DisasContext *ctx)
5221 {
5222 #if defined(CONFIG_USER_ONLY)
5223 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5224 #else
5225 if (unlikely(!ctx->mem_idx)) {
5226 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5227 return;
5228 }
5229 gen_helper_rfsvc(cpu_env);
5230 gen_sync_exception(ctx);
5231 #endif
5232 }
5233
5234 /* svc is not implemented for now */
5235
5236 /* POWER2 specific instructions */
5237 /* Quad manipulation (load/store two floats at a time) */
5238
5239 /* lfq */
5240 static void gen_lfq(DisasContext *ctx)
5241 {
5242 int rd = rD(ctx->opcode);
5243 TCGv t0;
5244 gen_set_access_type(ctx, ACCESS_FLOAT);
5245 t0 = tcg_temp_new();
5246 gen_addr_imm_index(ctx, t0, 0);
5247 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5248 gen_addr_add(ctx, t0, t0, 8);
5249 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5250 tcg_temp_free(t0);
5251 }
5252
5253 /* lfqu */
5254 static void gen_lfqu(DisasContext *ctx)
5255 {
5256 int ra = rA(ctx->opcode);
5257 int rd = rD(ctx->opcode);
5258 TCGv t0, t1;
5259 gen_set_access_type(ctx, ACCESS_FLOAT);
5260 t0 = tcg_temp_new();
5261 t1 = tcg_temp_new();
5262 gen_addr_imm_index(ctx, t0, 0);
5263 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5264 gen_addr_add(ctx, t1, t0, 8);
5265 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5266 if (ra != 0)
5267 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5268 tcg_temp_free(t0);
5269 tcg_temp_free(t1);
5270 }
5271
5272 /* lfqux */
5273 static void gen_lfqux(DisasContext *ctx)
5274 {
5275 int ra = rA(ctx->opcode);
5276 int rd = rD(ctx->opcode);
5277 gen_set_access_type(ctx, ACCESS_FLOAT);
5278 TCGv t0, t1;
5279 t0 = tcg_temp_new();
5280 gen_addr_reg_index(ctx, t0);
5281 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5282 t1 = tcg_temp_new();
5283 gen_addr_add(ctx, t1, t0, 8);
5284 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5285 tcg_temp_free(t1);
5286 if (ra != 0)
5287 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5288 tcg_temp_free(t0);
5289 }
5290
5291 /* lfqx */
5292 static void gen_lfqx(DisasContext *ctx)
5293 {
5294 int rd = rD(ctx->opcode);
5295 TCGv t0;
5296 gen_set_access_type(ctx, ACCESS_FLOAT);
5297 t0 = tcg_temp_new();
5298 gen_addr_reg_index(ctx, t0);
5299 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5300 gen_addr_add(ctx, t0, t0, 8);
5301 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5302 tcg_temp_free(t0);
5303 }
5304
5305 /* stfq */
5306 static void gen_stfq(DisasContext *ctx)
5307 {
5308 int rd = rD(ctx->opcode);
5309 TCGv t0;
5310 gen_set_access_type(ctx, ACCESS_FLOAT);
5311 t0 = tcg_temp_new();
5312 gen_addr_imm_index(ctx, t0, 0);
5313 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5314 gen_addr_add(ctx, t0, t0, 8);
5315 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5316 tcg_temp_free(t0);
5317 }
5318
5319 /* stfqu */
5320 static void gen_stfqu(DisasContext *ctx)
5321 {
5322 int ra = rA(ctx->opcode);
5323 int rd = rD(ctx->opcode);
5324 TCGv t0, t1;
5325 gen_set_access_type(ctx, ACCESS_FLOAT);
5326 t0 = tcg_temp_new();
5327 gen_addr_imm_index(ctx, t0, 0);
5328 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5329 t1 = tcg_temp_new();
5330 gen_addr_add(ctx, t1, t0, 8);
5331 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5332 tcg_temp_free(t1);
5333 if (ra != 0)
5334 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5335 tcg_temp_free(t0);
5336 }
5337
5338 /* stfqux */
5339 static void gen_stfqux(DisasContext *ctx)
5340 {
5341 int ra = rA(ctx->opcode);
5342 int rd = rD(ctx->opcode);
5343 TCGv t0, t1;
5344 gen_set_access_type(ctx, ACCESS_FLOAT);
5345 t0 = tcg_temp_new();
5346 gen_addr_reg_index(ctx, t0);
5347 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5348 t1 = tcg_temp_new();
5349 gen_addr_add(ctx, t1, t0, 8);
5350 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5351 tcg_temp_free(t1);
5352 if (ra != 0)
5353 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5354 tcg_temp_free(t0);
5355 }
5356
5357 /* stfqx */
5358 static void gen_stfqx(DisasContext *ctx)
5359 {
5360 int rd = rD(ctx->opcode);
5361 TCGv t0;
5362 gen_set_access_type(ctx, ACCESS_FLOAT);
5363 t0 = tcg_temp_new();
5364 gen_addr_reg_index(ctx, t0);
5365 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5366 gen_addr_add(ctx, t0, t0, 8);
5367 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5368 tcg_temp_free(t0);
5369 }
5370
5371 /* BookE specific instructions */
5372
5373 /* XXX: not implemented on 440 ? */
5374 static void gen_mfapidi(DisasContext *ctx)
5375 {
5376 /* XXX: TODO */
5377 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5378 }
5379
5380 /* XXX: not implemented on 440 ? */
5381 static void gen_tlbiva(DisasContext *ctx)
5382 {
5383 #if defined(CONFIG_USER_ONLY)
5384 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5385 #else
5386 TCGv t0;
5387 if (unlikely(!ctx->mem_idx)) {
5388 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5389 return;
5390 }
5391 t0 = tcg_temp_new();
5392 gen_addr_reg_index(ctx, t0);
5393 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5394 tcg_temp_free(t0);
5395 #endif
5396 }
5397
5398 /* All 405 MAC instructions are translated here */
5399 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5400 int ra, int rb, int rt, int Rc)
5401 {
5402 TCGv t0, t1;
5403
5404 t0 = tcg_temp_local_new();
5405 t1 = tcg_temp_local_new();
5406
5407 switch (opc3 & 0x0D) {
5408 case 0x05:
5409 /* macchw - macchw. - macchwo - macchwo. */
5410 /* macchws - macchws. - macchwso - macchwso. */
5411 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5412 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5413 /* mulchw - mulchw. */
5414 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5415 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5416 tcg_gen_ext16s_tl(t1, t1);
5417 break;
5418 case 0x04:
5419 /* macchwu - macchwu. - macchwuo - macchwuo. */
5420 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5421 /* mulchwu - mulchwu. */
5422 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5423 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5424 tcg_gen_ext16u_tl(t1, t1);
5425 break;
5426 case 0x01:
5427 /* machhw - machhw. - machhwo - machhwo. */
5428 /* machhws - machhws. - machhwso - machhwso. */
5429 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5430 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5431 /* mulhhw - mulhhw. */
5432 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5433 tcg_gen_ext16s_tl(t0, t0);
5434 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5435 tcg_gen_ext16s_tl(t1, t1);
5436 break;
5437 case 0x00:
5438 /* machhwu - machhwu. - machhwuo - machhwuo. */
5439 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5440 /* mulhhwu - mulhhwu. */
5441 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5442 tcg_gen_ext16u_tl(t0, t0);
5443 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5444 tcg_gen_ext16u_tl(t1, t1);
5445 break;
5446 case 0x0D:
5447 /* maclhw - maclhw. - maclhwo - maclhwo. */
5448 /* maclhws - maclhws. - maclhwso - maclhwso. */
5449 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5450 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5451 /* mullhw - mullhw. */
5452 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5453 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5454 break;
5455 case 0x0C:
5456 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5457 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5458 /* mullhwu - mullhwu. */
5459 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5460 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5461 break;
5462 }
5463 if (opc2 & 0x04) {
5464 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5465 tcg_gen_mul_tl(t1, t0, t1);
5466 if (opc2 & 0x02) {
5467 /* nmultiply-and-accumulate (0x0E) */
5468 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5469 } else {
5470 /* multiply-and-accumulate (0x0C) */
5471 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5472 }
5473
5474 if (opc3 & 0x12) {
5475 /* Check overflow and/or saturate */
5476 int l1 = gen_new_label();
5477
5478 if (opc3 & 0x10) {
5479 /* Start with XER OV disabled, the most likely case */
5480 tcg_gen_movi_tl(cpu_ov, 0);
5481 }
5482 if (opc3 & 0x01) {
5483 /* Signed */
5484 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5485 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5486 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5487 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5488 if (opc3 & 0x02) {
5489 /* Saturate */
5490 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5491 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5492 }
5493 } else {
5494 /* Unsigned */
5495 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5496 if (opc3 & 0x02) {
5497 /* Saturate */
5498 tcg_gen_movi_tl(t0, UINT32_MAX);
5499 }
5500 }
5501 if (opc3 & 0x10) {
5502 /* Check overflow */
5503 tcg_gen_movi_tl(cpu_ov, 1);
5504 tcg_gen_movi_tl(cpu_so, 1);
5505 }
5506 gen_set_label(l1);
5507 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5508 }
5509 } else {
5510 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5511 }
5512 tcg_temp_free(t0);
5513 tcg_temp_free(t1);
5514 if (unlikely(Rc) != 0) {
5515 /* Update Rc0 */
5516 gen_set_Rc0(ctx, cpu_gpr[rt]);
5517 }
5518 }
5519
5520 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5521 static void glue(gen_, name)(DisasContext *ctx) \
5522 { \
5523 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5524 rD(ctx->opcode), Rc(ctx->opcode)); \
5525 }
5526
5527 /* macchw - macchw. */
5528 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5529 /* macchwo - macchwo. */
5530 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5531 /* macchws - macchws. */
5532 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5533 /* macchwso - macchwso. */
5534 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5535 /* macchwsu - macchwsu. */
5536 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5537 /* macchwsuo - macchwsuo. */
5538 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5539 /* macchwu - macchwu. */
5540 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5541 /* macchwuo - macchwuo. */
5542 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5543 /* machhw - machhw. */
5544 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5545 /* machhwo - machhwo. */
5546 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5547 /* machhws - machhws. */
5548 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5549 /* machhwso - machhwso. */
5550 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5551 /* machhwsu - machhwsu. */
5552 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5553 /* machhwsuo - machhwsuo. */
5554 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5555 /* machhwu - machhwu. */
5556 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5557 /* machhwuo - machhwuo. */
5558 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5559 /* maclhw - maclhw. */
5560 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5561 /* maclhwo - maclhwo. */
5562 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5563 /* maclhws - maclhws. */
5564 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5565 /* maclhwso - maclhwso. */
5566 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5567 /* maclhwu - maclhwu. */
5568 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5569 /* maclhwuo - maclhwuo. */
5570 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5571 /* maclhwsu - maclhwsu. */
5572 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5573 /* maclhwsuo - maclhwsuo. */
5574 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5575 /* nmacchw - nmacchw. */
5576 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5577 /* nmacchwo - nmacchwo. */
5578 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5579 /* nmacchws - nmacchws. */
5580 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5581 /* nmacchwso - nmacchwso. */
5582 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5583 /* nmachhw - nmachhw. */
5584 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5585 /* nmachhwo - nmachhwo. */
5586 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5587 /* nmachhws - nmachhws. */
5588 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5589 /* nmachhwso - nmachhwso. */
5590 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5591 /* nmaclhw - nmaclhw. */
5592 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5593 /* nmaclhwo - nmaclhwo. */
5594 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5595 /* nmaclhws - nmaclhws. */
5596 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5597 /* nmaclhwso - nmaclhwso. */
5598 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5599
5600 /* mulchw - mulchw. */
5601 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5602 /* mulchwu - mulchwu. */
5603 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5604 /* mulhhw - mulhhw. */
5605 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5606 /* mulhhwu - mulhhwu. */
5607 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5608 /* mullhw - mullhw. */
5609 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5610 /* mullhwu - mullhwu. */
5611 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5612
5613 /* mfdcr */
5614 static void gen_mfdcr(DisasContext *ctx)
5615 {
5616 #if defined(CONFIG_USER_ONLY)
5617 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5618 #else
5619 TCGv dcrn;
5620 if (unlikely(!ctx->mem_idx)) {
5621 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5622 return;
5623 }
5624 /* NIP cannot be restored if the memory exception comes from an helper */
5625 gen_update_nip(ctx, ctx->nip - 4);
5626 dcrn = tcg_const_tl(SPR(ctx->opcode));
5627 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5628 tcg_temp_free(dcrn);
5629 #endif
5630 }
5631
5632 /* mtdcr */
5633 static void gen_mtdcr(DisasContext *ctx)
5634 {
5635 #if defined(CONFIG_USER_ONLY)
5636 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5637 #else
5638 TCGv dcrn;
5639 if (unlikely(!ctx->mem_idx)) {
5640 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5641 return;
5642 }
5643 /* NIP cannot be restored if the memory exception comes from an helper */
5644 gen_update_nip(ctx, ctx->nip - 4);
5645 dcrn = tcg_const_tl(SPR(ctx->opcode));
5646 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
5647 tcg_temp_free(dcrn);
5648 #endif
5649 }
5650
5651 /* mfdcrx */
5652 /* XXX: not implemented on 440 ? */
5653 static void gen_mfdcrx(DisasContext *ctx)
5654 {
5655 #if defined(CONFIG_USER_ONLY)
5656 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5657 #else
5658 if (unlikely(!ctx->mem_idx)) {
5659 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5660 return;
5661 }
5662 /* NIP cannot be restored if the memory exception comes from an helper */
5663 gen_update_nip(ctx, ctx->nip - 4);
5664 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5665 cpu_gpr[rA(ctx->opcode)]);
5666 /* Note: Rc update flag set leads to undefined state of Rc0 */
5667 #endif
5668 }
5669
5670 /* mtdcrx */
5671 /* XXX: not implemented on 440 ? */
5672 static void gen_mtdcrx(DisasContext *ctx)
5673 {
5674 #if defined(CONFIG_USER_ONLY)
5675 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5676 #else
5677 if (unlikely(!ctx->mem_idx)) {
5678 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5679 return;
5680 }
5681 /* NIP cannot be restored if the memory exception comes from an helper */
5682 gen_update_nip(ctx, ctx->nip - 4);
5683 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5684 cpu_gpr[rS(ctx->opcode)]);
5685 /* Note: Rc update flag set leads to undefined state of Rc0 */
5686 #endif
5687 }
5688
5689 /* mfdcrux (PPC 460) : user-mode access to DCR */
5690 static void gen_mfdcrux(DisasContext *ctx)
5691 {
5692 /* NIP cannot be restored if the memory exception comes from an helper */
5693 gen_update_nip(ctx, ctx->nip - 4);
5694 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
5695 cpu_gpr[rA(ctx->opcode)]);
5696 /* Note: Rc update flag set leads to undefined state of Rc0 */
5697 }
5698
5699 /* mtdcrux (PPC 460) : user-mode access to DCR */
5700 static void gen_mtdcrux(DisasContext *ctx)
5701 {
5702 /* NIP cannot be restored if the memory exception comes from an helper */
5703 gen_update_nip(ctx, ctx->nip - 4);
5704 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
5705 cpu_gpr[rS(ctx->opcode)]);
5706 /* Note: Rc update flag set leads to undefined state of Rc0 */
5707 }
5708
5709 /* dccci */
5710 static void gen_dccci(DisasContext *ctx)
5711 {
5712 #if defined(CONFIG_USER_ONLY)
5713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5714 #else
5715 if (unlikely(!ctx->mem_idx)) {
5716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5717 return;
5718 }
5719 /* interpreted as no-op */
5720 #endif
5721 }
5722
5723 /* dcread */
5724 static void gen_dcread(DisasContext *ctx)
5725 {
5726 #if defined(CONFIG_USER_ONLY)
5727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5728 #else
5729 TCGv EA, val;
5730 if (unlikely(!ctx->mem_idx)) {
5731 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5732 return;
5733 }
5734 gen_set_access_type(ctx, ACCESS_CACHE);
5735 EA = tcg_temp_new();
5736 gen_addr_reg_index(ctx, EA);
5737 val = tcg_temp_new();
5738 gen_qemu_ld32u(ctx, val, EA);
5739 tcg_temp_free(val);
5740 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
5741 tcg_temp_free(EA);
5742 #endif
5743 }
5744
5745 /* icbt */
5746 static void gen_icbt_40x(DisasContext *ctx)
5747 {
5748 /* interpreted as no-op */
5749 /* XXX: specification say this is treated as a load by the MMU
5750 * but does not generate any exception
5751 */
5752 }
5753
5754 /* iccci */
5755 static void gen_iccci(DisasContext *ctx)
5756 {
5757 #if defined(CONFIG_USER_ONLY)
5758 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5759 #else
5760 if (unlikely(!ctx->mem_idx)) {
5761 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5762 return;
5763 }
5764 /* interpreted as no-op */
5765 #endif
5766 }
5767
5768 /* icread */
5769 static void gen_icread(DisasContext *ctx)
5770 {
5771 #if defined(CONFIG_USER_ONLY)
5772 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5773 #else
5774 if (unlikely(!ctx->mem_idx)) {
5775 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5776 return;
5777 }
5778 /* interpreted as no-op */
5779 #endif
5780 }
5781
5782 /* rfci (mem_idx only) */
5783 static void gen_rfci_40x(DisasContext *ctx)
5784 {
5785 #if defined(CONFIG_USER_ONLY)
5786 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5787 #else
5788 if (unlikely(!ctx->mem_idx)) {
5789 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5790 return;
5791 }
5792 /* Restore CPU state */
5793 gen_helper_40x_rfci(cpu_env);
5794 gen_sync_exception(ctx);
5795 #endif
5796 }
5797
5798 static void gen_rfci(DisasContext *ctx)
5799 {
5800 #if defined(CONFIG_USER_ONLY)
5801 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5802 #else
5803 if (unlikely(!ctx->mem_idx)) {
5804 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5805 return;
5806 }
5807 /* Restore CPU state */
5808 gen_helper_rfci(cpu_env);
5809 gen_sync_exception(ctx);
5810 #endif
5811 }
5812
5813 /* BookE specific */
5814
5815 /* XXX: not implemented on 440 ? */
5816 static void gen_rfdi(DisasContext *ctx)
5817 {
5818 #if defined(CONFIG_USER_ONLY)
5819 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5820 #else
5821 if (unlikely(!ctx->mem_idx)) {
5822 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5823 return;
5824 }
5825 /* Restore CPU state */
5826 gen_helper_rfdi(cpu_env);
5827 gen_sync_exception(ctx);
5828 #endif
5829 }
5830
5831 /* XXX: not implemented on 440 ? */
5832 static void gen_rfmci(DisasContext *ctx)
5833 {
5834 #if defined(CONFIG_USER_ONLY)
5835 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5836 #else
5837 if (unlikely(!ctx->mem_idx)) {
5838 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5839 return;
5840 }
5841 /* Restore CPU state */
5842 gen_helper_rfmci(cpu_env);
5843 gen_sync_exception(ctx);
5844 #endif
5845 }
5846
5847 /* TLB management - PowerPC 405 implementation */
5848
5849 /* tlbre */
5850 static void gen_tlbre_40x(DisasContext *ctx)
5851 {
5852 #if defined(CONFIG_USER_ONLY)
5853 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5854 #else
5855 if (unlikely(!ctx->mem_idx)) {
5856 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5857 return;
5858 }
5859 switch (rB(ctx->opcode)) {
5860 case 0:
5861 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
5862 cpu_gpr[rA(ctx->opcode)]);
5863 break;
5864 case 1:
5865 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
5866 cpu_gpr[rA(ctx->opcode)]);
5867 break;
5868 default:
5869 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5870 break;
5871 }
5872 #endif
5873 }
5874
5875 /* tlbsx - tlbsx. */
5876 static void gen_tlbsx_40x(DisasContext *ctx)
5877 {
5878 #if defined(CONFIG_USER_ONLY)
5879 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5880 #else
5881 TCGv t0;
5882 if (unlikely(!ctx->mem_idx)) {
5883 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5884 return;
5885 }
5886 t0 = tcg_temp_new();
5887 gen_addr_reg_index(ctx, t0);
5888 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5889 tcg_temp_free(t0);
5890 if (Rc(ctx->opcode)) {
5891 int l1 = gen_new_label();
5892 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5893 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5894 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5895 gen_set_label(l1);
5896 }
5897 #endif
5898 }
5899
5900 /* tlbwe */
5901 static void gen_tlbwe_40x(DisasContext *ctx)
5902 {
5903 #if defined(CONFIG_USER_ONLY)
5904 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5905 #else
5906 if (unlikely(!ctx->mem_idx)) {
5907 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5908 return;
5909 }
5910 switch (rB(ctx->opcode)) {
5911 case 0:
5912 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
5913 cpu_gpr[rS(ctx->opcode)]);
5914 break;
5915 case 1:
5916 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
5917 cpu_gpr[rS(ctx->opcode)]);
5918 break;
5919 default:
5920 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5921 break;
5922 }
5923 #endif
5924 }
5925
5926 /* TLB management - PowerPC 440 implementation */
5927
5928 /* tlbre */
5929 static void gen_tlbre_440(DisasContext *ctx)
5930 {
5931 #if defined(CONFIG_USER_ONLY)
5932 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5933 #else
5934 if (unlikely(!ctx->mem_idx)) {
5935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5936 return;
5937 }
5938 switch (rB(ctx->opcode)) {
5939 case 0:
5940 case 1:
5941 case 2:
5942 {
5943 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5944 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
5945 t0, cpu_gpr[rA(ctx->opcode)]);
5946 tcg_temp_free_i32(t0);
5947 }
5948 break;
5949 default:
5950 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5951 break;
5952 }
5953 #endif
5954 }
5955
5956 /* tlbsx - tlbsx. */
5957 static void gen_tlbsx_440(DisasContext *ctx)
5958 {
5959 #if defined(CONFIG_USER_ONLY)
5960 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5961 #else
5962 TCGv t0;
5963 if (unlikely(!ctx->mem_idx)) {
5964 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5965 return;
5966 }
5967 t0 = tcg_temp_new();
5968 gen_addr_reg_index(ctx, t0);
5969 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5970 tcg_temp_free(t0);
5971 if (Rc(ctx->opcode)) {
5972 int l1 = gen_new_label();
5973 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
5974 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
5975 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
5976 gen_set_label(l1);
5977 }
5978 #endif
5979 }
5980
5981 /* tlbwe */
5982 static void gen_tlbwe_440(DisasContext *ctx)
5983 {
5984 #if defined(CONFIG_USER_ONLY)
5985 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5986 #else
5987 if (unlikely(!ctx->mem_idx)) {
5988 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5989 return;
5990 }
5991 switch (rB(ctx->opcode)) {
5992 case 0:
5993 case 1:
5994 case 2:
5995 {
5996 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
5997 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
5998 cpu_gpr[rS(ctx->opcode)]);
5999 tcg_temp_free_i32(t0);
6000 }
6001 break;
6002 default:
6003 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6004 break;
6005 }
6006 #endif
6007 }
6008
6009 /* TLB management - PowerPC BookE 2.06 implementation */
6010
6011 /* tlbre */
6012 static void gen_tlbre_booke206(DisasContext *ctx)
6013 {
6014 #if defined(CONFIG_USER_ONLY)
6015 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6016 #else
6017 if (unlikely(!ctx->mem_idx)) {
6018 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6019 return;
6020 }
6021
6022 gen_helper_booke206_tlbre(cpu_env);
6023 #endif
6024 }
6025
6026 /* tlbsx - tlbsx. */
6027 static void gen_tlbsx_booke206(DisasContext *ctx)
6028 {
6029 #if defined(CONFIG_USER_ONLY)
6030 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6031 #else
6032 TCGv t0;
6033 if (unlikely(!ctx->mem_idx)) {
6034 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6035 return;
6036 }
6037
6038 if (rA(ctx->opcode)) {
6039 t0 = tcg_temp_new();
6040 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6041 } else {
6042 t0 = tcg_const_tl(0);
6043 }
6044
6045 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6046 gen_helper_booke206_tlbsx(cpu_env, t0);
6047 #endif
6048 }
6049
6050 /* tlbwe */
6051 static void gen_tlbwe_booke206(DisasContext *ctx)
6052 {
6053 #if defined(CONFIG_USER_ONLY)
6054 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6055 #else
6056 if (unlikely(!ctx->mem_idx)) {
6057 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6058 return;
6059 }
6060 gen_update_nip(ctx, ctx->nip - 4);
6061 gen_helper_booke206_tlbwe(cpu_env);
6062 #endif
6063 }
6064
6065 static void gen_tlbivax_booke206(DisasContext *ctx)
6066 {
6067 #if defined(CONFIG_USER_ONLY)
6068 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6069 #else
6070 TCGv t0;
6071 if (unlikely(!ctx->mem_idx)) {
6072 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6073 return;
6074 }
6075
6076 t0 = tcg_temp_new();
6077 gen_addr_reg_index(ctx, t0);
6078
6079 gen_helper_booke206_tlbivax(cpu_env, t0);
6080 #endif
6081 }
6082
6083 static void gen_tlbilx_booke206(DisasContext *ctx)
6084 {
6085 #if defined(CONFIG_USER_ONLY)
6086 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6087 #else
6088 TCGv t0;
6089 if (unlikely(!ctx->mem_idx)) {
6090 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6091 return;
6092 }
6093
6094 t0 = tcg_temp_new();
6095 gen_addr_reg_index(ctx, t0);
6096
6097 switch((ctx->opcode >> 21) & 0x3) {
6098 case 0:
6099 gen_helper_booke206_tlbilx0(cpu_env, t0);
6100 break;
6101 case 1:
6102 gen_helper_booke206_tlbilx1(cpu_env, t0);
6103 break;
6104 case 3:
6105 gen_helper_booke206_tlbilx3(cpu_env, t0);
6106 break;
6107 default:
6108 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6109 break;
6110 }
6111
6112 tcg_temp_free(t0);
6113 #endif
6114 }
6115
6116
6117 /* wrtee */
6118 static void gen_wrtee(DisasContext *ctx)
6119 {
6120 #if defined(CONFIG_USER_ONLY)
6121 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6122 #else
6123 TCGv t0;
6124 if (unlikely(!ctx->mem_idx)) {
6125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6126 return;
6127 }
6128 t0 = tcg_temp_new();
6129 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6130 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6131 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6132 tcg_temp_free(t0);
6133 /* Stop translation to have a chance to raise an exception
6134 * if we just set msr_ee to 1
6135 */
6136 gen_stop_exception(ctx);
6137 #endif
6138 }
6139
6140 /* wrteei */
6141 static void gen_wrteei(DisasContext *ctx)
6142 {
6143 #if defined(CONFIG_USER_ONLY)
6144 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6145 #else
6146 if (unlikely(!ctx->mem_idx)) {
6147 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6148 return;
6149 }
6150 if (ctx->opcode & 0x00008000) {
6151 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6152 /* Stop translation to have a chance to raise an exception */
6153 gen_stop_exception(ctx);
6154 } else {
6155 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6156 }
6157 #endif
6158 }
6159
6160 /* PowerPC 440 specific instructions */
6161
6162 /* dlmzb */
6163 static void gen_dlmzb(DisasContext *ctx)
6164 {
6165 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6166 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6167 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6168 tcg_temp_free_i32(t0);
6169 }
6170
6171 /* mbar replaces eieio on 440 */
6172 static void gen_mbar(DisasContext *ctx)
6173 {
6174 /* interpreted as no-op */
6175 }
6176
6177 /* msync replaces sync on 440 */
6178 static void gen_msync_4xx(DisasContext *ctx)
6179 {
6180 /* interpreted as no-op */
6181 }
6182
6183 /* icbt */
6184 static void gen_icbt_440(DisasContext *ctx)
6185 {
6186 /* interpreted as no-op */
6187 /* XXX: specification say this is treated as a load by the MMU
6188 * but does not generate any exception
6189 */
6190 }
6191
6192 /* Embedded.Processor Control */
6193
6194 static void gen_msgclr(DisasContext *ctx)
6195 {
6196 #if defined(CONFIG_USER_ONLY)
6197 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6198 #else
6199 if (unlikely(ctx->mem_idx == 0)) {
6200 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6201 return;
6202 }
6203
6204 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6205 #endif
6206 }
6207
6208 static void gen_msgsnd(DisasContext *ctx)
6209 {
6210 #if defined(CONFIG_USER_ONLY)
6211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6212 #else
6213 if (unlikely(ctx->mem_idx == 0)) {
6214 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6215 return;
6216 }
6217
6218 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6219 #endif
6220 }
6221
6222 /*** Altivec vector extension ***/
6223 /* Altivec registers moves */
6224
6225 static inline TCGv_ptr gen_avr_ptr(int reg)
6226 {
6227 TCGv_ptr r = tcg_temp_new_ptr();
6228 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6229 return r;
6230 }
6231
6232 #define GEN_VR_LDX(name, opc2, opc3) \
6233 static void glue(gen_, name)(DisasContext *ctx) \
6234 { \
6235 TCGv EA; \
6236 if (unlikely(!ctx->altivec_enabled)) { \
6237 gen_exception(ctx, POWERPC_EXCP_VPU); \
6238 return; \
6239 } \
6240 gen_set_access_type(ctx, ACCESS_INT); \
6241 EA = tcg_temp_new(); \
6242 gen_addr_reg_index(ctx, EA); \
6243 tcg_gen_andi_tl(EA, EA, ~0xf); \
6244 if (ctx->le_mode) { \
6245 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6246 tcg_gen_addi_tl(EA, EA, 8); \
6247 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6248 } else { \
6249 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6250 tcg_gen_addi_tl(EA, EA, 8); \
6251 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6252 } \
6253 tcg_temp_free(EA); \
6254 }
6255
6256 #define GEN_VR_STX(name, opc2, opc3) \
6257 static void gen_st##name(DisasContext *ctx) \
6258 { \
6259 TCGv EA; \
6260 if (unlikely(!ctx->altivec_enabled)) { \
6261 gen_exception(ctx, POWERPC_EXCP_VPU); \
6262 return; \
6263 } \
6264 gen_set_access_type(ctx, ACCESS_INT); \
6265 EA = tcg_temp_new(); \
6266 gen_addr_reg_index(ctx, EA); \
6267 tcg_gen_andi_tl(EA, EA, ~0xf); \
6268 if (ctx->le_mode) { \
6269 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6270 tcg_gen_addi_tl(EA, EA, 8); \
6271 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6272 } else { \
6273 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6274 tcg_gen_addi_tl(EA, EA, 8); \
6275 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6276 } \
6277 tcg_temp_free(EA); \
6278 }
6279
6280 #define GEN_VR_LVE(name, opc2, opc3) \
6281 static void gen_lve##name(DisasContext *ctx) \
6282 { \
6283 TCGv EA; \
6284 TCGv_ptr rs; \
6285 if (unlikely(!ctx->altivec_enabled)) { \
6286 gen_exception(ctx, POWERPC_EXCP_VPU); \
6287 return; \
6288 } \
6289 gen_set_access_type(ctx, ACCESS_INT); \
6290 EA = tcg_temp_new(); \
6291 gen_addr_reg_index(ctx, EA); \
6292 rs = gen_avr_ptr(rS(ctx->opcode)); \
6293 gen_helper_lve##name(cpu_env, rs, EA); \
6294 tcg_temp_free(EA); \
6295 tcg_temp_free_ptr(rs); \
6296 }
6297
6298 #define GEN_VR_STVE(name, opc2, opc3) \
6299 static void gen_stve##name(DisasContext *ctx) \
6300 { \
6301 TCGv EA; \
6302 TCGv_ptr rs; \
6303 if (unlikely(!ctx->altivec_enabled)) { \
6304 gen_exception(ctx, POWERPC_EXCP_VPU); \
6305 return; \
6306 } \
6307 gen_set_access_type(ctx, ACCESS_INT); \
6308 EA = tcg_temp_new(); \
6309 gen_addr_reg_index(ctx, EA); \
6310 rs = gen_avr_ptr(rS(ctx->opcode)); \
6311 gen_helper_stve##name(cpu_env, rs, EA); \
6312 tcg_temp_free(EA); \
6313 tcg_temp_free_ptr(rs); \
6314 }
6315
6316 GEN_VR_LDX(lvx, 0x07, 0x03);
6317 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6318 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6319
6320 GEN_VR_LVE(bx, 0x07, 0x00);
6321 GEN_VR_LVE(hx, 0x07, 0x01);
6322 GEN_VR_LVE(wx, 0x07, 0x02);
6323
6324 GEN_VR_STX(svx, 0x07, 0x07);
6325 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6326 GEN_VR_STX(svxl, 0x07, 0x0F);
6327
6328 GEN_VR_STVE(bx, 0x07, 0x04);
6329 GEN_VR_STVE(hx, 0x07, 0x05);
6330 GEN_VR_STVE(wx, 0x07, 0x06);
6331
6332 static void gen_lvsl(DisasContext *ctx)
6333 {
6334 TCGv_ptr rd;
6335 TCGv EA;
6336 if (unlikely(!ctx->altivec_enabled)) {
6337 gen_exception(ctx, POWERPC_EXCP_VPU);
6338 return;
6339 }
6340 EA = tcg_temp_new();
6341 gen_addr_reg_index(ctx, EA);
6342 rd = gen_avr_ptr(rD(ctx->opcode));
6343 gen_helper_lvsl(rd, EA);
6344 tcg_temp_free(EA);
6345 tcg_temp_free_ptr(rd);
6346 }
6347
6348 static void gen_lvsr(DisasContext *ctx)
6349 {
6350 TCGv_ptr rd;
6351 TCGv EA;
6352 if (unlikely(!ctx->altivec_enabled)) {
6353 gen_exception(ctx, POWERPC_EXCP_VPU);
6354 return;
6355 }
6356 EA = tcg_temp_new();
6357 gen_addr_reg_index(ctx, EA);
6358 rd = gen_avr_ptr(rD(ctx->opcode));
6359 gen_helper_lvsr(rd, EA);
6360 tcg_temp_free(EA);
6361 tcg_temp_free_ptr(rd);
6362 }
6363
6364 static void gen_mfvscr(DisasContext *ctx)
6365 {
6366 TCGv_i32 t;
6367 if (unlikely(!ctx->altivec_enabled)) {
6368 gen_exception(ctx, POWERPC_EXCP_VPU);
6369 return;
6370 }
6371 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6372 t = tcg_temp_new_i32();
6373 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6374 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6375 tcg_temp_free_i32(t);
6376 }
6377
6378 static void gen_mtvscr(DisasContext *ctx)
6379 {
6380 TCGv_ptr p;
6381 if (unlikely(!ctx->altivec_enabled)) {
6382 gen_exception(ctx, POWERPC_EXCP_VPU);
6383 return;
6384 }
6385 p = gen_avr_ptr(rD(ctx->opcode));
6386 gen_helper_mtvscr(cpu_env, p);
6387 tcg_temp_free_ptr(p);
6388 }
6389
6390 /* Logical operations */
6391 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6392 static void glue(gen_, name)(DisasContext *ctx) \
6393 { \
6394 if (unlikely(!ctx->altivec_enabled)) { \
6395 gen_exception(ctx, POWERPC_EXCP_VPU); \
6396 return; \
6397 } \
6398 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6399 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6400 }
6401
6402 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6403 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6404 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6405 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6406 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6407
6408 #define GEN_VXFORM(name, opc2, opc3) \
6409 static void glue(gen_, name)(DisasContext *ctx) \
6410 { \
6411 TCGv_ptr ra, rb, rd; \
6412 if (unlikely(!ctx->altivec_enabled)) { \
6413 gen_exception(ctx, POWERPC_EXCP_VPU); \
6414 return; \
6415 } \
6416 ra = gen_avr_ptr(rA(ctx->opcode)); \
6417 rb = gen_avr_ptr(rB(ctx->opcode)); \
6418 rd = gen_avr_ptr(rD(ctx->opcode)); \
6419 gen_helper_##name (rd, ra, rb); \
6420 tcg_temp_free_ptr(ra); \
6421 tcg_temp_free_ptr(rb); \
6422 tcg_temp_free_ptr(rd); \
6423 }
6424
6425 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6426 static void glue(gen_, name)(DisasContext *ctx) \
6427 { \
6428 TCGv_ptr ra, rb, rd; \
6429 if (unlikely(!ctx->altivec_enabled)) { \
6430 gen_exception(ctx, POWERPC_EXCP_VPU); \
6431 return; \
6432 } \
6433 ra = gen_avr_ptr(rA(ctx->opcode)); \
6434 rb = gen_avr_ptr(rB(ctx->opcode)); \
6435 rd = gen_avr_ptr(rD(ctx->opcode)); \
6436 gen_helper_##name(cpu_env, rd, ra, rb); \
6437 tcg_temp_free_ptr(ra); \
6438 tcg_temp_free_ptr(rb); \
6439 tcg_temp_free_ptr(rd); \
6440 }
6441
6442 GEN_VXFORM(vaddubm, 0, 0);
6443 GEN_VXFORM(vadduhm, 0, 1);
6444 GEN_VXFORM(vadduwm, 0, 2);
6445 GEN_VXFORM(vsububm, 0, 16);
6446 GEN_VXFORM(vsubuhm, 0, 17);
6447 GEN_VXFORM(vsubuwm, 0, 18);
6448 GEN_VXFORM(vmaxub, 1, 0);
6449 GEN_VXFORM(vmaxuh, 1, 1);
6450 GEN_VXFORM(vmaxuw, 1, 2);
6451 GEN_VXFORM(vmaxsb, 1, 4);
6452 GEN_VXFORM(vmaxsh, 1, 5);
6453 GEN_VXFORM(vmaxsw, 1, 6);
6454 GEN_VXFORM(vminub, 1, 8);
6455 GEN_VXFORM(vminuh, 1, 9);
6456 GEN_VXFORM(vminuw, 1, 10);
6457 GEN_VXFORM(vminsb, 1, 12);
6458 GEN_VXFORM(vminsh, 1, 13);
6459 GEN_VXFORM(vminsw, 1, 14);
6460 GEN_VXFORM(vavgub, 1, 16);
6461 GEN_VXFORM(vavguh, 1, 17);
6462 GEN_VXFORM(vavguw, 1, 18);
6463 GEN_VXFORM(vavgsb, 1, 20);
6464 GEN_VXFORM(vavgsh, 1, 21);
6465 GEN_VXFORM(vavgsw, 1, 22);
6466 GEN_VXFORM(vmrghb, 6, 0);
6467 GEN_VXFORM(vmrghh, 6, 1);
6468 GEN_VXFORM(vmrghw, 6, 2);
6469 GEN_VXFORM(vmrglb, 6, 4);
6470 GEN_VXFORM(vmrglh, 6, 5);
6471 GEN_VXFORM(vmrglw, 6, 6);
6472 GEN_VXFORM(vmuloub, 4, 0);
6473 GEN_VXFORM(vmulouh, 4, 1);
6474 GEN_VXFORM(vmulosb, 4, 4);
6475 GEN_VXFORM(vmulosh, 4, 5);
6476 GEN_VXFORM(vmuleub, 4, 8);
6477 GEN_VXFORM(vmuleuh, 4, 9);
6478 GEN_VXFORM(vmulesb, 4, 12);
6479 GEN_VXFORM(vmulesh, 4, 13);
6480 GEN_VXFORM(vslb, 2, 4);
6481 GEN_VXFORM(vslh, 2, 5);
6482 GEN_VXFORM(vslw, 2, 6);
6483 GEN_VXFORM(vsrb, 2, 8);
6484 GEN_VXFORM(vsrh, 2, 9);
6485 GEN_VXFORM(vsrw, 2, 10);
6486 GEN_VXFORM(vsrab, 2, 12);
6487 GEN_VXFORM(vsrah, 2, 13);
6488 GEN_VXFORM(vsraw, 2, 14);
6489 GEN_VXFORM(vslo, 6, 16);
6490 GEN_VXFORM(vsro, 6, 17);
6491 GEN_VXFORM(vaddcuw, 0, 6);
6492 GEN_VXFORM(vsubcuw, 0, 22);
6493 GEN_VXFORM_ENV(vaddubs, 0, 8);
6494 GEN_VXFORM_ENV(vadduhs, 0, 9);
6495 GEN_VXFORM_ENV(vadduws, 0, 10);
6496 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6497 GEN_VXFORM_ENV(vaddshs, 0, 13);
6498 GEN_VXFORM_ENV(vaddsws, 0, 14);
6499 GEN_VXFORM_ENV(vsububs, 0, 24);
6500 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6501 GEN_VXFORM_ENV(vsubuws, 0, 26);
6502 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6503 GEN_VXFORM_ENV(vsubshs, 0, 29);
6504 GEN_VXFORM_ENV(vsubsws, 0, 30);
6505 GEN_VXFORM(vrlb, 2, 0);
6506 GEN_VXFORM(vrlh, 2, 1);
6507 GEN_VXFORM(vrlw, 2, 2);
6508 GEN_VXFORM(vsl, 2, 7);
6509 GEN_VXFORM(vsr, 2, 11);
6510 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6511 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6512 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6513 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6514 GEN_VXFORM_ENV(vpkshus, 7, 4);
6515 GEN_VXFORM_ENV(vpkswus, 7, 5);
6516 GEN_VXFORM_ENV(vpkshss, 7, 6);
6517 GEN_VXFORM_ENV(vpkswss, 7, 7);
6518 GEN_VXFORM(vpkpx, 7, 12);
6519 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6520 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6521 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6522 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6523 GEN_VXFORM_ENV(vsumsws, 4, 30);
6524 GEN_VXFORM_ENV(vaddfp, 5, 0);
6525 GEN_VXFORM_ENV(vsubfp, 5, 1);
6526 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6527 GEN_VXFORM_ENV(vminfp, 5, 17);
6528
6529 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6530 static void glue(gen_, name)(DisasContext *ctx) \
6531 { \
6532 TCGv_ptr ra, rb, rd; \
6533 if (unlikely(!ctx->altivec_enabled)) { \
6534 gen_exception(ctx, POWERPC_EXCP_VPU); \
6535 return; \
6536 } \
6537 ra = gen_avr_ptr(rA(ctx->opcode)); \
6538 rb = gen_avr_ptr(rB(ctx->opcode)); \
6539 rd = gen_avr_ptr(rD(ctx->opcode)); \
6540 gen_helper_##opname(cpu_env, rd, ra, rb); \
6541 tcg_temp_free_ptr(ra); \
6542 tcg_temp_free_ptr(rb); \
6543 tcg_temp_free_ptr(rd); \
6544 }
6545
6546 #define GEN_VXRFORM(name, opc2, opc3) \
6547 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6548 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6549
6550 GEN_VXRFORM(vcmpequb, 3, 0)
6551 GEN_VXRFORM(vcmpequh, 3, 1)
6552 GEN_VXRFORM(vcmpequw, 3, 2)
6553 GEN_VXRFORM(vcmpgtsb, 3, 12)
6554 GEN_VXRFORM(vcmpgtsh, 3, 13)
6555 GEN_VXRFORM(vcmpgtsw, 3, 14)
6556 GEN_VXRFORM(vcmpgtub, 3, 8)
6557 GEN_VXRFORM(vcmpgtuh, 3, 9)
6558 GEN_VXRFORM(vcmpgtuw, 3, 10)
6559 GEN_VXRFORM(vcmpeqfp, 3, 3)
6560 GEN_VXRFORM(vcmpgefp, 3, 7)
6561 GEN_VXRFORM(vcmpgtfp, 3, 11)
6562 GEN_VXRFORM(vcmpbfp, 3, 15)
6563
6564 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6565 static void glue(gen_, name)(DisasContext *ctx) \
6566 { \
6567 TCGv_ptr rd; \
6568 TCGv_i32 simm; \
6569 if (unlikely(!ctx->altivec_enabled)) { \
6570 gen_exception(ctx, POWERPC_EXCP_VPU); \
6571 return; \
6572 } \
6573 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6574 rd = gen_avr_ptr(rD(ctx->opcode)); \
6575 gen_helper_##name (rd, simm); \
6576 tcg_temp_free_i32(simm); \
6577 tcg_temp_free_ptr(rd); \
6578 }
6579
6580 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6581 GEN_VXFORM_SIMM(vspltish, 6, 13);
6582 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6583
6584 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6585 static void glue(gen_, name)(DisasContext *ctx) \
6586 { \
6587 TCGv_ptr rb, rd; \
6588 if (unlikely(!ctx->altivec_enabled)) { \
6589 gen_exception(ctx, POWERPC_EXCP_VPU); \
6590 return; \
6591 } \
6592 rb = gen_avr_ptr(rB(ctx->opcode)); \
6593 rd = gen_avr_ptr(rD(ctx->opcode)); \
6594 gen_helper_##name (rd, rb); \
6595 tcg_temp_free_ptr(rb); \
6596 tcg_temp_free_ptr(rd); \
6597 }
6598
6599 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6600 static void glue(gen_, name)(DisasContext *ctx) \
6601 { \
6602 TCGv_ptr rb, rd; \
6603 \
6604 if (unlikely(!ctx->altivec_enabled)) { \
6605 gen_exception(ctx, POWERPC_EXCP_VPU); \
6606 return; \
6607 } \
6608 rb = gen_avr_ptr(rB(ctx->opcode)); \
6609 rd = gen_avr_ptr(rD(ctx->opcode)); \
6610 gen_helper_##name(cpu_env, rd, rb); \
6611 tcg_temp_free_ptr(rb); \
6612 tcg_temp_free_ptr(rd); \
6613 }
6614
6615 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6616 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6617 GEN_VXFORM_NOA(vupklsb, 7, 10);
6618 GEN_VXFORM_NOA(vupklsh, 7, 11);
6619 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6620 GEN_VXFORM_NOA(vupklpx, 7, 15);
6621 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6622 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6623 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6624 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6625 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6626 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6627 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6628 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6629
6630 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6631 static void glue(gen_, name)(DisasContext *ctx) \
6632 { \
6633 TCGv_ptr rd; \
6634 TCGv_i32 simm; \
6635 if (unlikely(!ctx->altivec_enabled)) { \
6636 gen_exception(ctx, POWERPC_EXCP_VPU); \
6637 return; \
6638 } \
6639 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6640 rd = gen_avr_ptr(rD(ctx->opcode)); \
6641 gen_helper_##name (rd, simm); \
6642 tcg_temp_free_i32(simm); \
6643 tcg_temp_free_ptr(rd); \
6644 }
6645
6646 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
6647 static void glue(gen_, name)(DisasContext *ctx) \
6648 { \
6649 TCGv_ptr rb, rd; \
6650 TCGv_i32 uimm; \
6651 if (unlikely(!ctx->altivec_enabled)) { \
6652 gen_exception(ctx, POWERPC_EXCP_VPU); \
6653 return; \
6654 } \
6655 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6656 rb = gen_avr_ptr(rB(ctx->opcode)); \
6657 rd = gen_avr_ptr(rD(ctx->opcode)); \
6658 gen_helper_##name (rd, rb, uimm); \
6659 tcg_temp_free_i32(uimm); \
6660 tcg_temp_free_ptr(rb); \
6661 tcg_temp_free_ptr(rd); \
6662 }
6663
6664 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
6665 static void glue(gen_, name)(DisasContext *ctx) \
6666 { \
6667 TCGv_ptr rb, rd; \
6668 TCGv_i32 uimm; \
6669 \
6670 if (unlikely(!ctx->altivec_enabled)) { \
6671 gen_exception(ctx, POWERPC_EXCP_VPU); \
6672 return; \
6673 } \
6674 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
6675 rb = gen_avr_ptr(rB(ctx->opcode)); \
6676 rd = gen_avr_ptr(rD(ctx->opcode)); \
6677 gen_helper_##name(cpu_env, rd, rb, uimm); \
6678 tcg_temp_free_i32(uimm); \
6679 tcg_temp_free_ptr(rb); \
6680 tcg_temp_free_ptr(rd); \
6681 }
6682
6683 GEN_VXFORM_UIMM(vspltb, 6, 8);
6684 GEN_VXFORM_UIMM(vsplth, 6, 9);
6685 GEN_VXFORM_UIMM(vspltw, 6, 10);
6686 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
6687 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
6688 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
6689 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
6690
6691 static void gen_vsldoi(DisasContext *ctx)
6692 {
6693 TCGv_ptr ra, rb, rd;
6694 TCGv_i32 sh;
6695 if (unlikely(!ctx->altivec_enabled)) {
6696 gen_exception(ctx, POWERPC_EXCP_VPU);
6697 return;
6698 }
6699 ra = gen_avr_ptr(rA(ctx->opcode));
6700 rb = gen_avr_ptr(rB(ctx->opcode));
6701 rd = gen_avr_ptr(rD(ctx->opcode));
6702 sh = tcg_const_i32(VSH(ctx->opcode));
6703 gen_helper_vsldoi (rd, ra, rb, sh);
6704 tcg_temp_free_ptr(ra);
6705 tcg_temp_free_ptr(rb);
6706 tcg_temp_free_ptr(rd);
6707 tcg_temp_free_i32(sh);
6708 }
6709
6710 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
6711 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6712 { \
6713 TCGv_ptr ra, rb, rc, rd; \
6714 if (unlikely(!ctx->altivec_enabled)) { \
6715 gen_exception(ctx, POWERPC_EXCP_VPU); \
6716 return; \
6717 } \
6718 ra = gen_avr_ptr(rA(ctx->opcode)); \
6719 rb = gen_avr_ptr(rB(ctx->opcode)); \
6720 rc = gen_avr_ptr(rC(ctx->opcode)); \
6721 rd = gen_avr_ptr(rD(ctx->opcode)); \
6722 if (Rc(ctx->opcode)) { \
6723 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
6724 } else { \
6725 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
6726 } \
6727 tcg_temp_free_ptr(ra); \
6728 tcg_temp_free_ptr(rb); \
6729 tcg_temp_free_ptr(rc); \
6730 tcg_temp_free_ptr(rd); \
6731 }
6732
6733 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
6734
6735 static void gen_vmladduhm(DisasContext *ctx)
6736 {
6737 TCGv_ptr ra, rb, rc, rd;
6738 if (unlikely(!ctx->altivec_enabled)) {
6739 gen_exception(ctx, POWERPC_EXCP_VPU);
6740 return;
6741 }
6742 ra = gen_avr_ptr(rA(ctx->opcode));
6743 rb = gen_avr_ptr(rB(ctx->opcode));
6744 rc = gen_avr_ptr(rC(ctx->opcode));
6745 rd = gen_avr_ptr(rD(ctx->opcode));
6746 gen_helper_vmladduhm(rd, ra, rb, rc);
6747 tcg_temp_free_ptr(ra);
6748 tcg_temp_free_ptr(rb);
6749 tcg_temp_free_ptr(rc);
6750 tcg_temp_free_ptr(rd);
6751 }
6752
6753 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
6754 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
6755 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
6756 GEN_VAFORM_PAIRED(vsel, vperm, 21)
6757 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
6758
6759 /*** SPE extension ***/
6760 /* Register moves */
6761
6762
6763 static inline void gen_evmra(DisasContext *ctx)
6764 {
6765
6766 if (unlikely(!ctx->spe_enabled)) {
6767 gen_exception(ctx, POWERPC_EXCP_SPEU);
6768 return;
6769 }
6770
6771 #if defined(TARGET_PPC64)
6772 /* rD := rA */
6773 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6774
6775 /* spe_acc := rA */
6776 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
6777 cpu_env,
6778 offsetof(CPUPPCState, spe_acc));
6779 #else
6780 TCGv_i64 tmp = tcg_temp_new_i64();
6781
6782 /* tmp := rA_lo + rA_hi << 32 */
6783 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6784
6785 /* spe_acc := tmp */
6786 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
6787 tcg_temp_free_i64(tmp);
6788
6789 /* rD := rA */
6790 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
6791 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
6792 #endif
6793 }
6794
6795 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
6796 {
6797 #if defined(TARGET_PPC64)
6798 tcg_gen_mov_i64(t, cpu_gpr[reg]);
6799 #else
6800 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
6801 #endif
6802 }
6803
6804 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
6805 {
6806 #if defined(TARGET_PPC64)
6807 tcg_gen_mov_i64(cpu_gpr[reg], t);
6808 #else
6809 TCGv_i64 tmp = tcg_temp_new_i64();
6810 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
6811 tcg_gen_shri_i64(tmp, t, 32);
6812 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
6813 tcg_temp_free_i64(tmp);
6814 #endif
6815 }
6816
6817 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
6818 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
6819 { \
6820 if (Rc(ctx->opcode)) \
6821 gen_##name1(ctx); \
6822 else \
6823 gen_##name0(ctx); \
6824 }
6825
6826 /* Handler for undefined SPE opcodes */
6827 static inline void gen_speundef(DisasContext *ctx)
6828 {
6829 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6830 }
6831
6832 /* SPE logic */
6833 #if defined(TARGET_PPC64)
6834 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6835 static inline void gen_##name(DisasContext *ctx) \
6836 { \
6837 if (unlikely(!ctx->spe_enabled)) { \
6838 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6839 return; \
6840 } \
6841 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6842 cpu_gpr[rB(ctx->opcode)]); \
6843 }
6844 #else
6845 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
6846 static inline void gen_##name(DisasContext *ctx) \
6847 { \
6848 if (unlikely(!ctx->spe_enabled)) { \
6849 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6850 return; \
6851 } \
6852 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6853 cpu_gpr[rB(ctx->opcode)]); \
6854 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6855 cpu_gprh[rB(ctx->opcode)]); \
6856 }
6857 #endif
6858
6859 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
6860 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
6861 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
6862 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
6863 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
6864 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
6865 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
6866 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
6867
6868 /* SPE logic immediate */
6869 #if defined(TARGET_PPC64)
6870 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6871 static inline void gen_##name(DisasContext *ctx) \
6872 { \
6873 if (unlikely(!ctx->spe_enabled)) { \
6874 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6875 return; \
6876 } \
6877 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6878 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6879 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6880 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6881 tcg_opi(t0, t0, rB(ctx->opcode)); \
6882 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6883 tcg_gen_trunc_i64_i32(t1, t2); \
6884 tcg_temp_free_i64(t2); \
6885 tcg_opi(t1, t1, rB(ctx->opcode)); \
6886 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6887 tcg_temp_free_i32(t0); \
6888 tcg_temp_free_i32(t1); \
6889 }
6890 #else
6891 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
6892 static inline void gen_##name(DisasContext *ctx) \
6893 { \
6894 if (unlikely(!ctx->spe_enabled)) { \
6895 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6896 return; \
6897 } \
6898 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
6899 rB(ctx->opcode)); \
6900 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
6901 rB(ctx->opcode)); \
6902 }
6903 #endif
6904 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
6905 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
6906 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
6907 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
6908
6909 /* SPE arithmetic */
6910 #if defined(TARGET_PPC64)
6911 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6912 static inline void gen_##name(DisasContext *ctx) \
6913 { \
6914 if (unlikely(!ctx->spe_enabled)) { \
6915 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6916 return; \
6917 } \
6918 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6919 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6920 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
6921 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6922 tcg_op(t0, t0); \
6923 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
6924 tcg_gen_trunc_i64_i32(t1, t2); \
6925 tcg_temp_free_i64(t2); \
6926 tcg_op(t1, t1); \
6927 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6928 tcg_temp_free_i32(t0); \
6929 tcg_temp_free_i32(t1); \
6930 }
6931 #else
6932 #define GEN_SPEOP_ARITH1(name, tcg_op) \
6933 static inline void gen_##name(DisasContext *ctx) \
6934 { \
6935 if (unlikely(!ctx->spe_enabled)) { \
6936 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6937 return; \
6938 } \
6939 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
6940 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
6941 }
6942 #endif
6943
6944 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
6945 {
6946 int l1 = gen_new_label();
6947 int l2 = gen_new_label();
6948
6949 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
6950 tcg_gen_neg_i32(ret, arg1);
6951 tcg_gen_br(l2);
6952 gen_set_label(l1);
6953 tcg_gen_mov_i32(ret, arg1);
6954 gen_set_label(l2);
6955 }
6956 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
6957 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
6958 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
6959 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
6960 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
6961 {
6962 tcg_gen_addi_i32(ret, arg1, 0x8000);
6963 tcg_gen_ext16u_i32(ret, ret);
6964 }
6965 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
6966 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
6967 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
6968
6969 #if defined(TARGET_PPC64)
6970 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6971 static inline void gen_##name(DisasContext *ctx) \
6972 { \
6973 if (unlikely(!ctx->spe_enabled)) { \
6974 gen_exception(ctx, POWERPC_EXCP_SPEU); \
6975 return; \
6976 } \
6977 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
6978 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
6979 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
6980 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
6981 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
6982 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
6983 tcg_op(t0, t0, t2); \
6984 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
6985 tcg_gen_trunc_i64_i32(t1, t3); \
6986 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
6987 tcg_gen_trunc_i64_i32(t2, t3); \
6988 tcg_temp_free_i64(t3); \
6989 tcg_op(t1, t1, t2); \
6990 tcg_temp_free_i32(t2); \
6991 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
6992 tcg_temp_free_i32(t0); \
6993 tcg_temp_free_i32(t1); \
6994 }
6995 #else
6996 #define GEN_SPEOP_ARITH2(name, tcg_op) \
6997 static inline void gen_##name(DisasContext *ctx) \
6998 { \
6999 if (unlikely(!ctx->spe_enabled)) { \
7000 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7001 return; \
7002 } \
7003 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7004 cpu_gpr[rB(ctx->opcode)]); \
7005 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7006 cpu_gprh[rB(ctx->opcode)]); \
7007 }
7008 #endif
7009
7010 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7011 {
7012 TCGv_i32 t0;
7013 int l1, l2;
7014
7015 l1 = gen_new_label();
7016 l2 = gen_new_label();
7017 t0 = tcg_temp_local_new_i32();
7018 /* No error here: 6 bits are used */
7019 tcg_gen_andi_i32(t0, arg2, 0x3F);
7020 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7021 tcg_gen_shr_i32(ret, arg1, t0);
7022 tcg_gen_br(l2);
7023 gen_set_label(l1);
7024 tcg_gen_movi_i32(ret, 0);
7025 gen_set_label(l2);
7026 tcg_temp_free_i32(t0);
7027 }
7028 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
7029 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7030 {
7031 TCGv_i32 t0;
7032 int l1, l2;
7033
7034 l1 = gen_new_label();
7035 l2 = gen_new_label();
7036 t0 = tcg_temp_local_new_i32();
7037 /* No error here: 6 bits are used */
7038 tcg_gen_andi_i32(t0, arg2, 0x3F);
7039 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7040 tcg_gen_sar_i32(ret, arg1, t0);
7041 tcg_gen_br(l2);
7042 gen_set_label(l1);
7043 tcg_gen_movi_i32(ret, 0);
7044 gen_set_label(l2);
7045 tcg_temp_free_i32(t0);
7046 }
7047 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
7048 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7049 {
7050 TCGv_i32 t0;
7051 int l1, l2;
7052
7053 l1 = gen_new_label();
7054 l2 = gen_new_label();
7055 t0 = tcg_temp_local_new_i32();
7056 /* No error here: 6 bits are used */
7057 tcg_gen_andi_i32(t0, arg2, 0x3F);
7058 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
7059 tcg_gen_shl_i32(ret, arg1, t0);
7060 tcg_gen_br(l2);
7061 gen_set_label(l1);
7062 tcg_gen_movi_i32(ret, 0);
7063 gen_set_label(l2);
7064 tcg_temp_free_i32(t0);
7065 }
7066 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
7067 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7068 {
7069 TCGv_i32 t0 = tcg_temp_new_i32();
7070 tcg_gen_andi_i32(t0, arg2, 0x1F);
7071 tcg_gen_rotl_i32(ret, arg1, t0);
7072 tcg_temp_free_i32(t0);
7073 }
7074 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
7075 static inline void gen_evmergehi(DisasContext *ctx)
7076 {
7077 if (unlikely(!ctx->spe_enabled)) {
7078 gen_exception(ctx, POWERPC_EXCP_SPEU);
7079 return;
7080 }
7081 #if defined(TARGET_PPC64)
7082 TCGv t0 = tcg_temp_new();
7083 TCGv t1 = tcg_temp_new();
7084 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7085 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7086 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7087 tcg_temp_free(t0);
7088 tcg_temp_free(t1);
7089 #else
7090 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7091 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7092 #endif
7093 }
7094 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
7095 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
7096 {
7097 tcg_gen_sub_i32(ret, arg2, arg1);
7098 }
7099 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
7100
7101 /* SPE arithmetic immediate */
7102 #if defined(TARGET_PPC64)
7103 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7104 static inline void gen_##name(DisasContext *ctx) \
7105 { \
7106 if (unlikely(!ctx->spe_enabled)) { \
7107 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7108 return; \
7109 } \
7110 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7111 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7112 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7113 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
7114 tcg_op(t0, t0, rA(ctx->opcode)); \
7115 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7116 tcg_gen_trunc_i64_i32(t1, t2); \
7117 tcg_temp_free_i64(t2); \
7118 tcg_op(t1, t1, rA(ctx->opcode)); \
7119 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7120 tcg_temp_free_i32(t0); \
7121 tcg_temp_free_i32(t1); \
7122 }
7123 #else
7124 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
7125 static inline void gen_##name(DisasContext *ctx) \
7126 { \
7127 if (unlikely(!ctx->spe_enabled)) { \
7128 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7129 return; \
7130 } \
7131 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
7132 rA(ctx->opcode)); \
7133 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
7134 rA(ctx->opcode)); \
7135 }
7136 #endif
7137 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
7138 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
7139
7140 /* SPE comparison */
7141 #if defined(TARGET_PPC64)
7142 #define GEN_SPEOP_COMP(name, tcg_cond) \
7143 static inline void gen_##name(DisasContext *ctx) \
7144 { \
7145 if (unlikely(!ctx->spe_enabled)) { \
7146 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7147 return; \
7148 } \
7149 int l1 = gen_new_label(); \
7150 int l2 = gen_new_label(); \
7151 int l3 = gen_new_label(); \
7152 int l4 = gen_new_label(); \
7153 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7154 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7155 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7156 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7157 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
7158 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
7159 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
7160 tcg_gen_br(l2); \
7161 gen_set_label(l1); \
7162 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7163 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7164 gen_set_label(l2); \
7165 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7166 tcg_gen_trunc_i64_i32(t0, t2); \
7167 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
7168 tcg_gen_trunc_i64_i32(t1, t2); \
7169 tcg_temp_free_i64(t2); \
7170 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
7171 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7172 ~(CRF_CH | CRF_CH_AND_CL)); \
7173 tcg_gen_br(l4); \
7174 gen_set_label(l3); \
7175 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7176 CRF_CH | CRF_CH_OR_CL); \
7177 gen_set_label(l4); \
7178 tcg_temp_free_i32(t0); \
7179 tcg_temp_free_i32(t1); \
7180 }
7181 #else
7182 #define GEN_SPEOP_COMP(name, tcg_cond) \
7183 static inline void gen_##name(DisasContext *ctx) \
7184 { \
7185 if (unlikely(!ctx->spe_enabled)) { \
7186 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7187 return; \
7188 } \
7189 int l1 = gen_new_label(); \
7190 int l2 = gen_new_label(); \
7191 int l3 = gen_new_label(); \
7192 int l4 = gen_new_label(); \
7193 \
7194 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
7195 cpu_gpr[rB(ctx->opcode)], l1); \
7196 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
7197 tcg_gen_br(l2); \
7198 gen_set_label(l1); \
7199 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
7200 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
7201 gen_set_label(l2); \
7202 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
7203 cpu_gprh[rB(ctx->opcode)], l3); \
7204 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7205 ~(CRF_CH | CRF_CH_AND_CL)); \
7206 tcg_gen_br(l4); \
7207 gen_set_label(l3); \
7208 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
7209 CRF_CH | CRF_CH_OR_CL); \
7210 gen_set_label(l4); \
7211 }
7212 #endif
7213 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
7214 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
7215 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
7216 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
7217 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
7218
7219 /* SPE misc */
7220 static inline void gen_brinc(DisasContext *ctx)
7221 {
7222 /* Note: brinc is usable even if SPE is disabled */
7223 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
7224 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7225 }
7226 static inline void gen_evmergelo(DisasContext *ctx)
7227 {
7228 if (unlikely(!ctx->spe_enabled)) {
7229 gen_exception(ctx, POWERPC_EXCP_SPEU);
7230 return;
7231 }
7232 #if defined(TARGET_PPC64)
7233 TCGv t0 = tcg_temp_new();
7234 TCGv t1 = tcg_temp_new();
7235 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7236 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7237 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7238 tcg_temp_free(t0);
7239 tcg_temp_free(t1);
7240 #else
7241 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7242 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7243 #endif
7244 }
7245 static inline void gen_evmergehilo(DisasContext *ctx)
7246 {
7247 if (unlikely(!ctx->spe_enabled)) {
7248 gen_exception(ctx, POWERPC_EXCP_SPEU);
7249 return;
7250 }
7251 #if defined(TARGET_PPC64)
7252 TCGv t0 = tcg_temp_new();
7253 TCGv t1 = tcg_temp_new();
7254 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
7255 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
7256 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7257 tcg_temp_free(t0);
7258 tcg_temp_free(t1);
7259 #else
7260 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7261 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7262 #endif
7263 }
7264 static inline void gen_evmergelohi(DisasContext *ctx)
7265 {
7266 if (unlikely(!ctx->spe_enabled)) {
7267 gen_exception(ctx, POWERPC_EXCP_SPEU);
7268 return;
7269 }
7270 #if defined(TARGET_PPC64)
7271 TCGv t0 = tcg_temp_new();
7272 TCGv t1 = tcg_temp_new();
7273 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
7274 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
7275 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
7276 tcg_temp_free(t0);
7277 tcg_temp_free(t1);
7278 #else
7279 if (rD(ctx->opcode) == rA(ctx->opcode)) {
7280 TCGv_i32 tmp = tcg_temp_new_i32();
7281 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
7282 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7283 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
7284 tcg_temp_free_i32(tmp);
7285 } else {
7286 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7287 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7288 }
7289 #endif
7290 }
7291 static inline void gen_evsplati(DisasContext *ctx)
7292 {
7293 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
7294
7295 #if defined(TARGET_PPC64)
7296 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7297 #else
7298 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7299 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7300 #endif
7301 }
7302 static inline void gen_evsplatfi(DisasContext *ctx)
7303 {
7304 uint64_t imm = rA(ctx->opcode) << 27;
7305
7306 #if defined(TARGET_PPC64)
7307 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
7308 #else
7309 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
7310 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
7311 #endif
7312 }
7313
7314 static inline void gen_evsel(DisasContext *ctx)
7315 {
7316 int l1 = gen_new_label();
7317 int l2 = gen_new_label();
7318 int l3 = gen_new_label();
7319 int l4 = gen_new_label();
7320 TCGv_i32 t0 = tcg_temp_local_new_i32();
7321 #if defined(TARGET_PPC64)
7322 TCGv t1 = tcg_temp_local_new();
7323 TCGv t2 = tcg_temp_local_new();
7324 #endif
7325 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
7326 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
7327 #if defined(TARGET_PPC64)
7328 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7329 #else
7330 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7331 #endif
7332 tcg_gen_br(l2);
7333 gen_set_label(l1);
7334 #if defined(TARGET_PPC64)
7335 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
7336 #else
7337 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
7338 #endif
7339 gen_set_label(l2);
7340 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
7341 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
7342 #if defined(TARGET_PPC64)
7343 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
7344 #else
7345 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7346 #endif
7347 tcg_gen_br(l4);
7348 gen_set_label(l3);
7349 #if defined(TARGET_PPC64)
7350 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
7351 #else
7352 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
7353 #endif
7354 gen_set_label(l4);
7355 tcg_temp_free_i32(t0);
7356 #if defined(TARGET_PPC64)
7357 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
7358 tcg_temp_free(t1);
7359 tcg_temp_free(t2);
7360 #endif
7361 }
7362
7363 static void gen_evsel0(DisasContext *ctx)
7364 {
7365 gen_evsel(ctx);
7366 }
7367
7368 static void gen_evsel1(DisasContext *ctx)
7369 {
7370 gen_evsel(ctx);
7371 }
7372
7373 static void gen_evsel2(DisasContext *ctx)
7374 {
7375 gen_evsel(ctx);
7376 }
7377
7378 static void gen_evsel3(DisasContext *ctx)
7379 {
7380 gen_evsel(ctx);
7381 }
7382
7383 /* Multiply */
7384
7385 static inline void gen_evmwumi(DisasContext *ctx)
7386 {
7387 TCGv_i64 t0, t1;
7388
7389 if (unlikely(!ctx->spe_enabled)) {
7390 gen_exception(ctx, POWERPC_EXCP_SPEU);
7391 return;
7392 }
7393
7394 t0 = tcg_temp_new_i64();
7395 t1 = tcg_temp_new_i64();
7396
7397 /* t0 := rA; t1 := rB */
7398 #if defined(TARGET_PPC64)
7399 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7400 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7401 #else
7402 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7403 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7404 #endif
7405
7406 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7407
7408 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7409
7410 tcg_temp_free_i64(t0);
7411 tcg_temp_free_i64(t1);
7412 }
7413
7414 static inline void gen_evmwumia(DisasContext *ctx)
7415 {
7416 TCGv_i64 tmp;
7417
7418 if (unlikely(!ctx->spe_enabled)) {
7419 gen_exception(ctx, POWERPC_EXCP_SPEU);
7420 return;
7421 }
7422
7423 gen_evmwumi(ctx); /* rD := rA * rB */
7424
7425 tmp = tcg_temp_new_i64();
7426
7427 /* acc := rD */
7428 gen_load_gpr64(tmp, rD(ctx->opcode));
7429 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7430 tcg_temp_free_i64(tmp);
7431 }
7432
7433 static inline void gen_evmwumiaa(DisasContext *ctx)
7434 {
7435 TCGv_i64 acc;
7436 TCGv_i64 tmp;
7437
7438 if (unlikely(!ctx->spe_enabled)) {
7439 gen_exception(ctx, POWERPC_EXCP_SPEU);
7440 return;
7441 }
7442
7443 gen_evmwumi(ctx); /* rD := rA * rB */
7444
7445 acc = tcg_temp_new_i64();
7446 tmp = tcg_temp_new_i64();
7447
7448 /* tmp := rD */
7449 gen_load_gpr64(tmp, rD(ctx->opcode));
7450
7451 /* Load acc */
7452 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7453
7454 /* acc := tmp + acc */
7455 tcg_gen_add_i64(acc, acc, tmp);
7456
7457 /* Store acc */
7458 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7459
7460 /* rD := acc */
7461 gen_store_gpr64(rD(ctx->opcode), acc);
7462
7463 tcg_temp_free_i64(acc);
7464 tcg_temp_free_i64(tmp);
7465 }
7466
7467 static inline void gen_evmwsmi(DisasContext *ctx)
7468 {
7469 TCGv_i64 t0, t1;
7470
7471 if (unlikely(!ctx->spe_enabled)) {
7472 gen_exception(ctx, POWERPC_EXCP_SPEU);
7473 return;
7474 }
7475
7476 t0 = tcg_temp_new_i64();
7477 t1 = tcg_temp_new_i64();
7478
7479 /* t0 := rA; t1 := rB */
7480 #if defined(TARGET_PPC64)
7481 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
7482 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
7483 #else
7484 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
7485 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
7486 #endif
7487
7488 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
7489
7490 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
7491
7492 tcg_temp_free_i64(t0);
7493 tcg_temp_free_i64(t1);
7494 }
7495
7496 static inline void gen_evmwsmia(DisasContext *ctx)
7497 {
7498 TCGv_i64 tmp;
7499
7500 gen_evmwsmi(ctx); /* rD := rA * rB */
7501
7502 tmp = tcg_temp_new_i64();
7503
7504 /* acc := rD */
7505 gen_load_gpr64(tmp, rD(ctx->opcode));
7506 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7507
7508 tcg_temp_free_i64(tmp);
7509 }
7510
7511 static inline void gen_evmwsmiaa(DisasContext *ctx)
7512 {
7513 TCGv_i64 acc = tcg_temp_new_i64();
7514 TCGv_i64 tmp = tcg_temp_new_i64();
7515
7516 gen_evmwsmi(ctx); /* rD := rA * rB */
7517
7518 acc = tcg_temp_new_i64();
7519 tmp = tcg_temp_new_i64();
7520
7521 /* tmp := rD */
7522 gen_load_gpr64(tmp, rD(ctx->opcode));
7523
7524 /* Load acc */
7525 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7526
7527 /* acc := tmp + acc */
7528 tcg_gen_add_i64(acc, acc, tmp);
7529
7530 /* Store acc */
7531 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
7532
7533 /* rD := acc */
7534 gen_store_gpr64(rD(ctx->opcode), acc);
7535
7536 tcg_temp_free_i64(acc);
7537 tcg_temp_free_i64(tmp);
7538 }
7539
7540 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7541 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7542 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7543 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7544 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7545 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7546 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
7547 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
7548 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
7549 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7550 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7551 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7552 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7553 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7554 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7555 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7556 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
7557 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7558 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7559 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
7560 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
7561 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7562 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
7563 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
7564 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7565 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
7566 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7567 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
7568 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
7569
7570 /* SPE load and stores */
7571 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
7572 {
7573 target_ulong uimm = rB(ctx->opcode);
7574
7575 if (rA(ctx->opcode) == 0) {
7576 tcg_gen_movi_tl(EA, uimm << sh);
7577 } else {
7578 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
7579 #if defined(TARGET_PPC64)
7580 if (!ctx->sf_mode) {
7581 tcg_gen_ext32u_tl(EA, EA);
7582 }
7583 #endif
7584 }
7585 }
7586
7587 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
7588 {
7589 #if defined(TARGET_PPC64)
7590 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7591 #else
7592 TCGv_i64 t0 = tcg_temp_new_i64();
7593 gen_qemu_ld64(ctx, t0, addr);
7594 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
7595 tcg_gen_shri_i64(t0, t0, 32);
7596 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
7597 tcg_temp_free_i64(t0);
7598 #endif
7599 }
7600
7601 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
7602 {
7603 #if defined(TARGET_PPC64)
7604 TCGv t0 = tcg_temp_new();
7605 gen_qemu_ld32u(ctx, t0, addr);
7606 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7607 gen_addr_add(ctx, addr, addr, 4);
7608 gen_qemu_ld32u(ctx, t0, addr);
7609 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7610 tcg_temp_free(t0);
7611 #else
7612 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7613 gen_addr_add(ctx, addr, addr, 4);
7614 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7615 #endif
7616 }
7617
7618 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
7619 {
7620 TCGv t0 = tcg_temp_new();
7621 #if defined(TARGET_PPC64)
7622 gen_qemu_ld16u(ctx, t0, addr);
7623 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7624 gen_addr_add(ctx, addr, addr, 2);
7625 gen_qemu_ld16u(ctx, t0, addr);
7626 tcg_gen_shli_tl(t0, t0, 32);
7627 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7628 gen_addr_add(ctx, addr, addr, 2);
7629 gen_qemu_ld16u(ctx, t0, addr);
7630 tcg_gen_shli_tl(t0, t0, 16);
7631 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7632 gen_addr_add(ctx, addr, addr, 2);
7633 gen_qemu_ld16u(ctx, t0, addr);
7634 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7635 #else
7636 gen_qemu_ld16u(ctx, t0, addr);
7637 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7638 gen_addr_add(ctx, addr, addr, 2);
7639 gen_qemu_ld16u(ctx, t0, addr);
7640 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7641 gen_addr_add(ctx, addr, addr, 2);
7642 gen_qemu_ld16u(ctx, t0, addr);
7643 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7644 gen_addr_add(ctx, addr, addr, 2);
7645 gen_qemu_ld16u(ctx, t0, addr);
7646 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7647 #endif
7648 tcg_temp_free(t0);
7649 }
7650
7651 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
7652 {
7653 TCGv t0 = tcg_temp_new();
7654 gen_qemu_ld16u(ctx, t0, addr);
7655 #if defined(TARGET_PPC64)
7656 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7657 tcg_gen_shli_tl(t0, t0, 16);
7658 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7659 #else
7660 tcg_gen_shli_tl(t0, t0, 16);
7661 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7662 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7663 #endif
7664 tcg_temp_free(t0);
7665 }
7666
7667 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
7668 {
7669 TCGv t0 = tcg_temp_new();
7670 gen_qemu_ld16u(ctx, t0, addr);
7671 #if defined(TARGET_PPC64)
7672 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7673 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7674 #else
7675 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7676 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7677 #endif
7678 tcg_temp_free(t0);
7679 }
7680
7681 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
7682 {
7683 TCGv t0 = tcg_temp_new();
7684 gen_qemu_ld16s(ctx, t0, addr);
7685 #if defined(TARGET_PPC64)
7686 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7687 tcg_gen_ext32u_tl(t0, t0);
7688 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7689 #else
7690 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7691 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7692 #endif
7693 tcg_temp_free(t0);
7694 }
7695
7696 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
7697 {
7698 TCGv t0 = tcg_temp_new();
7699 #if defined(TARGET_PPC64)
7700 gen_qemu_ld16u(ctx, t0, addr);
7701 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7702 gen_addr_add(ctx, addr, addr, 2);
7703 gen_qemu_ld16u(ctx, t0, addr);
7704 tcg_gen_shli_tl(t0, t0, 16);
7705 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7706 #else
7707 gen_qemu_ld16u(ctx, t0, addr);
7708 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7709 gen_addr_add(ctx, addr, addr, 2);
7710 gen_qemu_ld16u(ctx, t0, addr);
7711 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7712 #endif
7713 tcg_temp_free(t0);
7714 }
7715
7716 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
7717 {
7718 #if defined(TARGET_PPC64)
7719 TCGv t0 = tcg_temp_new();
7720 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7721 gen_addr_add(ctx, addr, addr, 2);
7722 gen_qemu_ld16u(ctx, t0, addr);
7723 tcg_gen_shli_tl(t0, t0, 32);
7724 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7725 tcg_temp_free(t0);
7726 #else
7727 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7728 gen_addr_add(ctx, addr, addr, 2);
7729 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7730 #endif
7731 }
7732
7733 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
7734 {
7735 #if defined(TARGET_PPC64)
7736 TCGv t0 = tcg_temp_new();
7737 gen_qemu_ld16s(ctx, t0, addr);
7738 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
7739 gen_addr_add(ctx, addr, addr, 2);
7740 gen_qemu_ld16s(ctx, t0, addr);
7741 tcg_gen_shli_tl(t0, t0, 32);
7742 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7743 tcg_temp_free(t0);
7744 #else
7745 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
7746 gen_addr_add(ctx, addr, addr, 2);
7747 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
7748 #endif
7749 }
7750
7751 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
7752 {
7753 TCGv t0 = tcg_temp_new();
7754 gen_qemu_ld32u(ctx, t0, addr);
7755 #if defined(TARGET_PPC64)
7756 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
7757 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7758 #else
7759 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
7760 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
7761 #endif
7762 tcg_temp_free(t0);
7763 }
7764
7765 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
7766 {
7767 TCGv t0 = tcg_temp_new();
7768 #if defined(TARGET_PPC64)
7769 gen_qemu_ld16u(ctx, t0, addr);
7770 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
7771 tcg_gen_shli_tl(t0, t0, 32);
7772 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7773 gen_addr_add(ctx, addr, addr, 2);
7774 gen_qemu_ld16u(ctx, t0, addr);
7775 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7776 tcg_gen_shli_tl(t0, t0, 16);
7777 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
7778 #else
7779 gen_qemu_ld16u(ctx, t0, addr);
7780 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
7781 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7782 gen_addr_add(ctx, addr, addr, 2);
7783 gen_qemu_ld16u(ctx, t0, addr);
7784 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
7785 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
7786 #endif
7787 tcg_temp_free(t0);
7788 }
7789
7790 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
7791 {
7792 #if defined(TARGET_PPC64)
7793 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7794 #else
7795 TCGv_i64 t0 = tcg_temp_new_i64();
7796 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
7797 gen_qemu_st64(ctx, t0, addr);
7798 tcg_temp_free_i64(t0);
7799 #endif
7800 }
7801
7802 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
7803 {
7804 #if defined(TARGET_PPC64)
7805 TCGv t0 = tcg_temp_new();
7806 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7807 gen_qemu_st32(ctx, t0, addr);
7808 tcg_temp_free(t0);
7809 #else
7810 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7811 #endif
7812 gen_addr_add(ctx, addr, addr, 4);
7813 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7814 }
7815
7816 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
7817 {
7818 TCGv t0 = tcg_temp_new();
7819 #if defined(TARGET_PPC64)
7820 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7821 #else
7822 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7823 #endif
7824 gen_qemu_st16(ctx, t0, addr);
7825 gen_addr_add(ctx, addr, addr, 2);
7826 #if defined(TARGET_PPC64)
7827 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7828 gen_qemu_st16(ctx, t0, addr);
7829 #else
7830 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7831 #endif
7832 gen_addr_add(ctx, addr, addr, 2);
7833 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7834 gen_qemu_st16(ctx, t0, addr);
7835 tcg_temp_free(t0);
7836 gen_addr_add(ctx, addr, addr, 2);
7837 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7838 }
7839
7840 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
7841 {
7842 TCGv t0 = tcg_temp_new();
7843 #if defined(TARGET_PPC64)
7844 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
7845 #else
7846 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
7847 #endif
7848 gen_qemu_st16(ctx, t0, addr);
7849 gen_addr_add(ctx, addr, addr, 2);
7850 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
7851 gen_qemu_st16(ctx, t0, addr);
7852 tcg_temp_free(t0);
7853 }
7854
7855 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
7856 {
7857 #if defined(TARGET_PPC64)
7858 TCGv t0 = tcg_temp_new();
7859 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7860 gen_qemu_st16(ctx, t0, addr);
7861 tcg_temp_free(t0);
7862 #else
7863 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7864 #endif
7865 gen_addr_add(ctx, addr, addr, 2);
7866 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7867 }
7868
7869 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
7870 {
7871 #if defined(TARGET_PPC64)
7872 TCGv t0 = tcg_temp_new();
7873 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
7874 gen_qemu_st32(ctx, t0, addr);
7875 tcg_temp_free(t0);
7876 #else
7877 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
7878 #endif
7879 }
7880
7881 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
7882 {
7883 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
7884 }
7885
7886 #define GEN_SPEOP_LDST(name, opc2, sh) \
7887 static void glue(gen_, name)(DisasContext *ctx) \
7888 { \
7889 TCGv t0; \
7890 if (unlikely(!ctx->spe_enabled)) { \
7891 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7892 return; \
7893 } \
7894 gen_set_access_type(ctx, ACCESS_INT); \
7895 t0 = tcg_temp_new(); \
7896 if (Rc(ctx->opcode)) { \
7897 gen_addr_spe_imm_index(ctx, t0, sh); \
7898 } else { \
7899 gen_addr_reg_index(ctx, t0); \
7900 } \
7901 gen_op_##name(ctx, t0); \
7902 tcg_temp_free(t0); \
7903 }
7904
7905 GEN_SPEOP_LDST(evldd, 0x00, 3);
7906 GEN_SPEOP_LDST(evldw, 0x01, 3);
7907 GEN_SPEOP_LDST(evldh, 0x02, 3);
7908 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
7909 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
7910 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
7911 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
7912 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
7913 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
7914 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
7915 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
7916
7917 GEN_SPEOP_LDST(evstdd, 0x10, 3);
7918 GEN_SPEOP_LDST(evstdw, 0x11, 3);
7919 GEN_SPEOP_LDST(evstdh, 0x12, 3);
7920 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
7921 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
7922 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
7923 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
7924
7925 /* Multiply and add - TODO */
7926 #if 0
7927 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
7928 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7929 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7930 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7931 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7932 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7933 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7934 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7935 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7936 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7937 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
7938 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7939
7940 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7941 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7942 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7943 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7944 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7945 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7946 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7947 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
7948 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
7949 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7950 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7951 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7952
7953 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7954 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7955 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7956 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
7957 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
7958
7959 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7960 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7961 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7962 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7963 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7964 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7965 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7966 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7967 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7968 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7969 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
7970 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7971
7972 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7973 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
7974 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7975 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7976
7977 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7978 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7979 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7980 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7981 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7982 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7983 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7984 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7985 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7986 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7987 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
7988 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7989
7990 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7991 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7992 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7993 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
7994 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
7995 #endif
7996
7997 /*** SPE floating-point extension ***/
7998 #if defined(TARGET_PPC64)
7999 #define GEN_SPEFPUOP_CONV_32_32(name) \
8000 static inline void gen_##name(DisasContext *ctx) \
8001 { \
8002 TCGv_i32 t0; \
8003 TCGv t1; \
8004 t0 = tcg_temp_new_i32(); \
8005 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8006 gen_helper_##name(t0, cpu_env, t0); \
8007 t1 = tcg_temp_new(); \
8008 tcg_gen_extu_i32_tl(t1, t0); \
8009 tcg_temp_free_i32(t0); \
8010 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8011 0xFFFFFFFF00000000ULL); \
8012 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8013 tcg_temp_free(t1); \
8014 }
8015 #define GEN_SPEFPUOP_CONV_32_64(name) \
8016 static inline void gen_##name(DisasContext *ctx) \
8017 { \
8018 TCGv_i32 t0; \
8019 TCGv t1; \
8020 t0 = tcg_temp_new_i32(); \
8021 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8022 t1 = tcg_temp_new(); \
8023 tcg_gen_extu_i32_tl(t1, t0); \
8024 tcg_temp_free_i32(t0); \
8025 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8026 0xFFFFFFFF00000000ULL); \
8027 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
8028 tcg_temp_free(t1); \
8029 }
8030 #define GEN_SPEFPUOP_CONV_64_32(name) \
8031 static inline void gen_##name(DisasContext *ctx) \
8032 { \
8033 TCGv_i32 t0 = tcg_temp_new_i32(); \
8034 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8035 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8036 tcg_temp_free_i32(t0); \
8037 }
8038 #define GEN_SPEFPUOP_CONV_64_64(name) \
8039 static inline void gen_##name(DisasContext *ctx) \
8040 { \
8041 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8042 cpu_gpr[rB(ctx->opcode)]); \
8043 }
8044 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8045 static inline void gen_##name(DisasContext *ctx) \
8046 { \
8047 TCGv_i32 t0, t1; \
8048 TCGv_i64 t2; \
8049 if (unlikely(!ctx->spe_enabled)) { \
8050 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8051 return; \
8052 } \
8053 t0 = tcg_temp_new_i32(); \
8054 t1 = tcg_temp_new_i32(); \
8055 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8056 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8057 gen_helper_##name(t0, cpu_env, t0, t1); \
8058 tcg_temp_free_i32(t1); \
8059 t2 = tcg_temp_new(); \
8060 tcg_gen_extu_i32_tl(t2, t0); \
8061 tcg_temp_free_i32(t0); \
8062 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
8063 0xFFFFFFFF00000000ULL); \
8064 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
8065 tcg_temp_free(t2); \
8066 }
8067 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8068 static inline void gen_##name(DisasContext *ctx) \
8069 { \
8070 if (unlikely(!ctx->spe_enabled)) { \
8071 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8072 return; \
8073 } \
8074 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8075 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8076 }
8077 #define GEN_SPEFPUOP_COMP_32(name) \
8078 static inline void gen_##name(DisasContext *ctx) \
8079 { \
8080 TCGv_i32 t0, t1; \
8081 if (unlikely(!ctx->spe_enabled)) { \
8082 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8083 return; \
8084 } \
8085 t0 = tcg_temp_new_i32(); \
8086 t1 = tcg_temp_new_i32(); \
8087 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8088 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8089 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8090 tcg_temp_free_i32(t0); \
8091 tcg_temp_free_i32(t1); \
8092 }
8093 #define GEN_SPEFPUOP_COMP_64(name) \
8094 static inline void gen_##name(DisasContext *ctx) \
8095 { \
8096 if (unlikely(!ctx->spe_enabled)) { \
8097 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8098 return; \
8099 } \
8100 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8101 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8102 }
8103 #else
8104 #define GEN_SPEFPUOP_CONV_32_32(name) \
8105 static inline void gen_##name(DisasContext *ctx) \
8106 { \
8107 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8108 cpu_gpr[rB(ctx->opcode)]); \
8109 }
8110 #define GEN_SPEFPUOP_CONV_32_64(name) \
8111 static inline void gen_##name(DisasContext *ctx) \
8112 { \
8113 TCGv_i64 t0 = tcg_temp_new_i64(); \
8114 gen_load_gpr64(t0, rB(ctx->opcode)); \
8115 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
8116 tcg_temp_free_i64(t0); \
8117 }
8118 #define GEN_SPEFPUOP_CONV_64_32(name) \
8119 static inline void gen_##name(DisasContext *ctx) \
8120 { \
8121 TCGv_i64 t0 = tcg_temp_new_i64(); \
8122 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
8123 gen_store_gpr64(rD(ctx->opcode), t0); \
8124 tcg_temp_free_i64(t0); \
8125 }
8126 #define GEN_SPEFPUOP_CONV_64_64(name) \
8127 static inline void gen_##name(DisasContext *ctx) \
8128 { \
8129 TCGv_i64 t0 = tcg_temp_new_i64(); \
8130 gen_load_gpr64(t0, rB(ctx->opcode)); \
8131 gen_helper_##name(t0, cpu_env, t0); \
8132 gen_store_gpr64(rD(ctx->opcode), t0); \
8133 tcg_temp_free_i64(t0); \
8134 }
8135 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
8136 static inline void gen_##name(DisasContext *ctx) \
8137 { \
8138 if (unlikely(!ctx->spe_enabled)) { \
8139 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8140 return; \
8141 } \
8142 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
8143 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8144 }
8145 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
8146 static inline void gen_##name(DisasContext *ctx) \
8147 { \
8148 TCGv_i64 t0, t1; \
8149 if (unlikely(!ctx->spe_enabled)) { \
8150 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8151 return; \
8152 } \
8153 t0 = tcg_temp_new_i64(); \
8154 t1 = tcg_temp_new_i64(); \
8155 gen_load_gpr64(t0, rA(ctx->opcode)); \
8156 gen_load_gpr64(t1, rB(ctx->opcode)); \
8157 gen_helper_##name(t0, cpu_env, t0, t1); \
8158 gen_store_gpr64(rD(ctx->opcode), t0); \
8159 tcg_temp_free_i64(t0); \
8160 tcg_temp_free_i64(t1); \
8161 }
8162 #define GEN_SPEFPUOP_COMP_32(name) \
8163 static inline void gen_##name(DisasContext *ctx) \
8164 { \
8165 if (unlikely(!ctx->spe_enabled)) { \
8166 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8167 return; \
8168 } \
8169 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
8170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
8171 }
8172 #define GEN_SPEFPUOP_COMP_64(name) \
8173 static inline void gen_##name(DisasContext *ctx) \
8174 { \
8175 TCGv_i64 t0, t1; \
8176 if (unlikely(!ctx->spe_enabled)) { \
8177 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8178 return; \
8179 } \
8180 t0 = tcg_temp_new_i64(); \
8181 t1 = tcg_temp_new_i64(); \
8182 gen_load_gpr64(t0, rA(ctx->opcode)); \
8183 gen_load_gpr64(t1, rB(ctx->opcode)); \
8184 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
8185 tcg_temp_free_i64(t0); \
8186 tcg_temp_free_i64(t1); \
8187 }
8188 #endif
8189
8190 /* Single precision floating-point vectors operations */
8191 /* Arithmetic */
8192 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
8193 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
8194 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
8195 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
8196 static inline void gen_evfsabs(DisasContext *ctx)
8197 {
8198 if (unlikely(!ctx->spe_enabled)) {
8199 gen_exception(ctx, POWERPC_EXCP_SPEU);
8200 return;
8201 }
8202 #if defined(TARGET_PPC64)
8203 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
8204 #else
8205 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
8206 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8207 #endif
8208 }
8209 static inline void gen_evfsnabs(DisasContext *ctx)
8210 {
8211 if (unlikely(!ctx->spe_enabled)) {
8212 gen_exception(ctx, POWERPC_EXCP_SPEU);
8213 return;
8214 }
8215 #if defined(TARGET_PPC64)
8216 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8217 #else
8218 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8219 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8220 #endif
8221 }
8222 static inline void gen_evfsneg(DisasContext *ctx)
8223 {
8224 if (unlikely(!ctx->spe_enabled)) {
8225 gen_exception(ctx, POWERPC_EXCP_SPEU);
8226 return;
8227 }
8228 #if defined(TARGET_PPC64)
8229 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
8230 #else
8231 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8232 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8233 #endif
8234 }
8235
8236 /* Conversion */
8237 GEN_SPEFPUOP_CONV_64_64(evfscfui);
8238 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
8239 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
8240 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
8241 GEN_SPEFPUOP_CONV_64_64(evfsctui);
8242 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
8243 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
8244 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
8245 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
8246 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
8247
8248 /* Comparison */
8249 GEN_SPEFPUOP_COMP_64(evfscmpgt);
8250 GEN_SPEFPUOP_COMP_64(evfscmplt);
8251 GEN_SPEFPUOP_COMP_64(evfscmpeq);
8252 GEN_SPEFPUOP_COMP_64(evfststgt);
8253 GEN_SPEFPUOP_COMP_64(evfststlt);
8254 GEN_SPEFPUOP_COMP_64(evfststeq);
8255
8256 /* Opcodes definitions */
8257 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8258 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8259 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8260 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8261 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8262 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8263 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8264 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8265 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8266 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8267 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8268 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8269 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8270 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8271
8272 /* Single precision floating-point operations */
8273 /* Arithmetic */
8274 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
8275 GEN_SPEFPUOP_ARITH2_32_32(efssub);
8276 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
8277 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
8278 static inline void gen_efsabs(DisasContext *ctx)
8279 {
8280 if (unlikely(!ctx->spe_enabled)) {
8281 gen_exception(ctx, POWERPC_EXCP_SPEU);
8282 return;
8283 }
8284 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
8285 }
8286 static inline void gen_efsnabs(DisasContext *ctx)
8287 {
8288 if (unlikely(!ctx->spe_enabled)) {
8289 gen_exception(ctx, POWERPC_EXCP_SPEU);
8290 return;
8291 }
8292 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8293 }
8294 static inline void gen_efsneg(DisasContext *ctx)
8295 {
8296 if (unlikely(!ctx->spe_enabled)) {
8297 gen_exception(ctx, POWERPC_EXCP_SPEU);
8298 return;
8299 }
8300 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
8301 }
8302
8303 /* Conversion */
8304 GEN_SPEFPUOP_CONV_32_32(efscfui);
8305 GEN_SPEFPUOP_CONV_32_32(efscfsi);
8306 GEN_SPEFPUOP_CONV_32_32(efscfuf);
8307 GEN_SPEFPUOP_CONV_32_32(efscfsf);
8308 GEN_SPEFPUOP_CONV_32_32(efsctui);
8309 GEN_SPEFPUOP_CONV_32_32(efsctsi);
8310 GEN_SPEFPUOP_CONV_32_32(efsctuf);
8311 GEN_SPEFPUOP_CONV_32_32(efsctsf);
8312 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
8313 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
8314 GEN_SPEFPUOP_CONV_32_64(efscfd);
8315
8316 /* Comparison */
8317 GEN_SPEFPUOP_COMP_32(efscmpgt);
8318 GEN_SPEFPUOP_COMP_32(efscmplt);
8319 GEN_SPEFPUOP_COMP_32(efscmpeq);
8320 GEN_SPEFPUOP_COMP_32(efststgt);
8321 GEN_SPEFPUOP_COMP_32(efststlt);
8322 GEN_SPEFPUOP_COMP_32(efststeq);
8323
8324 /* Opcodes definitions */
8325 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8326 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
8327 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8328 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
8329 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8330 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
8331 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8332 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8333 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8334 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
8335 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8336 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8337 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
8338 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
8339
8340 /* Double precision floating-point operations */
8341 /* Arithmetic */
8342 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
8343 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
8344 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
8345 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
8346 static inline void gen_efdabs(DisasContext *ctx)
8347 {
8348 if (unlikely(!ctx->spe_enabled)) {
8349 gen_exception(ctx, POWERPC_EXCP_SPEU);
8350 return;
8351 }
8352 #if defined(TARGET_PPC64)
8353 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
8354 #else
8355 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8356 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
8357 #endif
8358 }
8359 static inline void gen_efdnabs(DisasContext *ctx)
8360 {
8361 if (unlikely(!ctx->spe_enabled)) {
8362 gen_exception(ctx, POWERPC_EXCP_SPEU);
8363 return;
8364 }
8365 #if defined(TARGET_PPC64)
8366 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8367 #else
8368 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8369 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8370 #endif
8371 }
8372 static inline void gen_efdneg(DisasContext *ctx)
8373 {
8374 if (unlikely(!ctx->spe_enabled)) {
8375 gen_exception(ctx, POWERPC_EXCP_SPEU);
8376 return;
8377 }
8378 #if defined(TARGET_PPC64)
8379 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
8380 #else
8381 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8382 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
8383 #endif
8384 }
8385
8386 /* Conversion */
8387 GEN_SPEFPUOP_CONV_64_32(efdcfui);
8388 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
8389 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
8390 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
8391 GEN_SPEFPUOP_CONV_32_64(efdctui);
8392 GEN_SPEFPUOP_CONV_32_64(efdctsi);
8393 GEN_SPEFPUOP_CONV_32_64(efdctuf);
8394 GEN_SPEFPUOP_CONV_32_64(efdctsf);
8395 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
8396 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
8397 GEN_SPEFPUOP_CONV_64_32(efdcfs);
8398 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
8399 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
8400 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
8401 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
8402
8403 /* Comparison */
8404 GEN_SPEFPUOP_COMP_64(efdcmpgt);
8405 GEN_SPEFPUOP_COMP_64(efdcmplt);
8406 GEN_SPEFPUOP_COMP_64(efdcmpeq);
8407 GEN_SPEFPUOP_COMP_64(efdtstgt);
8408 GEN_SPEFPUOP_COMP_64(efdtstlt);
8409 GEN_SPEFPUOP_COMP_64(efdtsteq);
8410
8411 /* Opcodes definitions */
8412 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8413 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8414 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
8415 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8416 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
8417 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8418 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8419 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
8420 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8421 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8422 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8423 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
8424 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8425 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8426 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
8427 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
8428
8429 static opcode_t opcodes[] = {
8430 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
8431 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
8432 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8433 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
8434 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
8435 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
8436 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8437 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8438 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8439 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8440 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
8441 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
8442 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
8443 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
8444 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8445 #if defined(TARGET_PPC64)
8446 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
8447 #endif
8448 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
8449 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
8450 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8451 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8452 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8453 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
8454 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
8455 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
8456 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8457 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8458 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8459 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8460 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
8461 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
8462 #if defined(TARGET_PPC64)
8463 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
8464 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
8465 #endif
8466 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8467 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8468 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8469 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
8470 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
8471 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
8472 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
8473 #if defined(TARGET_PPC64)
8474 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
8475 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
8476 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
8477 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
8478 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
8479 #endif
8480 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
8481 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8482 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
8483 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
8484 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
8485 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
8486 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
8487 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
8488 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
8489 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
8490 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00010000, PPC_FLOAT),
8491 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT),
8492 #if defined(TARGET_PPC64)
8493 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
8494 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
8495 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
8496 #endif
8497 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8498 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
8499 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
8500 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
8501 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
8502 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
8503 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
8504 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
8505 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
8506 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
8507 #if defined(TARGET_PPC64)
8508 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
8509 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
8510 #endif
8511 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
8512 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
8513 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8514 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8515 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
8516 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
8517 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
8518 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
8519 #if defined(TARGET_PPC64)
8520 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
8521 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
8522 #endif
8523 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
8524 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
8525 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
8526 #if defined(TARGET_PPC64)
8527 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
8528 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
8529 #endif
8530 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
8531 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
8532 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
8533 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
8534 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
8535 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
8536 #if defined(TARGET_PPC64)
8537 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
8538 #endif
8539 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
8540 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
8541 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
8542 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
8543 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
8544 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
8545 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
8546 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
8547 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
8548 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
8549 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
8550 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
8551 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
8552 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
8553 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
8554 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
8555 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
8556 #if defined(TARGET_PPC64)
8557 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
8558 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
8559 PPC_SEGMENT_64B),
8560 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
8561 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
8562 PPC_SEGMENT_64B),
8563 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
8564 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
8565 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
8566 #endif
8567 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
8568 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
8569 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
8570 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
8571 #if defined(TARGET_PPC64)
8572 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
8573 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
8574 #endif
8575 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
8576 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
8577 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
8578 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
8579 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
8580 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
8581 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
8582 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
8583 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
8584 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
8585 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
8586 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8587 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
8588 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
8589 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
8590 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
8591 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
8592 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
8593 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
8594 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
8595 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
8596 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
8597 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
8598 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
8599 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
8600 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
8601 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
8602 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
8603 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
8604 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
8605 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
8606 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
8607 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
8608 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
8609 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
8610 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
8611 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
8612 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
8613 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
8614 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
8615 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
8616 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
8617 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
8618 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
8619 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
8620 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
8621 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
8622 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
8623 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
8624 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8625 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8626 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
8627 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
8628 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8629 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
8630 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
8631 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
8632 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
8633 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
8634 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
8635 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
8636 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
8637 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
8638 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
8639 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
8640 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
8641 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
8642 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
8643 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
8644 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
8645 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
8646 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
8647 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
8648 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
8649 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
8650 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
8651 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
8652 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
8653 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
8654 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
8655 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
8656 PPC_NONE, PPC2_BOOKE206),
8657 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
8658 PPC_NONE, PPC2_BOOKE206),
8659 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
8660 PPC_NONE, PPC2_BOOKE206),
8661 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
8662 PPC_NONE, PPC2_BOOKE206),
8663 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
8664 PPC_NONE, PPC2_BOOKE206),
8665 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
8666 PPC_NONE, PPC2_PRCNTL),
8667 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
8668 PPC_NONE, PPC2_PRCNTL),
8669 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
8670 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
8671 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
8672 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
8673 PPC_BOOKE, PPC2_BOOKE206),
8674 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
8675 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
8676 PPC_BOOKE, PPC2_BOOKE206),
8677 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
8678 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
8679 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
8680 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
8681 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
8682 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
8683 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
8684 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
8685 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
8686 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
8687
8688 #undef GEN_INT_ARITH_ADD
8689 #undef GEN_INT_ARITH_ADD_CONST
8690 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
8691 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
8692 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
8693 add_ca, compute_ca, compute_ov) \
8694 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
8695 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
8696 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
8697 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
8698 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
8699 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
8700 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
8701 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
8702 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
8703 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
8704 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
8705
8706 #undef GEN_INT_ARITH_DIVW
8707 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
8708 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
8709 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
8710 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
8711 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
8712 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
8713
8714 #if defined(TARGET_PPC64)
8715 #undef GEN_INT_ARITH_DIVD
8716 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
8717 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8718 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
8719 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
8720 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
8721 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
8722
8723 #undef GEN_INT_ARITH_MUL_HELPER
8724 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
8725 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
8726 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
8727 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
8728 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
8729 #endif
8730
8731 #undef GEN_INT_ARITH_SUBF
8732 #undef GEN_INT_ARITH_SUBF_CONST
8733 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
8734 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
8735 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
8736 add_ca, compute_ca, compute_ov) \
8737 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
8738 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
8739 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
8740 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
8741 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
8742 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
8743 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
8744 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
8745 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
8746 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
8747 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
8748
8749 #undef GEN_LOGICAL1
8750 #undef GEN_LOGICAL2
8751 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
8752 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
8753 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
8754 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
8755 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
8756 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
8757 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
8758 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
8759 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
8760 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
8761 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
8762 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
8763 #if defined(TARGET_PPC64)
8764 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
8765 #endif
8766
8767 #if defined(TARGET_PPC64)
8768 #undef GEN_PPC64_R2
8769 #undef GEN_PPC64_R4
8770 #define GEN_PPC64_R2(name, opc1, opc2) \
8771 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8772 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8773 PPC_64B)
8774 #define GEN_PPC64_R4(name, opc1, opc2) \
8775 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
8776 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
8777 PPC_64B), \
8778 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
8779 PPC_64B), \
8780 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
8781 PPC_64B)
8782 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
8783 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
8784 GEN_PPC64_R4(rldic, 0x1E, 0x04),
8785 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
8786 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
8787 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
8788 #endif
8789
8790 #undef _GEN_FLOAT_ACB
8791 #undef GEN_FLOAT_ACB
8792 #undef _GEN_FLOAT_AB
8793 #undef GEN_FLOAT_AB
8794 #undef _GEN_FLOAT_AC
8795 #undef GEN_FLOAT_AC
8796 #undef GEN_FLOAT_B
8797 #undef GEN_FLOAT_BS
8798 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
8799 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
8800 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
8801 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
8802 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
8803 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8804 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8805 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
8806 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8807 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8808 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
8809 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
8810 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
8811 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
8812 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
8813 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
8814 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
8815 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
8816 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
8817
8818 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
8819 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
8820 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
8821 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
8822 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
8823 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
8824 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
8825 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
8826 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
8827 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
8828 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
8829 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
8830 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
8831 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
8832 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
8833 #if defined(TARGET_PPC64)
8834 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
8835 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
8836 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
8837 #endif
8838 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
8839 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
8840 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
8841 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
8842 GEN_FLOAT_B(abs, 0x08, 0x08, 0, PPC_FLOAT),
8843 GEN_FLOAT_B(nabs, 0x08, 0x04, 0, PPC_FLOAT),
8844 GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT),
8845
8846 #undef GEN_LD
8847 #undef GEN_LDU
8848 #undef GEN_LDUX
8849 #undef GEN_LDX_E
8850 #undef GEN_LDS
8851 #define GEN_LD(name, ldop, opc, type) \
8852 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8853 #define GEN_LDU(name, ldop, opc, type) \
8854 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8855 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
8856 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8857 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
8858 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8859 #define GEN_LDS(name, ldop, op, type) \
8860 GEN_LD(name, ldop, op | 0x20, type) \
8861 GEN_LDU(name, ldop, op | 0x21, type) \
8862 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
8863 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
8864
8865 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
8866 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
8867 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
8868 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
8869 #if defined(TARGET_PPC64)
8870 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
8871 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
8872 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
8873 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
8874 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
8875 #endif
8876 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
8877 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
8878
8879 #undef GEN_ST
8880 #undef GEN_STU
8881 #undef GEN_STUX
8882 #undef GEN_STX_E
8883 #undef GEN_STS
8884 #define GEN_ST(name, stop, opc, type) \
8885 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8886 #define GEN_STU(name, stop, opc, type) \
8887 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
8888 #define GEN_STUX(name, stop, opc2, opc3, type) \
8889 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
8890 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
8891 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
8892 #define GEN_STS(name, stop, op, type) \
8893 GEN_ST(name, stop, op | 0x20, type) \
8894 GEN_STU(name, stop, op | 0x21, type) \
8895 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
8896 GEN_STX(name, stop, 0x17, op | 0x00, type)
8897
8898 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
8899 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
8900 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
8901 #if defined(TARGET_PPC64)
8902 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
8903 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
8904 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
8905 #endif
8906 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
8907 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
8908
8909 #undef GEN_LDF
8910 #undef GEN_LDUF
8911 #undef GEN_LDUXF
8912 #undef GEN_LDXF
8913 #undef GEN_LDFS
8914 #define GEN_LDF(name, ldop, opc, type) \
8915 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8916 #define GEN_LDUF(name, ldop, opc, type) \
8917 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8918 #define GEN_LDUXF(name, ldop, opc, type) \
8919 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8920 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
8921 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8922 #define GEN_LDFS(name, ldop, op, type) \
8923 GEN_LDF(name, ldop, op | 0x20, type) \
8924 GEN_LDUF(name, ldop, op | 0x21, type) \
8925 GEN_LDUXF(name, ldop, op | 0x01, type) \
8926 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
8927
8928 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
8929 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
8930
8931 #undef GEN_STF
8932 #undef GEN_STUF
8933 #undef GEN_STUXF
8934 #undef GEN_STXF
8935 #undef GEN_STFS
8936 #define GEN_STF(name, stop, opc, type) \
8937 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
8938 #define GEN_STUF(name, stop, opc, type) \
8939 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
8940 #define GEN_STUXF(name, stop, opc, type) \
8941 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
8942 #define GEN_STXF(name, stop, opc2, opc3, type) \
8943 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
8944 #define GEN_STFS(name, stop, op, type) \
8945 GEN_STF(name, stop, op | 0x20, type) \
8946 GEN_STUF(name, stop, op | 0x21, type) \
8947 GEN_STUXF(name, stop, op | 0x01, type) \
8948 GEN_STXF(name, stop, 0x17, op | 0x00, type)
8949
8950 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
8951 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
8952 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
8953
8954 #undef GEN_CRLOGIC
8955 #define GEN_CRLOGIC(name, tcg_op, opc) \
8956 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
8957 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
8958 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
8959 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
8960 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
8961 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
8962 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
8963 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
8964 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
8965
8966 #undef GEN_MAC_HANDLER
8967 #define GEN_MAC_HANDLER(name, opc2, opc3) \
8968 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
8969 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
8970 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
8971 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
8972 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
8973 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
8974 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
8975 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
8976 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
8977 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
8978 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
8979 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
8980 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
8981 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
8982 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
8983 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
8984 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
8985 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
8986 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
8987 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
8988 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
8989 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
8990 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
8991 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
8992 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
8993 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
8994 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
8995 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
8996 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
8997 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
8998 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
8999 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
9000 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
9001 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
9002 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
9003 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
9004 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
9005 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
9006 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
9007 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
9008 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
9009 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
9010 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
9011
9012 #undef GEN_VR_LDX
9013 #undef GEN_VR_STX
9014 #undef GEN_VR_LVE
9015 #undef GEN_VR_STVE
9016 #define GEN_VR_LDX(name, opc2, opc3) \
9017 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9018 #define GEN_VR_STX(name, opc2, opc3) \
9019 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9020 #define GEN_VR_LVE(name, opc2, opc3) \
9021 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9022 #define GEN_VR_STVE(name, opc2, opc3) \
9023 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
9024 GEN_VR_LDX(lvx, 0x07, 0x03),
9025 GEN_VR_LDX(lvxl, 0x07, 0x0B),
9026 GEN_VR_LVE(bx, 0x07, 0x00),
9027 GEN_VR_LVE(hx, 0x07, 0x01),
9028 GEN_VR_LVE(wx, 0x07, 0x02),
9029 GEN_VR_STX(svx, 0x07, 0x07),
9030 GEN_VR_STX(svxl, 0x07, 0x0F),
9031 GEN_VR_STVE(bx, 0x07, 0x04),
9032 GEN_VR_STVE(hx, 0x07, 0x05),
9033 GEN_VR_STVE(wx, 0x07, 0x06),
9034
9035 #undef GEN_VX_LOGICAL
9036 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
9037 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9038 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
9039 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
9040 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
9041 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
9042 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
9043
9044 #undef GEN_VXFORM
9045 #define GEN_VXFORM(name, opc2, opc3) \
9046 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9047 GEN_VXFORM(vaddubm, 0, 0),
9048 GEN_VXFORM(vadduhm, 0, 1),
9049 GEN_VXFORM(vadduwm, 0, 2),
9050 GEN_VXFORM(vsububm, 0, 16),
9051 GEN_VXFORM(vsubuhm, 0, 17),
9052 GEN_VXFORM(vsubuwm, 0, 18),
9053 GEN_VXFORM(vmaxub, 1, 0),
9054 GEN_VXFORM(vmaxuh, 1, 1),
9055 GEN_VXFORM(vmaxuw, 1, 2),
9056 GEN_VXFORM(vmaxsb, 1, 4),
9057 GEN_VXFORM(vmaxsh, 1, 5),
9058 GEN_VXFORM(vmaxsw, 1, 6),
9059 GEN_VXFORM(vminub, 1, 8),
9060 GEN_VXFORM(vminuh, 1, 9),
9061 GEN_VXFORM(vminuw, 1, 10),
9062 GEN_VXFORM(vminsb, 1, 12),
9063 GEN_VXFORM(vminsh, 1, 13),
9064 GEN_VXFORM(vminsw, 1, 14),
9065 GEN_VXFORM(vavgub, 1, 16),
9066 GEN_VXFORM(vavguh, 1, 17),
9067 GEN_VXFORM(vavguw, 1, 18),
9068 GEN_VXFORM(vavgsb, 1, 20),
9069 GEN_VXFORM(vavgsh, 1, 21),
9070 GEN_VXFORM(vavgsw, 1, 22),
9071 GEN_VXFORM(vmrghb, 6, 0),
9072 GEN_VXFORM(vmrghh, 6, 1),
9073 GEN_VXFORM(vmrghw, 6, 2),
9074 GEN_VXFORM(vmrglb, 6, 4),
9075 GEN_VXFORM(vmrglh, 6, 5),
9076 GEN_VXFORM(vmrglw, 6, 6),
9077 GEN_VXFORM(vmuloub, 4, 0),
9078 GEN_VXFORM(vmulouh, 4, 1),
9079 GEN_VXFORM(vmulosb, 4, 4),
9080 GEN_VXFORM(vmulosh, 4, 5),
9081 GEN_VXFORM(vmuleub, 4, 8),
9082 GEN_VXFORM(vmuleuh, 4, 9),
9083 GEN_VXFORM(vmulesb, 4, 12),
9084 GEN_VXFORM(vmulesh, 4, 13),
9085 GEN_VXFORM(vslb, 2, 4),
9086 GEN_VXFORM(vslh, 2, 5),
9087 GEN_VXFORM(vslw, 2, 6),
9088 GEN_VXFORM(vsrb, 2, 8),
9089 GEN_VXFORM(vsrh, 2, 9),
9090 GEN_VXFORM(vsrw, 2, 10),
9091 GEN_VXFORM(vsrab, 2, 12),
9092 GEN_VXFORM(vsrah, 2, 13),
9093 GEN_VXFORM(vsraw, 2, 14),
9094 GEN_VXFORM(vslo, 6, 16),
9095 GEN_VXFORM(vsro, 6, 17),
9096 GEN_VXFORM(vaddcuw, 0, 6),
9097 GEN_VXFORM(vsubcuw, 0, 22),
9098 GEN_VXFORM(vaddubs, 0, 8),
9099 GEN_VXFORM(vadduhs, 0, 9),
9100 GEN_VXFORM(vadduws, 0, 10),
9101 GEN_VXFORM(vaddsbs, 0, 12),
9102 GEN_VXFORM(vaddshs, 0, 13),
9103 GEN_VXFORM(vaddsws, 0, 14),
9104 GEN_VXFORM(vsububs, 0, 24),
9105 GEN_VXFORM(vsubuhs, 0, 25),
9106 GEN_VXFORM(vsubuws, 0, 26),
9107 GEN_VXFORM(vsubsbs, 0, 28),
9108 GEN_VXFORM(vsubshs, 0, 29),
9109 GEN_VXFORM(vsubsws, 0, 30),
9110 GEN_VXFORM(vrlb, 2, 0),
9111 GEN_VXFORM(vrlh, 2, 1),
9112 GEN_VXFORM(vrlw, 2, 2),
9113 GEN_VXFORM(vsl, 2, 7),
9114 GEN_VXFORM(vsr, 2, 11),
9115 GEN_VXFORM(vpkuhum, 7, 0),
9116 GEN_VXFORM(vpkuwum, 7, 1),
9117 GEN_VXFORM(vpkuhus, 7, 2),
9118 GEN_VXFORM(vpkuwus, 7, 3),
9119 GEN_VXFORM(vpkshus, 7, 4),
9120 GEN_VXFORM(vpkswus, 7, 5),
9121 GEN_VXFORM(vpkshss, 7, 6),
9122 GEN_VXFORM(vpkswss, 7, 7),
9123 GEN_VXFORM(vpkpx, 7, 12),
9124 GEN_VXFORM(vsum4ubs, 4, 24),
9125 GEN_VXFORM(vsum4sbs, 4, 28),
9126 GEN_VXFORM(vsum4shs, 4, 25),
9127 GEN_VXFORM(vsum2sws, 4, 26),
9128 GEN_VXFORM(vsumsws, 4, 30),
9129 GEN_VXFORM(vaddfp, 5, 0),
9130 GEN_VXFORM(vsubfp, 5, 1),
9131 GEN_VXFORM(vmaxfp, 5, 16),
9132 GEN_VXFORM(vminfp, 5, 17),
9133
9134 #undef GEN_VXRFORM1
9135 #undef GEN_VXRFORM
9136 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
9137 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
9138 #define GEN_VXRFORM(name, opc2, opc3) \
9139 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
9140 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
9141 GEN_VXRFORM(vcmpequb, 3, 0)
9142 GEN_VXRFORM(vcmpequh, 3, 1)
9143 GEN_VXRFORM(vcmpequw, 3, 2)
9144 GEN_VXRFORM(vcmpgtsb, 3, 12)
9145 GEN_VXRFORM(vcmpgtsh, 3, 13)
9146 GEN_VXRFORM(vcmpgtsw, 3, 14)
9147 GEN_VXRFORM(vcmpgtub, 3, 8)
9148 GEN_VXRFORM(vcmpgtuh, 3, 9)
9149 GEN_VXRFORM(vcmpgtuw, 3, 10)
9150 GEN_VXRFORM(vcmpeqfp, 3, 3)
9151 GEN_VXRFORM(vcmpgefp, 3, 7)
9152 GEN_VXRFORM(vcmpgtfp, 3, 11)
9153 GEN_VXRFORM(vcmpbfp, 3, 15)
9154
9155 #undef GEN_VXFORM_SIMM
9156 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
9157 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9158 GEN_VXFORM_SIMM(vspltisb, 6, 12),
9159 GEN_VXFORM_SIMM(vspltish, 6, 13),
9160 GEN_VXFORM_SIMM(vspltisw, 6, 14),
9161
9162 #undef GEN_VXFORM_NOA
9163 #define GEN_VXFORM_NOA(name, opc2, opc3) \
9164 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
9165 GEN_VXFORM_NOA(vupkhsb, 7, 8),
9166 GEN_VXFORM_NOA(vupkhsh, 7, 9),
9167 GEN_VXFORM_NOA(vupklsb, 7, 10),
9168 GEN_VXFORM_NOA(vupklsh, 7, 11),
9169 GEN_VXFORM_NOA(vupkhpx, 7, 13),
9170 GEN_VXFORM_NOA(vupklpx, 7, 15),
9171 GEN_VXFORM_NOA(vrefp, 5, 4),
9172 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
9173 GEN_VXFORM_NOA(vexptefp, 5, 6),
9174 GEN_VXFORM_NOA(vlogefp, 5, 7),
9175 GEN_VXFORM_NOA(vrfim, 5, 8),
9176 GEN_VXFORM_NOA(vrfin, 5, 9),
9177 GEN_VXFORM_NOA(vrfip, 5, 10),
9178 GEN_VXFORM_NOA(vrfiz, 5, 11),
9179
9180 #undef GEN_VXFORM_UIMM
9181 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
9182 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
9183 GEN_VXFORM_UIMM(vspltb, 6, 8),
9184 GEN_VXFORM_UIMM(vsplth, 6, 9),
9185 GEN_VXFORM_UIMM(vspltw, 6, 10),
9186 GEN_VXFORM_UIMM(vcfux, 5, 12),
9187 GEN_VXFORM_UIMM(vcfsx, 5, 13),
9188 GEN_VXFORM_UIMM(vctuxs, 5, 14),
9189 GEN_VXFORM_UIMM(vctsxs, 5, 15),
9190
9191 #undef GEN_VAFORM_PAIRED
9192 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
9193 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
9194 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
9195 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
9196 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
9197 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
9198 GEN_VAFORM_PAIRED(vsel, vperm, 21),
9199 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
9200
9201 #undef GEN_SPE
9202 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
9203 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
9204 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9205 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9206 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9207 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9208 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9209 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9210 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
9211 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
9212 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
9213 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9214 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9215 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9216 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9217 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9218 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
9219 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
9220 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
9221 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9222 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9223 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9224 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9225 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
9226 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9227 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
9228 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9229 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
9230 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9231 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
9232 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
9233
9234 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9235 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9236 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9237 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9238 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9239 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9240 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9241 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9242 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9243 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9244 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9245 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9246 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9247 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9248
9249 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9250 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
9251 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
9252 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
9253 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9254 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
9255 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9256 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9257 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9258 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
9259 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9260 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9261 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
9262 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
9263
9264 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9265 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9266 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
9267 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9268 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
9269 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9270 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9271 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
9272 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9273 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9274 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9275 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
9276 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9277 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9278 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
9279 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
9280
9281 #undef GEN_SPEOP_LDST
9282 #define GEN_SPEOP_LDST(name, opc2, sh) \
9283 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
9284 GEN_SPEOP_LDST(evldd, 0x00, 3),
9285 GEN_SPEOP_LDST(evldw, 0x01, 3),
9286 GEN_SPEOP_LDST(evldh, 0x02, 3),
9287 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
9288 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
9289 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
9290 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
9291 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
9292 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
9293 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
9294 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
9295
9296 GEN_SPEOP_LDST(evstdd, 0x10, 3),
9297 GEN_SPEOP_LDST(evstdw, 0x11, 3),
9298 GEN_SPEOP_LDST(evstdh, 0x12, 3),
9299 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
9300 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
9301 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
9302 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
9303 };
9304
9305 #include "helper_regs.h"
9306 #include "translate_init.c"
9307
9308 /*****************************************************************************/
9309 /* Misc PowerPC helpers */
9310 void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf,
9311 int flags)
9312 {
9313 #define RGPL 4
9314 #define RFPL 4
9315
9316 int i;
9317
9318 cpu_synchronize_state(env);
9319
9320 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
9321 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
9322 env->nip, env->lr, env->ctr, cpu_read_xer(env));
9323 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
9324 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
9325 env->hflags, env->mmu_idx);
9326 #if !defined(NO_TIMER_DUMP)
9327 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
9328 #if !defined(CONFIG_USER_ONLY)
9329 " DECR %08" PRIu32
9330 #endif
9331 "\n",
9332 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
9333 #if !defined(CONFIG_USER_ONLY)
9334 , cpu_ppc_load_decr(env)
9335 #endif
9336 );
9337 #endif
9338 for (i = 0; i < 32; i++) {
9339 if ((i & (RGPL - 1)) == 0)
9340 cpu_fprintf(f, "GPR%02d", i);
9341 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
9342 if ((i & (RGPL - 1)) == (RGPL - 1))
9343 cpu_fprintf(f, "\n");
9344 }
9345 cpu_fprintf(f, "CR ");
9346 for (i = 0; i < 8; i++)
9347 cpu_fprintf(f, "%01x", env->crf[i]);
9348 cpu_fprintf(f, " [");
9349 for (i = 0; i < 8; i++) {
9350 char a = '-';
9351 if (env->crf[i] & 0x08)
9352 a = 'L';
9353 else if (env->crf[i] & 0x04)
9354 a = 'G';
9355 else if (env->crf[i] & 0x02)
9356 a = 'E';
9357 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
9358 }
9359 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
9360 env->reserve_addr);
9361 for (i = 0; i < 32; i++) {
9362 if ((i & (RFPL - 1)) == 0)
9363 cpu_fprintf(f, "FPR%02d", i);
9364 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
9365 if ((i & (RFPL - 1)) == (RFPL - 1))
9366 cpu_fprintf(f, "\n");
9367 }
9368 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
9369 #if !defined(CONFIG_USER_ONLY)
9370 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
9371 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
9372 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
9373 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
9374
9375 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
9376 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
9377 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
9378 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
9379
9380 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
9381 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
9382 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
9383 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
9384
9385 if (env->excp_model == POWERPC_EXCP_BOOKE) {
9386 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
9387 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
9388 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
9389 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
9390
9391 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
9392 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
9393 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
9394 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
9395
9396 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
9397 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
9398 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
9399 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
9400
9401 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
9402 " EPR " TARGET_FMT_lx "\n",
9403 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
9404 env->spr[SPR_BOOKE_EPR]);
9405
9406 /* FSL-specific */
9407 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
9408 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
9409 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
9410 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
9411
9412 /*
9413 * IVORs are left out as they are large and do not change often --
9414 * they can be read with "p $ivor0", "p $ivor1", etc.
9415 */
9416 }
9417
9418 #if defined(TARGET_PPC64)
9419 if (env->flags & POWERPC_FLAG_CFAR) {
9420 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
9421 }
9422 #endif
9423
9424 switch (env->mmu_model) {
9425 case POWERPC_MMU_32B:
9426 case POWERPC_MMU_601:
9427 case POWERPC_MMU_SOFT_6xx:
9428 case POWERPC_MMU_SOFT_74xx:
9429 #if defined(TARGET_PPC64)
9430 case POWERPC_MMU_620:
9431 case POWERPC_MMU_64B:
9432 #endif
9433 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "\n", env->spr[SPR_SDR1]);
9434 break;
9435 case POWERPC_MMU_BOOKE206:
9436 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
9437 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
9438 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
9439 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
9440
9441 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
9442 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
9443 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
9444 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
9445
9446 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
9447 " TLB1CFG " TARGET_FMT_lx "\n",
9448 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
9449 env->spr[SPR_BOOKE_TLB1CFG]);
9450 break;
9451 default:
9452 break;
9453 }
9454 #endif
9455
9456 #undef RGPL
9457 #undef RFPL
9458 }
9459
9460 void cpu_dump_statistics (CPUPPCState *env, FILE*f, fprintf_function cpu_fprintf,
9461 int flags)
9462 {
9463 #if defined(DO_PPC_STATISTICS)
9464 opc_handler_t **t1, **t2, **t3, *handler;
9465 int op1, op2, op3;
9466
9467 t1 = env->opcodes;
9468 for (op1 = 0; op1 < 64; op1++) {
9469 handler = t1[op1];
9470 if (is_indirect_opcode(handler)) {
9471 t2 = ind_table(handler);
9472 for (op2 = 0; op2 < 32; op2++) {
9473 handler = t2[op2];
9474 if (is_indirect_opcode(handler)) {
9475 t3 = ind_table(handler);
9476 for (op3 = 0; op3 < 32; op3++) {
9477 handler = t3[op3];
9478 if (handler->count == 0)
9479 continue;
9480 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
9481 "%016" PRIx64 " %" PRId64 "\n",
9482 op1, op2, op3, op1, (op3 << 5) | op2,
9483 handler->oname,
9484 handler->count, handler->count);
9485 }
9486 } else {
9487 if (handler->count == 0)
9488 continue;
9489 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
9490 "%016" PRIx64 " %" PRId64 "\n",
9491 op1, op2, op1, op2, handler->oname,
9492 handler->count, handler->count);
9493 }
9494 }
9495 } else {
9496 if (handler->count == 0)
9497 continue;
9498 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
9499 " %" PRId64 "\n",
9500 op1, op1, handler->oname,
9501 handler->count, handler->count);
9502 }
9503 }
9504 #endif
9505 }
9506
9507 /*****************************************************************************/
9508 static inline void gen_intermediate_code_internal(CPUPPCState *env,
9509 TranslationBlock *tb,
9510 int search_pc)
9511 {
9512 DisasContext ctx, *ctxp = &ctx;
9513 opc_handler_t **table, *handler;
9514 target_ulong pc_start;
9515 uint16_t *gen_opc_end;
9516 CPUBreakpoint *bp;
9517 int j, lj = -1;
9518 int num_insns;
9519 int max_insns;
9520
9521 pc_start = tb->pc;
9522 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
9523 ctx.nip = pc_start;
9524 ctx.tb = tb;
9525 ctx.exception = POWERPC_EXCP_NONE;
9526 ctx.spr_cb = env->spr_cb;
9527 ctx.mem_idx = env->mmu_idx;
9528 ctx.access_type = -1;
9529 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
9530 #if defined(TARGET_PPC64)
9531 ctx.sf_mode = msr_is_64bit(env, env->msr);
9532 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
9533 #endif
9534 ctx.fpu_enabled = msr_fp;
9535 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
9536 ctx.spe_enabled = msr_spe;
9537 else
9538 ctx.spe_enabled = 0;
9539 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
9540 ctx.altivec_enabled = msr_vr;
9541 else
9542 ctx.altivec_enabled = 0;
9543 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
9544 ctx.singlestep_enabled = CPU_SINGLE_STEP;
9545 else
9546 ctx.singlestep_enabled = 0;
9547 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
9548 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
9549 if (unlikely(env->singlestep_enabled))
9550 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
9551 #if defined (DO_SINGLE_STEP) && 0
9552 /* Single step trace mode */
9553 msr_se = 1;
9554 #endif
9555 num_insns = 0;
9556 max_insns = tb->cflags & CF_COUNT_MASK;
9557 if (max_insns == 0)
9558 max_insns = CF_COUNT_MASK;
9559
9560 gen_icount_start();
9561 /* Set env in case of segfault during code fetch */
9562 while (ctx.exception == POWERPC_EXCP_NONE
9563 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
9564 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
9565 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
9566 if (bp->pc == ctx.nip) {
9567 gen_debug_exception(ctxp);
9568 break;
9569 }
9570 }
9571 }
9572 if (unlikely(search_pc)) {
9573 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9574 if (lj < j) {
9575 lj++;
9576 while (lj < j)
9577 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9578 }
9579 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
9580 tcg_ctx.gen_opc_instr_start[lj] = 1;
9581 tcg_ctx.gen_opc_icount[lj] = num_insns;
9582 }
9583 LOG_DISAS("----------------\n");
9584 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
9585 ctx.nip, ctx.mem_idx, (int)msr_ir);
9586 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
9587 gen_io_start();
9588 if (unlikely(ctx.le_mode)) {
9589 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
9590 } else {
9591 ctx.opcode = cpu_ldl_code(env, ctx.nip);
9592 }
9593 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
9594 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
9595 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
9596 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
9597 tcg_gen_debug_insn_start(ctx.nip);
9598 }
9599 ctx.nip += 4;
9600 table = env->opcodes;
9601 num_insns++;
9602 handler = table[opc1(ctx.opcode)];
9603 if (is_indirect_opcode(handler)) {
9604 table = ind_table(handler);
9605 handler = table[opc2(ctx.opcode)];
9606 if (is_indirect_opcode(handler)) {
9607 table = ind_table(handler);
9608 handler = table[opc3(ctx.opcode)];
9609 }
9610 }
9611 /* Is opcode *REALLY* valid ? */
9612 if (unlikely(handler->handler == &gen_invalid)) {
9613 if (qemu_log_enabled()) {
9614 qemu_log("invalid/unsupported opcode: "
9615 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
9616 opc1(ctx.opcode), opc2(ctx.opcode),
9617 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
9618 }
9619 } else {
9620 uint32_t inval;
9621
9622 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
9623 inval = handler->inval2;
9624 } else {
9625 inval = handler->inval1;
9626 }
9627
9628 if (unlikely((ctx.opcode & inval) != 0)) {
9629 if (qemu_log_enabled()) {
9630 qemu_log("invalid bits: %08x for opcode: "
9631 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
9632 ctx.opcode & inval, opc1(ctx.opcode),
9633 opc2(ctx.opcode), opc3(ctx.opcode),
9634 ctx.opcode, ctx.nip - 4);
9635 }
9636 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
9637 break;
9638 }
9639 }
9640 (*(handler->handler))(&ctx);
9641 #if defined(DO_PPC_STATISTICS)
9642 handler->count++;
9643 #endif
9644 /* Check trace mode exceptions */
9645 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
9646 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
9647 ctx.exception != POWERPC_SYSCALL &&
9648 ctx.exception != POWERPC_EXCP_TRAP &&
9649 ctx.exception != POWERPC_EXCP_BRANCH)) {
9650 gen_exception(ctxp, POWERPC_EXCP_TRACE);
9651 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
9652 (env->singlestep_enabled) ||
9653 singlestep ||
9654 num_insns >= max_insns)) {
9655 /* if we reach a page boundary or are single stepping, stop
9656 * generation
9657 */
9658 break;
9659 }
9660 }
9661 if (tb->cflags & CF_LAST_IO)
9662 gen_io_end();
9663 if (ctx.exception == POWERPC_EXCP_NONE) {
9664 gen_goto_tb(&ctx, 0, ctx.nip);
9665 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
9666 if (unlikely(env->singlestep_enabled)) {
9667 gen_debug_exception(ctxp);
9668 }
9669 /* Generate the return instruction */
9670 tcg_gen_exit_tb(0);
9671 }
9672 gen_icount_end(tb, num_insns);
9673 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
9674 if (unlikely(search_pc)) {
9675 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
9676 lj++;
9677 while (lj <= j)
9678 tcg_ctx.gen_opc_instr_start[lj++] = 0;
9679 } else {
9680 tb->size = ctx.nip - pc_start;
9681 tb->icount = num_insns;
9682 }
9683 #if defined(DEBUG_DISAS)
9684 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
9685 int flags;
9686 flags = env->bfd_mach;
9687 flags |= ctx.le_mode << 16;
9688 qemu_log("IN: %s\n", lookup_symbol(pc_start));
9689 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
9690 qemu_log("\n");
9691 }
9692 #endif
9693 }
9694
9695 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
9696 {
9697 gen_intermediate_code_internal(env, tb, 0);
9698 }
9699
9700 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
9701 {
9702 gen_intermediate_code_internal(env, tb, 1);
9703 }
9704
9705 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
9706 {
9707 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
9708 }
Various patches