2 * Status and system control registers for ARM RealView/Versatile boards.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
11 #include "qemu-timer.h"
13 #include "primecell.h"
16 #define LOCK_VALUE 0xa05f
21 qemu_irq pl110_mux_ctrl
;
39 static const VMStateDescription vmstate_arm_sysctl
= {
40 .name
= "realview_sysctl",
42 .minimum_version_id
= 1,
43 .fields
= (VMStateField
[]) {
44 VMSTATE_UINT32(leds
, arm_sysctl_state
),
45 VMSTATE_UINT16(lockval
, arm_sysctl_state
),
46 VMSTATE_UINT32(cfgdata1
, arm_sysctl_state
),
47 VMSTATE_UINT32(cfgdata2
, arm_sysctl_state
),
48 VMSTATE_UINT32(flags
, arm_sysctl_state
),
49 VMSTATE_UINT32(nvflags
, arm_sysctl_state
),
50 VMSTATE_UINT32(resetlevel
, arm_sysctl_state
),
51 VMSTATE_UINT32_V(sys_mci
, arm_sysctl_state
, 2),
52 VMSTATE_UINT32_V(sys_cfgdata
, arm_sysctl_state
, 2),
53 VMSTATE_UINT32_V(sys_cfgctrl
, arm_sysctl_state
, 2),
54 VMSTATE_UINT32_V(sys_cfgstat
, arm_sysctl_state
, 2),
55 VMSTATE_UINT32_V(sys_clcd
, arm_sysctl_state
, 3),
60 /* The PB926 actually uses a different format for
61 * its SYS_ID register. Fortunately the bits which are
62 * board type on later boards are distinct.
64 #define BOARD_ID_PB926 0x100
65 #define BOARD_ID_EB 0x140
66 #define BOARD_ID_PBA8 0x178
67 #define BOARD_ID_PBX 0x182
68 #define BOARD_ID_VEXPRESS 0x190
70 static int board_id(arm_sysctl_state
*s
)
72 /* Extract the board ID field from the SYS_ID register value */
73 return (s
->sys_id
>> 16) & 0xfff;
76 static void arm_sysctl_reset(DeviceState
*d
)
78 arm_sysctl_state
*s
= FROM_SYSBUS(arm_sysctl_state
, sysbus_from_qdev(d
));
86 if (board_id(s
) == BOARD_ID_VEXPRESS
) {
87 /* On VExpress this register will RAZ/WI */
90 /* All others: CLCDID 0x1f, indicating VGA */
95 static uint64_t arm_sysctl_read(void *opaque
, hwaddr offset
,
98 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
104 /* General purpose hardware switches.
105 We don't have a useful way of exposing these to the user. */
109 case 0x20: /* LOCK */
111 case 0x0c: /* OSC0 */
112 case 0x10: /* OSC1 */
113 case 0x14: /* OSC2 */
114 case 0x18: /* OSC3 */
115 case 0x1c: /* OSC4 */
116 case 0x24: /* 100HZ */
117 /* ??? Implement these. */
119 case 0x28: /* CFGDATA1 */
121 case 0x2c: /* CFGDATA2 */
123 case 0x30: /* FLAGS */
125 case 0x38: /* NVFLAGS */
127 case 0x40: /* RESETCTL */
128 if (board_id(s
) == BOARD_ID_VEXPRESS
) {
129 /* reserved: RAZ/WI */
132 return s
->resetlevel
;
133 case 0x44: /* PCICTL */
137 case 0x4c: /* FLASH */
139 case 0x50: /* CLCD */
141 case 0x54: /* CLCDSER */
143 case 0x58: /* BOOTCS */
145 case 0x5c: /* 24MHz */
146 return muldiv64(qemu_get_clock_ns(vm_clock
), 24000000, get_ticks_per_sec());
147 case 0x60: /* MISC */
149 case 0x84: /* PROCID0 */
151 case 0x88: /* PROCID1 */
153 case 0x64: /* DMAPSR0 */
154 case 0x68: /* DMAPSR1 */
155 case 0x6c: /* DMAPSR2 */
156 case 0x70: /* IOSEL */
157 case 0x74: /* PLDCTL */
158 case 0x80: /* BUSID */
159 case 0x8c: /* OSCRESET0 */
160 case 0x90: /* OSCRESET1 */
161 case 0x94: /* OSCRESET2 */
162 case 0x98: /* OSCRESET3 */
163 case 0x9c: /* OSCRESET4 */
164 case 0xc0: /* SYS_TEST_OSC0 */
165 case 0xc4: /* SYS_TEST_OSC1 */
166 case 0xc8: /* SYS_TEST_OSC2 */
167 case 0xcc: /* SYS_TEST_OSC3 */
168 case 0xd0: /* SYS_TEST_OSC4 */
170 case 0xa0: /* SYS_CFGDATA */
171 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
174 return s
->sys_cfgdata
;
175 case 0xa4: /* SYS_CFGCTRL */
176 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
179 return s
->sys_cfgctrl
;
180 case 0xa8: /* SYS_CFGSTAT */
181 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
184 return s
->sys_cfgstat
;
187 qemu_log_mask(LOG_GUEST_ERROR
,
188 "arm_sysctl_read: Bad register offset 0x%x\n",
194 static void arm_sysctl_write(void *opaque
, hwaddr offset
,
195 uint64_t val
, unsigned size
)
197 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
202 case 0x0c: /* OSC0 */
203 case 0x10: /* OSC1 */
204 case 0x14: /* OSC2 */
205 case 0x18: /* OSC3 */
206 case 0x1c: /* OSC4 */
209 case 0x20: /* LOCK */
210 if (val
== LOCK_VALUE
)
213 s
->lockval
= val
& 0x7fff;
215 case 0x28: /* CFGDATA1 */
216 /* ??? Need to implement this. */
219 case 0x2c: /* CFGDATA2 */
220 /* ??? Need to implement this. */
223 case 0x30: /* FLAGSSET */
226 case 0x34: /* FLAGSCLR */
229 case 0x38: /* NVFLAGSSET */
232 case 0x3c: /* NVFLAGSCLR */
235 case 0x40: /* RESETCTL */
236 switch (board_id(s
)) {
238 if (s
->lockval
== LOCK_VALUE
) {
241 qemu_system_reset_request();
247 if (s
->lockval
== LOCK_VALUE
) {
250 qemu_system_reset_request();
254 case BOARD_ID_VEXPRESS
:
257 /* reserved: RAZ/WI */
261 case 0x44: /* PCICTL */
264 case 0x4c: /* FLASH */
266 case 0x50: /* CLCD */
267 switch (board_id(s
)) {
269 /* On 926 bits 13:8 are R/O, bits 1:0 control
270 * the mux that defines how to interpret the PL110
271 * graphics format, and other bits are r/w but we
272 * don't implement them to do anything.
274 s
->sys_clcd
&= 0x3f00;
275 s
->sys_clcd
|= val
& ~0x3f00;
276 qemu_set_irq(s
->pl110_mux_ctrl
, val
& 3);
279 /* The EB is the same except that there is no mux since
280 * the EB has a PL111.
282 s
->sys_clcd
&= 0x3f00;
283 s
->sys_clcd
|= val
& ~0x3f00;
287 /* On PBA8 and PBX bit 7 is r/w and all other bits
288 * are either r/o or RAZ/WI.
290 s
->sys_clcd
&= (1 << 7);
291 s
->sys_clcd
|= val
& ~(1 << 7);
293 case BOARD_ID_VEXPRESS
:
295 /* On VExpress this register is unimplemented and will RAZ/WI */
298 case 0x54: /* CLCDSER */
299 case 0x64: /* DMAPSR0 */
300 case 0x68: /* DMAPSR1 */
301 case 0x6c: /* DMAPSR2 */
302 case 0x70: /* IOSEL */
303 case 0x74: /* PLDCTL */
304 case 0x80: /* BUSID */
305 case 0x84: /* PROCID0 */
306 case 0x88: /* PROCID1 */
307 case 0x8c: /* OSCRESET0 */
308 case 0x90: /* OSCRESET1 */
309 case 0x94: /* OSCRESET2 */
310 case 0x98: /* OSCRESET3 */
311 case 0x9c: /* OSCRESET4 */
313 case 0xa0: /* SYS_CFGDATA */
314 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
317 s
->sys_cfgdata
= val
;
319 case 0xa4: /* SYS_CFGCTRL */
320 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
323 s
->sys_cfgctrl
= val
& ~(3 << 18);
324 s
->sys_cfgstat
= 1; /* complete */
325 switch (s
->sys_cfgctrl
) {
326 case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
327 qemu_system_shutdown_request();
329 case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
330 qemu_system_reset_request();
333 s
->sys_cfgstat
|= 2; /* error */
336 case 0xa8: /* SYS_CFGSTAT */
337 if (board_id(s
) != BOARD_ID_VEXPRESS
) {
340 s
->sys_cfgstat
= val
& 3;
344 qemu_log_mask(LOG_GUEST_ERROR
,
345 "arm_sysctl_write: Bad register offset 0x%x\n",
351 static const MemoryRegionOps arm_sysctl_ops
= {
352 .read
= arm_sysctl_read
,
353 .write
= arm_sysctl_write
,
354 .endianness
= DEVICE_NATIVE_ENDIAN
,
357 static void arm_sysctl_gpio_set(void *opaque
, int line
, int level
)
359 arm_sysctl_state
*s
= (arm_sysctl_state
*)opaque
;
361 case ARM_SYSCTL_GPIO_MMC_WPROT
:
363 /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
364 * for all later boards it is bit 1.
367 if ((board_id(s
) == BOARD_ID_PB926
) || (board_id(s
) == BOARD_ID_EB
)) {
376 case ARM_SYSCTL_GPIO_MMC_CARDIN
:
385 static int arm_sysctl_init(SysBusDevice
*dev
)
387 arm_sysctl_state
*s
= FROM_SYSBUS(arm_sysctl_state
, dev
);
389 memory_region_init_io(&s
->iomem
, &arm_sysctl_ops
, s
, "arm-sysctl", 0x1000);
390 sysbus_init_mmio(dev
, &s
->iomem
);
391 qdev_init_gpio_in(&s
->busdev
.qdev
, arm_sysctl_gpio_set
, 2);
392 qdev_init_gpio_out(&s
->busdev
.qdev
, &s
->pl110_mux_ctrl
, 1);
396 static Property arm_sysctl_properties
[] = {
397 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state
, sys_id
, 0),
398 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state
, proc_id
, 0),
399 DEFINE_PROP_END_OF_LIST(),
402 static void arm_sysctl_class_init(ObjectClass
*klass
, void *data
)
404 DeviceClass
*dc
= DEVICE_CLASS(klass
);
405 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
407 k
->init
= arm_sysctl_init
;
408 dc
->reset
= arm_sysctl_reset
;
409 dc
->vmsd
= &vmstate_arm_sysctl
;
410 dc
->props
= arm_sysctl_properties
;
413 static TypeInfo arm_sysctl_info
= {
414 .name
= "realview_sysctl",
415 .parent
= TYPE_SYS_BUS_DEVICE
,
416 .instance_size
= sizeof(arm_sysctl_state
),
417 .class_init
= arm_sysctl_class_init
,
420 static void arm_sysctl_register_types(void)
422 type_register_static(&arm_sysctl_info
);
425 type_init(arm_sysctl_register_types
)