configure: Default to 'cc', not 'gcc'
[qemu/pbrook.git] / hw / arm_sysctl.c
blob58eb98216d1c288fb873e847520f148cd7ea593f
1 /*
2 * Status and system control registers for ARM RealView/Versatile boards.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "hw.h"
11 #include "qemu-timer.h"
12 #include "sysbus.h"
13 #include "primecell.h"
14 #include "sysemu.h"
16 #define LOCK_VALUE 0xa05f
18 typedef struct {
19 SysBusDevice busdev;
20 MemoryRegion iomem;
21 qemu_irq pl110_mux_ctrl;
23 uint32_t sys_id;
24 uint32_t leds;
25 uint16_t lockval;
26 uint32_t cfgdata1;
27 uint32_t cfgdata2;
28 uint32_t flags;
29 uint32_t nvflags;
30 uint32_t resetlevel;
31 uint32_t proc_id;
32 uint32_t sys_mci;
33 uint32_t sys_cfgdata;
34 uint32_t sys_cfgctrl;
35 uint32_t sys_cfgstat;
36 uint32_t sys_clcd;
37 } arm_sysctl_state;
39 static const VMStateDescription vmstate_arm_sysctl = {
40 .name = "realview_sysctl",
41 .version_id = 3,
42 .minimum_version_id = 1,
43 .fields = (VMStateField[]) {
44 VMSTATE_UINT32(leds, arm_sysctl_state),
45 VMSTATE_UINT16(lockval, arm_sysctl_state),
46 VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
47 VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
48 VMSTATE_UINT32(flags, arm_sysctl_state),
49 VMSTATE_UINT32(nvflags, arm_sysctl_state),
50 VMSTATE_UINT32(resetlevel, arm_sysctl_state),
51 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
52 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
53 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
54 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
55 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
56 VMSTATE_END_OF_LIST()
60 /* The PB926 actually uses a different format for
61 * its SYS_ID register. Fortunately the bits which are
62 * board type on later boards are distinct.
64 #define BOARD_ID_PB926 0x100
65 #define BOARD_ID_EB 0x140
66 #define BOARD_ID_PBA8 0x178
67 #define BOARD_ID_PBX 0x182
68 #define BOARD_ID_VEXPRESS 0x190
70 static int board_id(arm_sysctl_state *s)
72 /* Extract the board ID field from the SYS_ID register value */
73 return (s->sys_id >> 16) & 0xfff;
76 static void arm_sysctl_reset(DeviceState *d)
78 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d));
80 s->leds = 0;
81 s->lockval = 0;
82 s->cfgdata1 = 0;
83 s->cfgdata2 = 0;
84 s->flags = 0;
85 s->resetlevel = 0;
86 if (board_id(s) == BOARD_ID_VEXPRESS) {
87 /* On VExpress this register will RAZ/WI */
88 s->sys_clcd = 0;
89 } else {
90 /* All others: CLCDID 0x1f, indicating VGA */
91 s->sys_clcd = 0x1f00;
95 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
96 unsigned size)
98 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
100 switch (offset) {
101 case 0x00: /* ID */
102 return s->sys_id;
103 case 0x04: /* SW */
104 /* General purpose hardware switches.
105 We don't have a useful way of exposing these to the user. */
106 return 0;
107 case 0x08: /* LED */
108 return s->leds;
109 case 0x20: /* LOCK */
110 return s->lockval;
111 case 0x0c: /* OSC0 */
112 case 0x10: /* OSC1 */
113 case 0x14: /* OSC2 */
114 case 0x18: /* OSC3 */
115 case 0x1c: /* OSC4 */
116 case 0x24: /* 100HZ */
117 /* ??? Implement these. */
118 return 0;
119 case 0x28: /* CFGDATA1 */
120 return s->cfgdata1;
121 case 0x2c: /* CFGDATA2 */
122 return s->cfgdata2;
123 case 0x30: /* FLAGS */
124 return s->flags;
125 case 0x38: /* NVFLAGS */
126 return s->nvflags;
127 case 0x40: /* RESETCTL */
128 if (board_id(s) == BOARD_ID_VEXPRESS) {
129 /* reserved: RAZ/WI */
130 return 0;
132 return s->resetlevel;
133 case 0x44: /* PCICTL */
134 return 1;
135 case 0x48: /* MCI */
136 return s->sys_mci;
137 case 0x4c: /* FLASH */
138 return 0;
139 case 0x50: /* CLCD */
140 return s->sys_clcd;
141 case 0x54: /* CLCDSER */
142 return 0;
143 case 0x58: /* BOOTCS */
144 return 0;
145 case 0x5c: /* 24MHz */
146 return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
147 case 0x60: /* MISC */
148 return 0;
149 case 0x84: /* PROCID0 */
150 return s->proc_id;
151 case 0x88: /* PROCID1 */
152 return 0xff000000;
153 case 0x64: /* DMAPSR0 */
154 case 0x68: /* DMAPSR1 */
155 case 0x6c: /* DMAPSR2 */
156 case 0x70: /* IOSEL */
157 case 0x74: /* PLDCTL */
158 case 0x80: /* BUSID */
159 case 0x8c: /* OSCRESET0 */
160 case 0x90: /* OSCRESET1 */
161 case 0x94: /* OSCRESET2 */
162 case 0x98: /* OSCRESET3 */
163 case 0x9c: /* OSCRESET4 */
164 case 0xc0: /* SYS_TEST_OSC0 */
165 case 0xc4: /* SYS_TEST_OSC1 */
166 case 0xc8: /* SYS_TEST_OSC2 */
167 case 0xcc: /* SYS_TEST_OSC3 */
168 case 0xd0: /* SYS_TEST_OSC4 */
169 return 0;
170 case 0xa0: /* SYS_CFGDATA */
171 if (board_id(s) != BOARD_ID_VEXPRESS) {
172 goto bad_reg;
174 return s->sys_cfgdata;
175 case 0xa4: /* SYS_CFGCTRL */
176 if (board_id(s) != BOARD_ID_VEXPRESS) {
177 goto bad_reg;
179 return s->sys_cfgctrl;
180 case 0xa8: /* SYS_CFGSTAT */
181 if (board_id(s) != BOARD_ID_VEXPRESS) {
182 goto bad_reg;
184 return s->sys_cfgstat;
185 default:
186 bad_reg:
187 qemu_log_mask(LOG_GUEST_ERROR,
188 "arm_sysctl_read: Bad register offset 0x%x\n",
189 (int)offset);
190 return 0;
194 static void arm_sysctl_write(void *opaque, hwaddr offset,
195 uint64_t val, unsigned size)
197 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
199 switch (offset) {
200 case 0x08: /* LED */
201 s->leds = val;
202 case 0x0c: /* OSC0 */
203 case 0x10: /* OSC1 */
204 case 0x14: /* OSC2 */
205 case 0x18: /* OSC3 */
206 case 0x1c: /* OSC4 */
207 /* ??? */
208 break;
209 case 0x20: /* LOCK */
210 if (val == LOCK_VALUE)
211 s->lockval = val;
212 else
213 s->lockval = val & 0x7fff;
214 break;
215 case 0x28: /* CFGDATA1 */
216 /* ??? Need to implement this. */
217 s->cfgdata1 = val;
218 break;
219 case 0x2c: /* CFGDATA2 */
220 /* ??? Need to implement this. */
221 s->cfgdata2 = val;
222 break;
223 case 0x30: /* FLAGSSET */
224 s->flags |= val;
225 break;
226 case 0x34: /* FLAGSCLR */
227 s->flags &= ~val;
228 break;
229 case 0x38: /* NVFLAGSSET */
230 s->nvflags |= val;
231 break;
232 case 0x3c: /* NVFLAGSCLR */
233 s->nvflags &= ~val;
234 break;
235 case 0x40: /* RESETCTL */
236 switch (board_id(s)) {
237 case BOARD_ID_PB926:
238 if (s->lockval == LOCK_VALUE) {
239 s->resetlevel = val;
240 if (val & 0x100) {
241 qemu_system_reset_request();
244 break;
245 case BOARD_ID_PBX:
246 case BOARD_ID_PBA8:
247 if (s->lockval == LOCK_VALUE) {
248 s->resetlevel = val;
249 if (val & 0x04) {
250 qemu_system_reset_request();
253 break;
254 case BOARD_ID_VEXPRESS:
255 case BOARD_ID_EB:
256 default:
257 /* reserved: RAZ/WI */
258 break;
260 break;
261 case 0x44: /* PCICTL */
262 /* nothing to do. */
263 break;
264 case 0x4c: /* FLASH */
265 break;
266 case 0x50: /* CLCD */
267 switch (board_id(s)) {
268 case BOARD_ID_PB926:
269 /* On 926 bits 13:8 are R/O, bits 1:0 control
270 * the mux that defines how to interpret the PL110
271 * graphics format, and other bits are r/w but we
272 * don't implement them to do anything.
274 s->sys_clcd &= 0x3f00;
275 s->sys_clcd |= val & ~0x3f00;
276 qemu_set_irq(s->pl110_mux_ctrl, val & 3);
277 break;
278 case BOARD_ID_EB:
279 /* The EB is the same except that there is no mux since
280 * the EB has a PL111.
282 s->sys_clcd &= 0x3f00;
283 s->sys_clcd |= val & ~0x3f00;
284 break;
285 case BOARD_ID_PBA8:
286 case BOARD_ID_PBX:
287 /* On PBA8 and PBX bit 7 is r/w and all other bits
288 * are either r/o or RAZ/WI.
290 s->sys_clcd &= (1 << 7);
291 s->sys_clcd |= val & ~(1 << 7);
292 break;
293 case BOARD_ID_VEXPRESS:
294 default:
295 /* On VExpress this register is unimplemented and will RAZ/WI */
296 break;
298 case 0x54: /* CLCDSER */
299 case 0x64: /* DMAPSR0 */
300 case 0x68: /* DMAPSR1 */
301 case 0x6c: /* DMAPSR2 */
302 case 0x70: /* IOSEL */
303 case 0x74: /* PLDCTL */
304 case 0x80: /* BUSID */
305 case 0x84: /* PROCID0 */
306 case 0x88: /* PROCID1 */
307 case 0x8c: /* OSCRESET0 */
308 case 0x90: /* OSCRESET1 */
309 case 0x94: /* OSCRESET2 */
310 case 0x98: /* OSCRESET3 */
311 case 0x9c: /* OSCRESET4 */
312 break;
313 case 0xa0: /* SYS_CFGDATA */
314 if (board_id(s) != BOARD_ID_VEXPRESS) {
315 goto bad_reg;
317 s->sys_cfgdata = val;
318 return;
319 case 0xa4: /* SYS_CFGCTRL */
320 if (board_id(s) != BOARD_ID_VEXPRESS) {
321 goto bad_reg;
323 s->sys_cfgctrl = val & ~(3 << 18);
324 s->sys_cfgstat = 1; /* complete */
325 switch (s->sys_cfgctrl) {
326 case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */
327 qemu_system_shutdown_request();
328 break;
329 case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */
330 qemu_system_reset_request();
331 break;
332 default:
333 s->sys_cfgstat |= 2; /* error */
335 return;
336 case 0xa8: /* SYS_CFGSTAT */
337 if (board_id(s) != BOARD_ID_VEXPRESS) {
338 goto bad_reg;
340 s->sys_cfgstat = val & 3;
341 return;
342 default:
343 bad_reg:
344 qemu_log_mask(LOG_GUEST_ERROR,
345 "arm_sysctl_write: Bad register offset 0x%x\n",
346 (int)offset);
347 return;
351 static const MemoryRegionOps arm_sysctl_ops = {
352 .read = arm_sysctl_read,
353 .write = arm_sysctl_write,
354 .endianness = DEVICE_NATIVE_ENDIAN,
357 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
359 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
360 switch (line) {
361 case ARM_SYSCTL_GPIO_MMC_WPROT:
363 /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
364 * for all later boards it is bit 1.
366 int bit = 2;
367 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
368 bit = 4;
370 s->sys_mci &= ~bit;
371 if (level) {
372 s->sys_mci |= bit;
374 break;
376 case ARM_SYSCTL_GPIO_MMC_CARDIN:
377 s->sys_mci &= ~1;
378 if (level) {
379 s->sys_mci |= 1;
381 break;
385 static int arm_sysctl_init(SysBusDevice *dev)
387 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
389 memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
390 sysbus_init_mmio(dev, &s->iomem);
391 qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
392 qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
393 return 0;
396 static Property arm_sysctl_properties[] = {
397 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
398 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
399 DEFINE_PROP_END_OF_LIST(),
402 static void arm_sysctl_class_init(ObjectClass *klass, void *data)
404 DeviceClass *dc = DEVICE_CLASS(klass);
405 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
407 k->init = arm_sysctl_init;
408 dc->reset = arm_sysctl_reset;
409 dc->vmsd = &vmstate_arm_sysctl;
410 dc->props = arm_sysctl_properties;
413 static TypeInfo arm_sysctl_info = {
414 .name = "realview_sysctl",
415 .parent = TYPE_SYS_BUS_DEVICE,
416 .instance_size = sizeof(arm_sysctl_state),
417 .class_init = arm_sysctl_class_init,
420 static void arm_sysctl_register_types(void)
422 type_register_static(&arm_sysctl_info);
425 type_init(arm_sysctl_register_types)