configure: Default to 'cc', not 'gcc'
[qemu/pbrook.git] / hw / openrisc_pic.c
blobaaeb9a9171933849cdfb42ccb461eb44ef319156
1 /*
2 * OpenRISC Programmable Interrupt Controller support.
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "hw.h"
22 #include "cpu.h"
24 /* OpenRISC pic handler */
25 static void openrisc_pic_cpu_handler(void *opaque, int irq, int level)
27 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque;
28 int i;
29 uint32_t irq_bit = 1 << irq;
31 if (irq > 31 || irq < 0) {
32 return;
35 if (level) {
36 cpu->env.picsr |= irq_bit;
37 } else {
38 cpu->env.picsr &= ~irq_bit;
41 for (i = 0; i < 32; i++) {
42 if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) {
43 cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
44 } else {
45 cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD);
46 cpu->env.picsr &= ~(1 << i);
51 void cpu_openrisc_pic_init(OpenRISCCPU *cpu)
53 int i;
54 qemu_irq *qi;
55 qi = qemu_allocate_irqs(openrisc_pic_cpu_handler, cpu, NR_IRQS);
57 for (i = 0; i < NR_IRQS; i++) {
58 cpu->env.irq[i] = qi[i];