2 * Model of Petalogix linux reference design targeting Xilinx Spartan 3ADSP-1800
5 * Copyright (c) 2009 Edgar E. Iglesias.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
35 #include "exec-memory.h"
37 #include "microblaze_boot.h"
38 #include "microblaze_pic_cpu.h"
40 #define LMB_BRAM_SIZE (128 * 1024)
41 #define FLASH_SIZE (16 * 1024 * 1024)
43 #define BINARY_DEVICE_TREE_FILE "petalogix-s3adsp1800.dtb"
45 #define MEMORY_BASEADDR 0x90000000
46 #define FLASH_BASEADDR 0xa0000000
47 #define INTC_BASEADDR 0x81800000
48 #define TIMER_BASEADDR 0x83c00000
49 #define UARTLITE_BASEADDR 0x84000000
50 #define ETHLITE_BASEADDR 0x81000000
52 static void machine_cpu_reset(MicroBlazeCPU
*cpu
)
54 CPUMBState
*env
= &cpu
->env
;
56 env
->pvr
.regs
[10] = 0x0c000000; /* spartan 3a dsp family. */
60 petalogix_s3adsp1800_init(QEMUMachineInitArgs
*args
)
62 ram_addr_t ram_size
= args
->ram_size
;
63 const char *cpu_model
= args
->cpu_model
;
69 hwaddr ddr_base
= MEMORY_BASEADDR
;
70 MemoryRegion
*phys_lmb_bram
= g_new(MemoryRegion
, 1);
71 MemoryRegion
*phys_ram
= g_new(MemoryRegion
, 1);
72 qemu_irq irq
[32], *cpu_irq
;
73 MemoryRegion
*sysmem
= get_system_memory();
76 if (cpu_model
== NULL
) {
77 cpu_model
= "microblaze";
79 cpu
= cpu_mb_init(cpu_model
);
82 /* Attach emulated BRAM through the LMB. */
83 memory_region_init_ram(phys_lmb_bram
,
84 "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE
);
85 vmstate_register_ram_global(phys_lmb_bram
);
86 memory_region_add_subregion(sysmem
, 0x00000000, phys_lmb_bram
);
88 memory_region_init_ram(phys_ram
, "petalogix_s3adsp1800.ram", ram_size
);
89 vmstate_register_ram_global(phys_ram
);
90 memory_region_add_subregion(sysmem
, ddr_base
, phys_ram
);
92 dinfo
= drive_get(IF_PFLASH
, 0, 0);
93 pflash_cfi01_register(FLASH_BASEADDR
,
94 NULL
, "petalogix_s3adsp1800.flash", FLASH_SIZE
,
95 dinfo
? dinfo
->bdrv
: NULL
, (64 * 1024),
97 1, 0x89, 0x18, 0x0000, 0x0, 1);
99 cpu_irq
= microblaze_pic_init_cpu(env
);
100 dev
= xilinx_intc_create(INTC_BASEADDR
, cpu_irq
[0], 2);
101 for (i
= 0; i
< 32; i
++) {
102 irq
[i
] = qdev_get_gpio_in(dev
, i
);
105 sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR
, irq
[3]);
106 /* 2 timers at irq 2 @ 62 Mhz. */
107 xilinx_timer_create(TIMER_BASEADDR
, irq
[0], 0, 62 * 1000000);
108 xilinx_ethlite_create(&nd_table
[0], ETHLITE_BASEADDR
, irq
[1], 0, 0);
110 microblaze_load_kernel(cpu
, ddr_base
, ram_size
,
111 BINARY_DEVICE_TREE_FILE
, machine_cpu_reset
);
114 static QEMUMachine petalogix_s3adsp1800_machine
= {
115 .name
= "petalogix-s3adsp1800",
116 .desc
= "PetaLogix linux refdesign for xilinx Spartan 3ADSP1800",
117 .init
= petalogix_s3adsp1800_init
,
121 static void petalogix_s3adsp1800_machine_init(void)
123 qemu_register_machine(&petalogix_s3adsp1800_machine
);
126 machine_init(petalogix_s3adsp1800_machine_init
);