configure: Default to 'cc', not 'gcc'
[qemu/pbrook.git] / hw / tcx.c
blob7aee2a9bd31b5b064e311656620719e9491fec30
1 /*
2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
25 #include "console.h"
26 #include "pixel_ops.h"
27 #include "sysbus.h"
28 #include "qdev-addr.h"
30 #define MAXX 1024
31 #define MAXY 768
32 #define TCX_DAC_NREGS 16
33 #define TCX_THC_NREGS_8 0x081c
34 #define TCX_THC_NREGS_24 0x1000
35 #define TCX_TEC_NREGS 0x1000
37 typedef struct TCXState {
38 SysBusDevice busdev;
39 hwaddr addr;
40 DisplayState *ds;
41 uint8_t *vram;
42 uint32_t *vram24, *cplane;
43 MemoryRegion vram_mem;
44 MemoryRegion vram_8bit;
45 MemoryRegion vram_24bit;
46 MemoryRegion vram_cplane;
47 MemoryRegion dac;
48 MemoryRegion tec;
49 MemoryRegion thc24;
50 MemoryRegion thc8;
51 ram_addr_t vram24_offset, cplane_offset;
52 uint32_t vram_size;
53 uint32_t palette[256];
54 uint8_t r[256], g[256], b[256];
55 uint16_t width, height, depth;
56 uint8_t dac_index, dac_state;
57 } TCXState;
59 static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
60 Error **errp);
61 static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
62 Error **errp);
64 static void tcx_set_dirty(TCXState *s)
66 memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
69 static void tcx24_set_dirty(TCXState *s)
71 memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
72 memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
75 static void update_palette_entries(TCXState *s, int start, int end)
77 int i;
78 for(i = start; i < end; i++) {
79 switch(ds_get_bits_per_pixel(s->ds)) {
80 default:
81 case 8:
82 s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
83 break;
84 case 15:
85 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
86 break;
87 case 16:
88 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
89 break;
90 case 32:
91 if (is_surface_bgr(s->ds->surface))
92 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
93 else
94 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
95 break;
98 if (s->depth == 24) {
99 tcx24_set_dirty(s);
100 } else {
101 tcx_set_dirty(s);
105 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
106 const uint8_t *s, int width)
108 int x;
109 uint8_t val;
110 uint32_t *p = (uint32_t *)d;
112 for(x = 0; x < width; x++) {
113 val = *s++;
114 *p++ = s1->palette[val];
118 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
119 const uint8_t *s, int width)
121 int x;
122 uint8_t val;
123 uint16_t *p = (uint16_t *)d;
125 for(x = 0; x < width; x++) {
126 val = *s++;
127 *p++ = s1->palette[val];
131 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
132 const uint8_t *s, int width)
134 int x;
135 uint8_t val;
137 for(x = 0; x < width; x++) {
138 val = *s++;
139 *d++ = s1->palette[val];
144 XXX Could be much more optimal:
145 * detect if line/page/whole screen is in 24 bit mode
146 * if destination is also BGR, use memcpy
148 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
149 const uint8_t *s, int width,
150 const uint32_t *cplane,
151 const uint32_t *s24)
153 int x, bgr, r, g, b;
154 uint8_t val, *p8;
155 uint32_t *p = (uint32_t *)d;
156 uint32_t dval;
158 bgr = is_surface_bgr(s1->ds->surface);
159 for(x = 0; x < width; x++, s++, s24++) {
160 if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
161 // 24-bit direct, BGR order
162 p8 = (uint8_t *)s24;
163 p8++;
164 b = *p8++;
165 g = *p8++;
166 r = *p8;
167 if (bgr)
168 dval = rgb_to_pixel32bgr(r, g, b);
169 else
170 dval = rgb_to_pixel32(r, g, b);
171 } else {
172 val = *s;
173 dval = s1->palette[val];
175 *p++ = dval;
179 static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
180 ram_addr_t cpage)
182 int ret;
184 ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
185 DIRTY_MEMORY_VGA);
186 ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
187 DIRTY_MEMORY_VGA);
188 ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
189 DIRTY_MEMORY_VGA);
190 return ret;
193 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
194 ram_addr_t page_max, ram_addr_t page24,
195 ram_addr_t cpage)
197 memory_region_reset_dirty(&ts->vram_mem,
198 page_min, page_max + TARGET_PAGE_SIZE,
199 DIRTY_MEMORY_VGA);
200 memory_region_reset_dirty(&ts->vram_mem,
201 page24 + page_min * 4,
202 page24 + page_max * 4 + TARGET_PAGE_SIZE,
203 DIRTY_MEMORY_VGA);
204 memory_region_reset_dirty(&ts->vram_mem,
205 cpage + page_min * 4,
206 cpage + page_max * 4 + TARGET_PAGE_SIZE,
207 DIRTY_MEMORY_VGA);
210 /* Fixed line length 1024 allows us to do nice tricks not possible on
211 VGA... */
212 static void tcx_update_display(void *opaque)
214 TCXState *ts = opaque;
215 ram_addr_t page, page_min, page_max;
216 int y, y_start, dd, ds;
217 uint8_t *d, *s;
218 void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
220 if (ds_get_bits_per_pixel(ts->ds) == 0)
221 return;
222 page = 0;
223 y_start = -1;
224 page_min = -1;
225 page_max = 0;
226 d = ds_get_data(ts->ds);
227 s = ts->vram;
228 dd = ds_get_linesize(ts->ds);
229 ds = 1024;
231 switch (ds_get_bits_per_pixel(ts->ds)) {
232 case 32:
233 f = tcx_draw_line32;
234 break;
235 case 15:
236 case 16:
237 f = tcx_draw_line16;
238 break;
239 default:
240 case 8:
241 f = tcx_draw_line8;
242 break;
243 case 0:
244 return;
247 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
248 if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
249 DIRTY_MEMORY_VGA)) {
250 if (y_start < 0)
251 y_start = y;
252 if (page < page_min)
253 page_min = page;
254 if (page > page_max)
255 page_max = page;
256 f(ts, d, s, ts->width);
257 d += dd;
258 s += ds;
259 f(ts, d, s, ts->width);
260 d += dd;
261 s += ds;
262 f(ts, d, s, ts->width);
263 d += dd;
264 s += ds;
265 f(ts, d, s, ts->width);
266 d += dd;
267 s += ds;
268 } else {
269 if (y_start >= 0) {
270 /* flush to display */
271 dpy_gfx_update(ts->ds, 0, y_start,
272 ts->width, y - y_start);
273 y_start = -1;
275 d += dd * 4;
276 s += ds * 4;
279 if (y_start >= 0) {
280 /* flush to display */
281 dpy_gfx_update(ts->ds, 0, y_start,
282 ts->width, y - y_start);
284 /* reset modified pages */
285 if (page_max >= page_min) {
286 memory_region_reset_dirty(&ts->vram_mem,
287 page_min, page_max + TARGET_PAGE_SIZE,
288 DIRTY_MEMORY_VGA);
292 static void tcx24_update_display(void *opaque)
294 TCXState *ts = opaque;
295 ram_addr_t page, page_min, page_max, cpage, page24;
296 int y, y_start, dd, ds;
297 uint8_t *d, *s;
298 uint32_t *cptr, *s24;
300 if (ds_get_bits_per_pixel(ts->ds) != 32)
301 return;
302 page = 0;
303 page24 = ts->vram24_offset;
304 cpage = ts->cplane_offset;
305 y_start = -1;
306 page_min = -1;
307 page_max = 0;
308 d = ds_get_data(ts->ds);
309 s = ts->vram;
310 s24 = ts->vram24;
311 cptr = ts->cplane;
312 dd = ds_get_linesize(ts->ds);
313 ds = 1024;
315 for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
316 page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
317 if (check_dirty(ts, page, page24, cpage)) {
318 if (y_start < 0)
319 y_start = y;
320 if (page < page_min)
321 page_min = page;
322 if (page > page_max)
323 page_max = page;
324 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
325 d += dd;
326 s += ds;
327 cptr += ds;
328 s24 += ds;
329 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
330 d += dd;
331 s += ds;
332 cptr += ds;
333 s24 += ds;
334 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
335 d += dd;
336 s += ds;
337 cptr += ds;
338 s24 += ds;
339 tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
340 d += dd;
341 s += ds;
342 cptr += ds;
343 s24 += ds;
344 } else {
345 if (y_start >= 0) {
346 /* flush to display */
347 dpy_gfx_update(ts->ds, 0, y_start,
348 ts->width, y - y_start);
349 y_start = -1;
351 d += dd * 4;
352 s += ds * 4;
353 cptr += ds * 4;
354 s24 += ds * 4;
357 if (y_start >= 0) {
358 /* flush to display */
359 dpy_gfx_update(ts->ds, 0, y_start,
360 ts->width, y - y_start);
362 /* reset modified pages */
363 if (page_max >= page_min) {
364 reset_dirty(ts, page_min, page_max, page24, cpage);
368 static void tcx_invalidate_display(void *opaque)
370 TCXState *s = opaque;
372 tcx_set_dirty(s);
373 qemu_console_resize(s->ds, s->width, s->height);
376 static void tcx24_invalidate_display(void *opaque)
378 TCXState *s = opaque;
380 tcx_set_dirty(s);
381 tcx24_set_dirty(s);
382 qemu_console_resize(s->ds, s->width, s->height);
385 static int vmstate_tcx_post_load(void *opaque, int version_id)
387 TCXState *s = opaque;
389 update_palette_entries(s, 0, 256);
390 if (s->depth == 24) {
391 tcx24_set_dirty(s);
392 } else {
393 tcx_set_dirty(s);
396 return 0;
399 static const VMStateDescription vmstate_tcx = {
400 .name ="tcx",
401 .version_id = 4,
402 .minimum_version_id = 4,
403 .minimum_version_id_old = 4,
404 .post_load = vmstate_tcx_post_load,
405 .fields = (VMStateField []) {
406 VMSTATE_UINT16(height, TCXState),
407 VMSTATE_UINT16(width, TCXState),
408 VMSTATE_UINT16(depth, TCXState),
409 VMSTATE_BUFFER(r, TCXState),
410 VMSTATE_BUFFER(g, TCXState),
411 VMSTATE_BUFFER(b, TCXState),
412 VMSTATE_UINT8(dac_index, TCXState),
413 VMSTATE_UINT8(dac_state, TCXState),
414 VMSTATE_END_OF_LIST()
418 static void tcx_reset(DeviceState *d)
420 TCXState *s = container_of(d, TCXState, busdev.qdev);
422 /* Initialize palette */
423 memset(s->r, 0, 256);
424 memset(s->g, 0, 256);
425 memset(s->b, 0, 256);
426 s->r[255] = s->g[255] = s->b[255] = 255;
427 update_palette_entries(s, 0, 256);
428 memset(s->vram, 0, MAXX*MAXY);
429 memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
430 DIRTY_MEMORY_VGA);
431 s->dac_index = 0;
432 s->dac_state = 0;
435 static uint64_t tcx_dac_readl(void *opaque, hwaddr addr,
436 unsigned size)
438 return 0;
441 static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val,
442 unsigned size)
444 TCXState *s = opaque;
446 switch (addr) {
447 case 0:
448 s->dac_index = val >> 24;
449 s->dac_state = 0;
450 break;
451 case 4:
452 switch (s->dac_state) {
453 case 0:
454 s->r[s->dac_index] = val >> 24;
455 update_palette_entries(s, s->dac_index, s->dac_index + 1);
456 s->dac_state++;
457 break;
458 case 1:
459 s->g[s->dac_index] = val >> 24;
460 update_palette_entries(s, s->dac_index, s->dac_index + 1);
461 s->dac_state++;
462 break;
463 case 2:
464 s->b[s->dac_index] = val >> 24;
465 update_palette_entries(s, s->dac_index, s->dac_index + 1);
466 s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
467 default:
468 s->dac_state = 0;
469 break;
471 break;
472 default:
473 break;
477 static const MemoryRegionOps tcx_dac_ops = {
478 .read = tcx_dac_readl,
479 .write = tcx_dac_writel,
480 .endianness = DEVICE_NATIVE_ENDIAN,
481 .valid = {
482 .min_access_size = 4,
483 .max_access_size = 4,
487 static uint64_t dummy_readl(void *opaque, hwaddr addr,
488 unsigned size)
490 return 0;
493 static void dummy_writel(void *opaque, hwaddr addr,
494 uint64_t val, unsigned size)
498 static const MemoryRegionOps dummy_ops = {
499 .read = dummy_readl,
500 .write = dummy_writel,
501 .endianness = DEVICE_NATIVE_ENDIAN,
502 .valid = {
503 .min_access_size = 4,
504 .max_access_size = 4,
508 static int tcx_init1(SysBusDevice *dev)
510 TCXState *s = FROM_SYSBUS(TCXState, dev);
511 ram_addr_t vram_offset = 0;
512 int size;
513 uint8_t *vram_base;
515 memory_region_init_ram(&s->vram_mem, "tcx.vram",
516 s->vram_size * (1 + 4 + 4));
517 vmstate_register_ram_global(&s->vram_mem);
518 vram_base = memory_region_get_ram_ptr(&s->vram_mem);
520 /* 8-bit plane */
521 s->vram = vram_base;
522 size = s->vram_size;
523 memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
524 &s->vram_mem, vram_offset, size);
525 sysbus_init_mmio(dev, &s->vram_8bit);
526 vram_offset += size;
527 vram_base += size;
529 /* DAC */
530 memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
531 sysbus_init_mmio(dev, &s->dac);
533 /* TEC (dummy) */
534 memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
535 sysbus_init_mmio(dev, &s->tec);
536 /* THC: NetBSD writes here even with 8-bit display: dummy */
537 memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
538 TCX_THC_NREGS_24);
539 sysbus_init_mmio(dev, &s->thc24);
541 if (s->depth == 24) {
542 /* 24-bit plane */
543 size = s->vram_size * 4;
544 s->vram24 = (uint32_t *)vram_base;
545 s->vram24_offset = vram_offset;
546 memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
547 &s->vram_mem, vram_offset, size);
548 sysbus_init_mmio(dev, &s->vram_24bit);
549 vram_offset += size;
550 vram_base += size;
552 /* Control plane */
553 size = s->vram_size * 4;
554 s->cplane = (uint32_t *)vram_base;
555 s->cplane_offset = vram_offset;
556 memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
557 &s->vram_mem, vram_offset, size);
558 sysbus_init_mmio(dev, &s->vram_cplane);
560 s->ds = graphic_console_init(tcx24_update_display,
561 tcx24_invalidate_display,
562 tcx24_screen_dump, NULL, s);
563 } else {
564 /* THC 8 bit (dummy) */
565 memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
566 TCX_THC_NREGS_8);
567 sysbus_init_mmio(dev, &s->thc8);
569 s->ds = graphic_console_init(tcx_update_display,
570 tcx_invalidate_display,
571 tcx_screen_dump, NULL, s);
574 qemu_console_resize(s->ds, s->width, s->height);
575 return 0;
578 static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
579 Error **errp)
581 TCXState *s = opaque;
582 FILE *f;
583 uint8_t *d, *d1, v;
584 int ret, y, x;
586 f = fopen(filename, "wb");
587 if (!f) {
588 error_setg(errp, "failed to open file '%s': %s", filename,
589 strerror(errno));
590 return;
592 ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
593 if (ret < 0) {
594 goto write_err;
596 d1 = s->vram;
597 for(y = 0; y < s->height; y++) {
598 d = d1;
599 for(x = 0; x < s->width; x++) {
600 v = *d;
601 ret = fputc(s->r[v], f);
602 if (ret == EOF) {
603 goto write_err;
605 ret = fputc(s->g[v], f);
606 if (ret == EOF) {
607 goto write_err;
609 ret = fputc(s->b[v], f);
610 if (ret == EOF) {
611 goto write_err;
613 d++;
615 d1 += MAXX;
618 out:
619 fclose(f);
620 return;
622 write_err:
623 error_setg(errp, "failed to write to file '%s': %s", filename,
624 strerror(errno));
625 unlink(filename);
626 goto out;
629 static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
630 Error **errp)
632 TCXState *s = opaque;
633 FILE *f;
634 uint8_t *d, *d1, v;
635 uint32_t *s24, *cptr, dval;
636 int ret, y, x;
638 f = fopen(filename, "wb");
639 if (!f) {
640 error_setg(errp, "failed to open file '%s': %s", filename,
641 strerror(errno));
642 return;
644 ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
645 if (ret < 0) {
646 goto write_err;
648 d1 = s->vram;
649 s24 = s->vram24;
650 cptr = s->cplane;
651 for(y = 0; y < s->height; y++) {
652 d = d1;
653 for(x = 0; x < s->width; x++, d++, s24++) {
654 if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
655 dval = *s24 & 0x00ffffff;
656 ret = fputc((dval >> 16) & 0xff, f);
657 if (ret == EOF) {
658 goto write_err;
660 ret = fputc((dval >> 8) & 0xff, f);
661 if (ret == EOF) {
662 goto write_err;
664 ret = fputc(dval & 0xff, f);
665 if (ret == EOF) {
666 goto write_err;
668 } else {
669 v = *d;
670 ret = fputc(s->r[v], f);
671 if (ret == EOF) {
672 goto write_err;
674 ret = fputc(s->g[v], f);
675 if (ret == EOF) {
676 goto write_err;
678 ret = fputc(s->b[v], f);
679 if (ret == EOF) {
680 goto write_err;
684 d1 += MAXX;
687 out:
688 fclose(f);
689 return;
691 write_err:
692 error_setg(errp, "failed to write to file '%s': %s", filename,
693 strerror(errno));
694 unlink(filename);
695 goto out;
698 static Property tcx_properties[] = {
699 DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
700 DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
701 DEFINE_PROP_UINT16("width", TCXState, width, -1),
702 DEFINE_PROP_UINT16("height", TCXState, height, -1),
703 DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
704 DEFINE_PROP_END_OF_LIST(),
707 static void tcx_class_init(ObjectClass *klass, void *data)
709 DeviceClass *dc = DEVICE_CLASS(klass);
710 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
712 k->init = tcx_init1;
713 dc->reset = tcx_reset;
714 dc->vmsd = &vmstate_tcx;
715 dc->props = tcx_properties;
718 static TypeInfo tcx_info = {
719 .name = "SUNW,tcx",
720 .parent = TYPE_SYS_BUS_DEVICE,
721 .instance_size = sizeof(TCXState),
722 .class_init = tcx_class_init,
725 static void tcx_register_types(void)
727 type_register_static(&tcx_info);
730 type_init(tcx_register_types)