hw/pci/pci_bridge.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to dea
   8
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
  22
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26 /*
  27  * split out from pci.c
  28  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
  29  *                    VA Linux Systems Japan K.K.
  30  */
  31
  32 #include "hw/pci/pci_bridge.h"
  33 #include "hw/pci/pci_bus.h"
  34 #include "qemu/range.h"
  35
  36 /* PCI bridge subsystem vendor ID helper functions */
  37 #define PCI_SSVID_SIZEOF        8
  38 #define PCI_SSVID_SVID          4
  39 #define PCI_SSVID_SSID          6
  40
  41 int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
  42                           uint16_t svid, uint16_t ssid)
  43 {
  44     int pos;
  45     pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset, PCI_SSVID_SIZEOF);
  46     if (pos < 0) {
  47         return pos;
  48     }
  49
  50     pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
  51     pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
  52     return pos;
  53 }
  54
  55 /* Accessor function to get parent bridge device from pci bus. */
  56 PCIDevice *pci_bridge_get_device(PCIBus *bus)
  57 {
  58     return bus->parent_dev;
  59 }
  60
  61 /* Accessor function to get secondary bus from pci-to-pci bridge device */
  62 PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
  63 {
  64     return &br->sec_bus;
  65 }
  66
  67 static uint32_t pci_config_get_io_base(const PCIDevice *d,
  68                                        uint32_t base, uint32_t base_upper16)
  69 {
  70     uint32_t val;
  71
  72     val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
  73     if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
  74         val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
  75     }
  76     return val;
  77 }
  78
  79 static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
  80 {
  81     return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
  82         << 16;
  83 }
  84
  85 static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
  86                                          uint32_t base, uint32_t upper)
  87 {
  88     pcibus_t tmp;
  89     pcibus_t val;
  90
  91     tmp = (pcibus_t)pci_get_word(d->config + base);
  92     val = (tmp & PCI_PREF_RANGE_MASK) << 16;
  93     if (tmp & PCI_PREF_RANGE_TYPE_64) {
  94         val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
  95     }
  96     return val;
  97 }
  98
  99 /* accessor function to get bridge filtering base address */
 100 pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
 101 {
 102     pcibus_t base;
 103     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 104         base = pci_config_get_io_base(bridge,
 105                                       PCI_IO_BASE, PCI_IO_BASE_UPPER16);
 106     } else {
 107         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 108             base = pci_config_get_pref_base(
 109                 bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
 110         } else {
 111             base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
 112         }
 113     }
 114
 115     return base;
 116 }
 117
 118 /* accessor funciton to get bridge filtering limit */
 119 pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
 120 {
 121     pcibus_t limit;
 122     if (type & PCI_BASE_ADDRESS_SPACE_IO) {
 123         limit = pci_config_get_io_base(bridge,
 124                                       PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
 125         limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
 126     } else {
 127         if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 128             limit = pci_config_get_pref_base(
 129                 bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
 130         } else {
 131             limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
 132         }
 133         limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
 134     }
 135     return limit;
 136 }
 137
 138 static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
 139                                   uint8_t type, const char *name,
 140                                   MemoryRegion *space,
 141                                   MemoryRegion *parent_space,
 142                                   bool enabled)
 143 {
 144     pcibus_t base = pci_bridge_get_base(&bridge->dev, type);
 145     pcibus_t limit = pci_bridge_get_limit(&bridge->dev, type);
 146     /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
 147      * Apparently no way to do this with existing memory APIs. */
 148     pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
 149
 150     memory_region_init_alias(alias, name, space, base, size);
 151     memory_region_add_subregion_overlap(parent_space, base, alias, 1);
 152 }
 153
 154 static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
 155                                         MemoryRegion *alias_vga)
 156 {
 157     uint16_t brctl = pci_get_word(br->dev.config + PCI_BRIDGE_CONTROL);
 158
 159     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO],
 160                              "pci_bridge_vga_io_lo", &br->address_space_io,
 161                              QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
 162     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI],
 163                              "pci_bridge_vga_io_hi", &br->address_space_io,
 164                              QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
 165     memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM],
 166                              "pci_bridge_vga_mem", &br->address_space_mem,
 167                              QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
 168
 169     if (brctl & PCI_BRIDGE_CTL_VGA) {
 170         pci_register_vga(&br->dev, &alias_vga[QEMU_PCI_VGA_MEM],
 171                          &alias_vga[QEMU_PCI_VGA_IO_LO],
 172                          &alias_vga[QEMU_PCI_VGA_IO_HI]);
 173     }
 174 }
 175
 176 static PCIBridgeWindows *pci_bridge_region_init(PCIBridge *br)
 177 {
 178     PCIBus *parent = br->dev.bus;
 179     PCIBridgeWindows *w = g_new(PCIBridgeWindows, 1);
 180     uint16_t cmd = pci_get_word(br->dev.config + PCI_COMMAND);
 181
 182     pci_bridge_init_alias(br, &w->alias_pref_mem,
 183                           PCI_BASE_ADDRESS_MEM_PREFETCH,
 184                           "pci_bridge_pref_mem",
 185                           &br->address_space_mem,
 186                           parent->address_space_mem,
 187                           cmd & PCI_COMMAND_MEMORY);
 188     pci_bridge_init_alias(br, &w->alias_mem,
 189                           PCI_BASE_ADDRESS_SPACE_MEMORY,
 190                           "pci_bridge_mem",
 191                           &br->address_space_mem,
 192                           parent->address_space_mem,
 193                           cmd & PCI_COMMAND_MEMORY);
 194     pci_bridge_init_alias(br, &w->alias_io,
 195                           PCI_BASE_ADDRESS_SPACE_IO,
 196                           "pci_bridge_io",
 197                           &br->address_space_io,
 198                           parent->address_space_io,
 199                           cmd & PCI_COMMAND_IO);
 200
 201     pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
 202
 203     return w;
 204 }
 205
 206 static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
 207 {
 208     PCIBus *parent = br->dev.bus;
 209
 210     memory_region_del_subregion(parent->address_space_io, &w->alias_io);
 211     memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
 212     memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
 213     pci_unregister_vga(&br->dev);
 214 }
 215
 216 static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
 217 {
 218     memory_region_destroy(&w->alias_io);
 219     memory_region_destroy(&w->alias_mem);
 220     memory_region_destroy(&w->alias_pref_mem);
 221     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_IO_LO]);
 222     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_IO_HI]);
 223     memory_region_destroy(&w->alias_vga[QEMU_PCI_VGA_MEM]);
 224     g_free(w);
 225 }
 226
 227 static void pci_bridge_update_mappings(PCIBridge *br)
 228 {
 229     PCIBridgeWindows *w = br->windows;
 230
 231     /* Make updates atomic to: handle the case of one VCPU updating the bridge
 232      * while another accesses an unaffected region. */
 233     memory_region_transaction_begin();
 234     pci_bridge_region_del(br, br->windows);
 235     br->windows = pci_bridge_region_init(br);
 236     memory_region_transaction_commit();
 237     pci_bridge_region_cleanup(br, w);
 238 }
 239
 240 /* default write_config function for PCI-to-PCI bridge */
 241 void pci_bridge_write_config(PCIDevice *d,
 242                              uint32_t address, uint32_t val, int len)
 243 {
 244     PCIBridge *s = container_of(d, PCIBridge, dev);
 245     uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 246     uint16_t newctl;
 247
 248     pci_default_write_config(d, address, val, len);
 249
 250     if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
 251
 252         /* io base/limit */
 253         ranges_overlap(address, len, PCI_IO_BASE, 2) ||
 254
 255         /* memory base/limit, prefetchable base/limit and
 256            io base/limit upper 16 */
 257         ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
 258
 259         /* vga enable */
 260         ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
 261         pci_bridge_update_mappings(s);
 262     }
 263
 264     newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
 265     if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
 266         /* Trigger hot reset on 0->1 transition. */
 267         pci_bus_reset(&s->sec_bus);
 268     }
 269 }
 270
 271 void pci_bridge_disable_base_limit(PCIDevice *dev)
 272 {
 273     uint8_t *conf = dev->config;
 274
 275     pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
 276                                PCI_IO_RANGE_MASK & 0xff);
 277     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 278                                  PCI_IO_RANGE_MASK & 0xff);
 279     pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
 280                                PCI_MEMORY_RANGE_MASK & 0xffff);
 281     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 282                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 283     pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
 284                                PCI_PREF_RANGE_MASK & 0xffff);
 285     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 286                                  PCI_PREF_RANGE_MASK & 0xffff);
 287     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 288     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 289 }
 290
 291 /* reset bridge specific configuration registers */
 292 void pci_bridge_reset(DeviceState *qdev)
 293 {
 294     PCIDevice *dev = PCI_DEVICE(qdev);
 295     uint8_t *conf = dev->config;
 296
 297     conf[PCI_PRIMARY_BUS] = 0;
 298     conf[PCI_SECONDARY_BUS] = 0;
 299     conf[PCI_SUBORDINATE_BUS] = 0;
 300     conf[PCI_SEC_LATENCY_TIMER] = 0;
 301
 302     /*
 303      * the default values for base/limit registers aren't specified
 304      * in the PCI-to-PCI-bridge spec. So we don't thouch them here.
 305      * Each implementation can override it.
 306      * typical implementation does
 307      * zero base/limit registers or
 308      * disable forwarding: pci_bridge_disable_base_limit()
 309      * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
 310      * after this function.
 311      */
 312     pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
 313                                  PCI_IO_RANGE_MASK & 0xff);
 314     pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
 315                                  PCI_IO_RANGE_MASK & 0xff);
 316     pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
 317                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 318     pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
 319                                  PCI_MEMORY_RANGE_MASK & 0xffff);
 320     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
 321                                  PCI_PREF_RANGE_MASK & 0xffff);
 322     pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
 323                                  PCI_PREF_RANGE_MASK & 0xffff);
 324     pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
 325     pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
 326
 327     pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
 328 }
 329
 330 /* default qdev initialization function for PCI-to-PCI bridge */
 331 int pci_bridge_initfn(PCIDevice *dev, const char *typename)
 332 {
 333     PCIBus *parent = dev->bus;
 334     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
 335     PCIBus *sec_bus = &br->sec_bus;
 336
 337     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 338                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 339
 340     /*
 341      * TODO: We implement VGA Enable in the Bridge Control Register
 342      * therefore per the PCI to PCI bridge spec we must also implement
 343      * VGA Palette Snooping.  When done, set this bit writable:
 344      *
 345      * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
 346      *                            PCI_COMMAND_VGA_PALETTE);
 347      */
 348
 349     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
 350     dev->config[PCI_HEADER_TYPE] =
 351         (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 352         PCI_HEADER_TYPE_BRIDGE;
 353     pci_set_word(dev->config + PCI_SEC_STATUS,
 354                  PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 355
 356     /*
 357      * If we don't specify the name, the bus will be addressed as <id>.0, where
 358      * id is the device id.
 359      * Since PCI Bridge devices have a single bus each, we don't need the index:
 360      * let users address the bus using the device name.
 361      */
 362     if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
 363             br->bus_name = dev->qdev.id;
 364     }
 365
 366     qbus_create_inplace(&sec_bus->qbus, typename, &dev->qdev, br->bus_name);
 367     sec_bus->parent_dev = dev;
 368     sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
 369     sec_bus->address_space_mem = &br->address_space_mem;
 370     memory_region_init(&br->address_space_mem, "pci_bridge_pci", INT64_MAX);
 371     sec_bus->address_space_io = &br->address_space_io;
 372     memory_region_init(&br->address_space_io, "pci_bridge_io", 65536);
 373     br->windows = pci_bridge_region_init(br);
 374     QLIST_INIT(&sec_bus->child);
 375     QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
 376     return 0;
 377 }
 378
 379 /* default qdev clean up function for PCI-to-PCI bridge */
 380 void pci_bridge_exitfn(PCIDevice *pci_dev)
 381 {
 382     PCIBridge *s = DO_UPCAST(PCIBridge, dev, pci_dev);
 383     assert(QLIST_EMPTY(&s->sec_bus.child));
 384     QLIST_REMOVE(&s->sec_bus, sibling);
 385     pci_bridge_region_del(s, s->windows);
 386     pci_bridge_region_cleanup(s, s->windows);
 387     memory_region_destroy(&s->address_space_mem);
 388     memory_region_destroy(&s->address_space_io);
 389     /* qbus_free() is called automatically by qdev_free() */
 390 }
 391
 392 /*
 393  * before qdev initialization(qdev_init()), this function sets bus_name and
 394  * map_irq callback which are necessry for pci_bridge_initfn() to
 395  * initialize bus.
 396  */
 397 void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
 398                         pci_map_irq_fn map_irq)
 399 {
 400     br->map_irq = map_irq;
 401     br->bus_name = bus_name;
 402 }