hw/pci/pcie.c

   1 /*
   2  * pcie.c
   3  *
   4  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   5  *                    VA Linux Systems Japan K.K.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu-common.h"
  22 #include "hw/pci/pci_bridge.h"
  23 #include "hw/pci/pcie.h"
  24 #include "hw/pci/msix.h"
  25 #include "hw/pci/msi.h"
  26 #include "hw/pci/pci_bus.h"
  27 #include "hw/pci/pcie_regs.h"
  28 #include "qemu/range.h"
  29
  30 //#define DEBUG_PCIE
  31 #ifdef DEBUG_PCIE
  32 # define PCIE_DPRINTF(fmt, ...)                                         \
  33     fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
  34 #else
  35 # define PCIE_DPRINTF(fmt, ...) do {} while (0)
  36 #endif
  37 #define PCIE_DEV_PRINTF(dev, fmt, ...)                                  \
  38     PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
  39
  40
  41 /***************************************************************************
  42  * pci express capability helper functions
  43  */
  44 int pcie_cap_init(PCIDevice *dev, uint8_t offset, uint8_t type, uint8_t port)
  45 {
  46     int pos;
  47     uint8_t *exp_cap;
  48
  49     assert(pci_is_express(dev));
  50
  51     pos = pci_add_capability(dev, PCI_CAP_ID_EXP, offset,
  52                                  PCI_EXP_VER2_SIZEOF);
  53     if (pos < 0) {
  54         return pos;
  55     }
  56     dev->exp.exp_cap = pos;
  57     exp_cap = dev->config + pos;
  58
  59     /* capability register
  60        interrupt message number defaults to 0 */
  61     pci_set_word(exp_cap + PCI_EXP_FLAGS,
  62                  ((type << PCI_EXP_FLAGS_TYPE_SHIFT) & PCI_EXP_FLAGS_TYPE) |
  63                  PCI_EXP_FLAGS_VER2);
  64
  65     /* device capability register
  66      * table 7-12:
  67      * roll based error reporting bit must be set by all
  68      * Functions conforming to the ECN, PCI Express Base
  69      * Specification, Revision 1.1., or subsequent PCI Express Base
  70      * Specification revisions.
  71      */
  72     pci_set_long(exp_cap + PCI_EXP_DEVCAP, PCI_EXP_DEVCAP_RBER);
  73
  74     pci_set_long(exp_cap + PCI_EXP_LNKCAP,
  75                  (port << PCI_EXP_LNKCAP_PN_SHIFT) |
  76                  PCI_EXP_LNKCAP_ASPMS_0S |
  77                  PCI_EXP_LNK_MLW_1 |
  78                  PCI_EXP_LNK_LS_25);
  79
  80     pci_set_word(exp_cap + PCI_EXP_LNKSTA,
  81                  PCI_EXP_LNK_MLW_1 | PCI_EXP_LNK_LS_25);
  82
  83     pci_set_long(exp_cap + PCI_EXP_DEVCAP2,
  84                  PCI_EXP_DEVCAP2_EFF | PCI_EXP_DEVCAP2_EETLPP);
  85
  86     pci_set_word(dev->wmask + pos, PCI_EXP_DEVCTL2_EETLPPB);
  87     return pos;
  88 }
  89
  90 int pcie_endpoint_cap_init(PCIDevice *dev, uint8_t offset)
  91 {
  92     uint8_t type = PCI_EXP_TYPE_ENDPOINT;
  93
  94     /*
  95      * Windows guests will report Code 10, device cannot start, if
  96      * a regular Endpoint type is exposed on a root complex.  These
  97      * should instead be Root Complex Integrated Endpoints.
  98      */
  99     if (pci_bus_is_express(dev->bus) && pci_bus_is_root(dev->bus)) {
 100         type = PCI_EXP_TYPE_RC_END;
 101     }
 102
 103     return pcie_cap_init(dev, offset, type, 0);
 104 }
 105
 106 void pcie_cap_exit(PCIDevice *dev)
 107 {
 108     pci_del_capability(dev, PCI_CAP_ID_EXP, PCI_EXP_VER2_SIZEOF);
 109 }
 110
 111 uint8_t pcie_cap_get_type(const PCIDevice *dev)
 112 {
 113     uint32_t pos = dev->exp.exp_cap;
 114     assert(pos > 0);
 115     return (pci_get_word(dev->config + pos + PCI_EXP_FLAGS) &
 116             PCI_EXP_FLAGS_TYPE) >> PCI_EXP_FLAGS_TYPE_SHIFT;
 117 }
 118
 119 /* MSI/MSI-X */
 120 /* pci express interrupt message number */
 121 /* 7.8.2 PCI Express Capabilities Register: Interrupt Message Number */
 122 void pcie_cap_flags_set_vector(PCIDevice *dev, uint8_t vector)
 123 {
 124     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 125     assert(vector < 32);
 126     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_FLAGS, PCI_EXP_FLAGS_IRQ);
 127     pci_word_test_and_set_mask(exp_cap + PCI_EXP_FLAGS,
 128                                vector << PCI_EXP_FLAGS_IRQ_SHIFT);
 129 }
 130
 131 uint8_t pcie_cap_flags_get_vector(PCIDevice *dev)
 132 {
 133     return (pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_FLAGS) &
 134             PCI_EXP_FLAGS_IRQ) >> PCI_EXP_FLAGS_IRQ_SHIFT;
 135 }
 136
 137 void pcie_cap_deverr_init(PCIDevice *dev)
 138 {
 139     uint32_t pos = dev->exp.exp_cap;
 140     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP,
 141                                PCI_EXP_DEVCAP_RBER);
 142     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL,
 143                                PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 144                                PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 145     pci_long_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_DEVSTA,
 146                                PCI_EXP_DEVSTA_CED | PCI_EXP_DEVSTA_NFED |
 147                                PCI_EXP_DEVSTA_URD | PCI_EXP_DEVSTA_URD);
 148 }
 149
 150 void pcie_cap_deverr_reset(PCIDevice *dev)
 151 {
 152     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 153     pci_long_test_and_clear_mask(devctl,
 154                                  PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE |
 155                                  PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
 156 }
 157
 158 static void hotplug_event_update_event_status(PCIDevice *dev)
 159 {
 160     uint32_t pos = dev->exp.exp_cap;
 161     uint8_t *exp_cap = dev->config + pos;
 162     uint16_t sltctl = pci_get_word(exp_cap + PCI_EXP_SLTCTL);
 163     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 164
 165     dev->exp.hpev_notified = (sltctl & PCI_EXP_SLTCTL_HPIE) &&
 166         (sltsta & sltctl & PCI_EXP_HP_EV_SUPPORTED);
 167 }
 168
 169 static void hotplug_event_notify(PCIDevice *dev)
 170 {
 171     bool prev = dev->exp.hpev_notified;
 172
 173     hotplug_event_update_event_status(dev);
 174
 175     if (prev == dev->exp.hpev_notified) {
 176         return;
 177     }
 178
 179     /* Note: the logic above does not take into account whether interrupts
 180      * are masked. The result is that interrupt will be sent when it is
 181      * subsequently unmasked. This appears to be legal: Section 6.7.3.4:
 182      * The Port may optionally send an MSI when there are hot-plug events that
 183      * occur while interrupt generation is disabled, and interrupt generation is
 184      * subsequently enabled. */
 185     if (msix_enabled(dev)) {
 186         msix_notify(dev, pcie_cap_flags_get_vector(dev));
 187     } else if (msi_enabled(dev)) {
 188         msi_notify(dev, pcie_cap_flags_get_vector(dev));
 189     } else {
 190         qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
 191     }
 192 }
 193
 194 static void hotplug_event_clear(PCIDevice *dev)
 195 {
 196     hotplug_event_update_event_status(dev);
 197     if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
 198         qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
 199     }
 200 }
 201
 202 /*
 203  * A PCI Express Hot-Plug Event has occurred, so update slot status register
 204  * and notify OS of the event if necessary.
 205  *
 206  * 6.7.3 PCI Express Hot-Plug Events
 207  * 6.7.3.4 Software Notification of Hot-Plug Events
 208  */
 209 static void pcie_cap_slot_event(PCIDevice *dev, PCIExpressHotPlugEvent event)
 210 {
 211     /* Minor optimization: if nothing changed - no event is needed. */
 212     if (pci_word_test_and_set_mask(dev->config + dev->exp.exp_cap +
 213                                    PCI_EXP_SLTSTA, event)) {
 214         return;
 215     }
 216     hotplug_event_notify(dev);
 217 }
 218
 219 static int pcie_cap_slot_hotplug(DeviceState *qdev,
 220                                  PCIDevice *pci_dev, PCIHotplugState state)
 221 {
 222     PCIDevice *d = PCI_DEVICE(qdev);
 223     uint8_t *exp_cap = d->config + d->exp.exp_cap;
 224     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 225
 226     /* Don't send event when device is enabled during qemu machine creation:
 227      * it is present on boot, no hotplug event is necessary. We do send an
 228      * event when the device is disabled later. */
 229     if (state == PCI_COLDPLUG_ENABLED) {
 230         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 231                                    PCI_EXP_SLTSTA_PDS);
 232         return 0;
 233     }
 234
 235     PCIE_DEV_PRINTF(pci_dev, "hotplug state: %d\n", state);
 236     if (sltsta & PCI_EXP_SLTSTA_EIS) {
 237         /* the slot is electromechanically locked.
 238          * This error is propagated up to qdev and then to HMP/QMP.
 239          */
 240         return -EBUSY;
 241     }
 242
 243     /* TODO: multifunction hot-plug.
 244      * Right now, only a device of function = 0 is allowed to be
 245      * hot plugged/unplugged.
 246      */
 247     assert(PCI_FUNC(pci_dev->devfn) == 0);
 248
 249     if (state == PCI_HOTPLUG_ENABLED) {
 250         pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA,
 251                                    PCI_EXP_SLTSTA_PDS);
 252         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 253     } else {
 254         qdev_free(&pci_dev->qdev);
 255         pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 256                                      PCI_EXP_SLTSTA_PDS);
 257         pcie_cap_slot_event(d, PCI_EXP_HP_EV_PDC);
 258     }
 259     return 0;
 260 }
 261
 262 /* pci express slot for pci express root/downstream port
 263    PCI express capability slot registers */
 264 void pcie_cap_slot_init(PCIDevice *dev, uint16_t slot)
 265 {
 266     uint32_t pos = dev->exp.exp_cap;
 267
 268     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS,
 269                                PCI_EXP_FLAGS_SLOT);
 270
 271     pci_long_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCAP,
 272                                  ~PCI_EXP_SLTCAP_PSN);
 273     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCAP,
 274                                (slot << PCI_EXP_SLTCAP_PSN_SHIFT) |
 275                                PCI_EXP_SLTCAP_EIP |
 276                                PCI_EXP_SLTCAP_HPS |
 277                                PCI_EXP_SLTCAP_HPC |
 278                                PCI_EXP_SLTCAP_PIP |
 279                                PCI_EXP_SLTCAP_AIP |
 280                                PCI_EXP_SLTCAP_ABP);
 281
 282     pci_word_test_and_clear_mask(dev->config + pos + PCI_EXP_SLTCTL,
 283                                  PCI_EXP_SLTCTL_PIC |
 284                                  PCI_EXP_SLTCTL_AIC);
 285     pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_SLTCTL,
 286                                PCI_EXP_SLTCTL_PIC_OFF |
 287                                PCI_EXP_SLTCTL_AIC_OFF);
 288     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 289                                PCI_EXP_SLTCTL_PIC |
 290                                PCI_EXP_SLTCTL_AIC |
 291                                PCI_EXP_SLTCTL_HPIE |
 292                                PCI_EXP_SLTCTL_CCIE |
 293                                PCI_EXP_SLTCTL_PDCE |
 294                                PCI_EXP_SLTCTL_ABPE);
 295     /* Although reading PCI_EXP_SLTCTL_EIC returns always 0,
 296      * make the bit writable here in order to detect 1b is written.
 297      * pcie_cap_slot_write_config() test-and-clear the bit, so
 298      * this bit always returns 0 to the guest.
 299      */
 300     pci_word_test_and_set_mask(dev->wmask + pos + PCI_EXP_SLTCTL,
 301                                PCI_EXP_SLTCTL_EIC);
 302
 303     pci_word_test_and_set_mask(dev->w1cmask + pos + PCI_EXP_SLTSTA,
 304                                PCI_EXP_HP_EV_SUPPORTED);
 305
 306     dev->exp.hpev_notified = false;
 307
 308     pci_bus_hotplug(pci_bridge_get_sec_bus(DO_UPCAST(PCIBridge, dev, dev)),
 309                     pcie_cap_slot_hotplug, &dev->qdev);
 310 }
 311
 312 void pcie_cap_slot_reset(PCIDevice *dev)
 313 {
 314     uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
 315
 316     PCIE_DEV_PRINTF(dev, "reset\n");
 317
 318     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 319                                  PCI_EXP_SLTCTL_EIC |
 320                                  PCI_EXP_SLTCTL_PIC |
 321                                  PCI_EXP_SLTCTL_AIC |
 322                                  PCI_EXP_SLTCTL_HPIE |
 323                                  PCI_EXP_SLTCTL_CCIE |
 324                                  PCI_EXP_SLTCTL_PDCE |
 325                                  PCI_EXP_SLTCTL_ABPE);
 326     pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTCTL,
 327                                PCI_EXP_SLTCTL_PIC_OFF |
 328                                PCI_EXP_SLTCTL_AIC_OFF);
 329
 330     pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA,
 331                                  PCI_EXP_SLTSTA_EIS |/* on reset,
 332                                                         the lock is released */
 333                                  PCI_EXP_SLTSTA_CC |
 334                                  PCI_EXP_SLTSTA_PDC |
 335                                  PCI_EXP_SLTSTA_ABP);
 336
 337     hotplug_event_update_event_status(dev);
 338 }
 339
 340 void pcie_cap_slot_write_config(PCIDevice *dev,
 341                                 uint32_t addr, uint32_t val, int len)
 342 {
 343     uint32_t pos = dev->exp.exp_cap;
 344     uint8_t *exp_cap = dev->config + pos;
 345     uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA);
 346
 347     if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) {
 348         hotplug_event_clear(dev);
 349     }
 350
 351     if (!ranges_overlap(addr, len, pos + PCI_EXP_SLTCTL, 2)) {
 352         return;
 353     }
 354
 355     if (pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTCTL,
 356                                      PCI_EXP_SLTCTL_EIC)) {
 357         sltsta ^= PCI_EXP_SLTSTA_EIS; /* toggle PCI_EXP_SLTSTA_EIS bit */
 358         pci_set_word(exp_cap + PCI_EXP_SLTSTA, sltsta);
 359         PCIE_DEV_PRINTF(dev, "PCI_EXP_SLTCTL_EIC: "
 360                         "sltsta -> 0x%02"PRIx16"\n",
 361                         sltsta);
 362     }
 363
 364     hotplug_event_notify(dev);
 365
 366     /*
 367      * 6.7.3.2 Command Completed Events
 368      *
 369      * Software issues a command to a hot-plug capable Downstream Port by
 370      * issuing a write transaction that targets any portion of the Port’s Slot
 371      * Control register. A single write to the Slot Control register is
 372      * considered to be a single command, even if the write affects more than
 373      * one field in the Slot Control register. In response to this transaction,
 374      * the Port must carry out the requested actions and then set the
 375      * associated status field for the command completed event. */
 376
 377     /* Real hardware might take a while to complete requested command because
 378      * physical movement would be involved like locking the electromechanical
 379      * lock.  However in our case, command is completed instantaneously above,
 380      * so send a command completion event right now.
 381      */
 382     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_CCI);
 383 }
 384
 385 int pcie_cap_slot_post_load(void *opaque, int version_id)
 386 {
 387     PCIDevice *dev = opaque;
 388     hotplug_event_update_event_status(dev);
 389     return 0;
 390 }
 391
 392 void pcie_cap_slot_push_attention_button(PCIDevice *dev)
 393 {
 394     pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP);
 395 }
 396
 397 /* root control/capabilities/status. PME isn't emulated for now */
 398 void pcie_cap_root_init(PCIDevice *dev)
 399 {
 400     pci_set_word(dev->wmask + dev->exp.exp_cap + PCI_EXP_RTCTL,
 401                  PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
 402                  PCI_EXP_RTCTL_SEFEE);
 403 }
 404
 405 void pcie_cap_root_reset(PCIDevice *dev)
 406 {
 407     pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_RTCTL, 0);
 408 }
 409
 410 /* function level reset(FLR) */
 411 void pcie_cap_flr_init(PCIDevice *dev)
 412 {
 413     pci_long_test_and_set_mask(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCAP,
 414                                PCI_EXP_DEVCAP_FLR);
 415
 416     /* Although reading BCR_FLR returns always 0,
 417      * the bit is made writable here in order to detect the 1b is written
 418      * pcie_cap_flr_write_config() test-and-clear the bit, so
 419      * this bit always returns 0 to the guest.
 420      */
 421     pci_word_test_and_set_mask(dev->wmask + dev->exp.exp_cap + PCI_EXP_DEVCTL,
 422                                PCI_EXP_DEVCTL_BCR_FLR);
 423 }
 424
 425 void pcie_cap_flr_write_config(PCIDevice *dev,
 426                                uint32_t addr, uint32_t val, int len)
 427 {
 428     uint8_t *devctl = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL;
 429     if (pci_get_word(devctl) & PCI_EXP_DEVCTL_BCR_FLR) {
 430         /* Clear PCI_EXP_DEVCTL_BCR_FLR after invoking the reset handler
 431            so the handler can detect FLR by looking at this bit. */
 432         pci_device_reset(dev);
 433         pci_word_test_and_clear_mask(devctl, PCI_EXP_DEVCTL_BCR_FLR);
 434     }
 435 }
 436
 437 /* Alternative Routing-ID Interpretation (ARI) */
 438 /* ari forwarding support for down stream port */
 439 void pcie_cap_ari_init(PCIDevice *dev)
 440 {
 441     uint32_t pos = dev->exp.exp_cap;
 442     pci_long_test_and_set_mask(dev->config + pos + PCI_EXP_DEVCAP2,
 443                                PCI_EXP_DEVCAP2_ARI);
 444     pci_long_test_and_set_mask(dev->wmask + pos + PCI_EXP_DEVCTL2,
 445                                PCI_EXP_DEVCTL2_ARI);
 446 }
 447
 448 void pcie_cap_ari_reset(PCIDevice *dev)
 449 {
 450     uint8_t *devctl2 = dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2;
 451     pci_long_test_and_clear_mask(devctl2, PCI_EXP_DEVCTL2_ARI);
 452 }
 453
 454 bool pcie_cap_is_ari_enabled(const PCIDevice *dev)
 455 {
 456     if (!pci_is_express(dev)) {
 457         return false;
 458     }
 459     if (!dev->exp.exp_cap) {
 460         return false;
 461     }
 462
 463     return pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
 464         PCI_EXP_DEVCTL2_ARI;
 465 }
 466
 467 /**************************************************************************
 468  * pci express extended capability allocation functions
 469  * uint16_t ext_cap_id (16 bit)
 470  * uint8_t cap_ver (4 bit)
 471  * uint16_t cap_offset (12 bit)
 472  * uint16_t ext_cap_size
 473  */
 474
 475 static uint16_t pcie_find_capability_list(PCIDevice *dev, uint16_t cap_id,
 476                                           uint16_t *prev_p)
 477 {
 478     uint16_t prev = 0;
 479     uint16_t next;
 480     uint32_t header = pci_get_long(dev->config + PCI_CONFIG_SPACE_SIZE);
 481
 482     if (!header) {
 483         /* no extended capability */
 484         next = 0;
 485         goto out;
 486     }
 487     for (next = PCI_CONFIG_SPACE_SIZE; next;
 488          prev = next, next = PCI_EXT_CAP_NEXT(header)) {
 489
 490         assert(next >= PCI_CONFIG_SPACE_SIZE);
 491         assert(next <= PCIE_CONFIG_SPACE_SIZE - 8);
 492
 493         header = pci_get_long(dev->config + next);
 494         if (PCI_EXT_CAP_ID(header) == cap_id) {
 495             break;
 496         }
 497     }
 498
 499 out:
 500     if (prev_p) {
 501         *prev_p = prev;
 502     }
 503     return next;
 504 }
 505
 506 uint16_t pcie_find_capability(PCIDevice *dev, uint16_t cap_id)
 507 {
 508     return pcie_find_capability_list(dev, cap_id, NULL);
 509 }
 510
 511 static void pcie_ext_cap_set_next(PCIDevice *dev, uint16_t pos, uint16_t next)
 512 {
 513     uint32_t header = pci_get_long(dev->config + pos);
 514     assert(!(next & (PCI_EXT_CAP_ALIGN - 1)));
 515     header = (header & ~PCI_EXT_CAP_NEXT_MASK) |
 516         ((next << PCI_EXT_CAP_NEXT_SHIFT) & PCI_EXT_CAP_NEXT_MASK);
 517     pci_set_long(dev->config + pos, header);
 518 }
 519
 520 /*
 521  * caller must supply valid (offset, size) * such that the range shouldn't
 522  * overlap with other capability or other registers.
 523  * This function doesn't check it.
 524  */
 525 void pcie_add_capability(PCIDevice *dev,
 526                          uint16_t cap_id, uint8_t cap_ver,
 527                          uint16_t offset, uint16_t size)
 528 {
 529     uint32_t header;
 530     uint16_t next;
 531
 532     assert(offset >= PCI_CONFIG_SPACE_SIZE);
 533     assert(offset < offset + size);
 534     assert(offset + size < PCIE_CONFIG_SPACE_SIZE);
 535     assert(size >= 8);
 536     assert(pci_is_express(dev));
 537
 538     if (offset == PCI_CONFIG_SPACE_SIZE) {
 539         header = pci_get_long(dev->config + offset);
 540         next = PCI_EXT_CAP_NEXT(header);
 541     } else {
 542         uint16_t prev;
 543
 544         /* 0 is reserved cap id. use internally to find the last capability
 545            in the linked list */
 546         next = pcie_find_capability_list(dev, 0, &prev);
 547
 548         assert(prev >= PCI_CONFIG_SPACE_SIZE);
 549         assert(next == 0);
 550         pcie_ext_cap_set_next(dev, prev, offset);
 551     }
 552     pci_set_long(dev->config + offset, PCI_EXT_CAP(cap_id, cap_ver, next));
 553
 554     /* Make capability read-only by default */
 555     memset(dev->wmask + offset, 0, size);
 556     memset(dev->w1cmask + offset, 0, size);
 557     /* Check capability by default */
 558     memset(dev->cmask + offset, 0xFF, size);
 559 }
 560
 561 /**************************************************************************
 562  * pci express extended capability helper functions
 563  */
 564
 565 /* ARI */
 566 void pcie_ari_init(PCIDevice *dev, uint16_t offset, uint16_t nextfn)
 567 {
 568     pcie_add_capability(dev, PCI_EXT_CAP_ID_ARI, PCI_ARI_VER,
 569                         offset, PCI_ARI_SIZEOF);
 570     pci_set_long(dev->config + offset + PCI_ARI_CAP, PCI_ARI_CAP_NFN(nextfn));
 571 }