hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sun4m.h"
  26 #include "qemu-timer.h"
  27 #include "sysbus.h"
  28 #include "trace.h"
  29
  30 /*
  31  * Registers of hardware timer in sun4m.
  32  *
  33  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  34  * produced as NCR89C105. See
  35  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  36  *
  37  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  38  * are zero. Bit 31 is 1 when count has been reached.
  39  *
  40  * Per-CPU timers interrupt local CPU, system timer uses normal
  41  * interrupt routing.
  42  *
  43  */
  44
  45 #define MAX_CPUS 16
  46
  47 typedef struct CPUTimerState {
  48     qemu_irq irq;
  49     ptimer_state *timer;
  50     uint32_t count, counthigh, reached;
  51     /* processor only */
  52     uint32_t running;
  53     uint64_t limit;
  54 } CPUTimerState;
  55
  56 typedef struct SLAVIO_TIMERState {
  57     SysBusDevice busdev;
  58     uint32_t num_cpus;
  59     uint32_t cputimer_mode;
  60     CPUTimerState cputimer[MAX_CPUS + 1];
  61 } SLAVIO_TIMERState;
  62
  63 typedef struct TimerContext {
  64     MemoryRegion iomem;
  65     SLAVIO_TIMERState *s;
  66     unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
  67 } TimerContext;
  68
  69 #define SYS_TIMER_SIZE 0x14
  70 #define CPU_TIMER_SIZE 0x10
  71
  72 #define TIMER_LIMIT         0
  73 #define TIMER_COUNTER       1
  74 #define TIMER_COUNTER_NORST 2
  75 #define TIMER_STATUS        3
  76 #define TIMER_MODE          4
  77
  78 #define TIMER_COUNT_MASK32 0xfffffe00
  79 #define TIMER_LIMIT_MASK32 0x7fffffff
  80 #define TIMER_MAX_COUNT64  0x7ffffffffffffe00ULL
  81 #define TIMER_MAX_COUNT32  0x7ffffe00ULL
  82 #define TIMER_REACHED      0x80000000
  83 #define TIMER_PERIOD       500ULL // 500ns
  84 #define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
  85 #define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
  86
  87 static int slavio_timer_is_user(TimerContext *tc)
  88 {
  89     SLAVIO_TIMERState *s = tc->s;
  90     unsigned int timer_index = tc->timer_index;
  91
  92     return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
  93 }
  94
  95 // Update count, set irq, update expire_time
  96 // Convert from ptimer countdown units
  97 static void slavio_timer_get_out(CPUTimerState *t)
  98 {
  99     uint64_t count, limit;
 100
 101     if (t->limit == 0) { /* free-run system or processor counter */
 102         limit = TIMER_MAX_COUNT32;
 103     } else {
 104         limit = t->limit;
 105     }
 106     count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
 107
 108     trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
 109     t->count = count & TIMER_COUNT_MASK32;
 110     t->counthigh = count >> 32;
 111 }
 112
 113 // timer callback
 114 static void slavio_timer_irq(void *opaque)
 115 {
 116     TimerContext *tc = opaque;
 117     SLAVIO_TIMERState *s = tc->s;
 118     CPUTimerState *t = &s->cputimer[tc->timer_index];
 119
 120     slavio_timer_get_out(t);
 121     trace_slavio_timer_irq(t->counthigh, t->count);
 122     /* if limit is 0 (free-run), there will be no match */
 123     if (t->limit != 0) {
 124         t->reached = TIMER_REACHED;
 125     }
 126     /* there is no interrupt if user timer or free-run */
 127     if (!slavio_timer_is_user(tc) && t->limit != 0) {
 128         qemu_irq_raise(t->irq);
 129     }
 130 }
 131
 132 static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
 133                                        unsigned size)
 134 {
 135     TimerContext *tc = opaque;
 136     SLAVIO_TIMERState *s = tc->s;
 137     uint32_t saddr, ret;
 138     unsigned int timer_index = tc->timer_index;
 139     CPUTimerState *t = &s->cputimer[timer_index];
 140
 141     saddr = addr >> 2;
 142     switch (saddr) {
 143     case TIMER_LIMIT:
 144         // read limit (system counter mode) or read most signifying
 145         // part of counter (user mode)
 146         if (slavio_timer_is_user(tc)) {
 147             // read user timer MSW
 148             slavio_timer_get_out(t);
 149             ret = t->counthigh | t->reached;
 150         } else {
 151             // read limit
 152             // clear irq
 153             qemu_irq_lower(t->irq);
 154             t->reached = 0;
 155             ret = t->limit & TIMER_LIMIT_MASK32;
 156         }
 157         break;
 158     case TIMER_COUNTER:
 159         // read counter and reached bit (system mode) or read lsbits
 160         // of counter (user mode)
 161         slavio_timer_get_out(t);
 162         if (slavio_timer_is_user(tc)) { // read user timer LSW
 163             ret = t->count & TIMER_MAX_COUNT64;
 164         } else { // read limit
 165             ret = (t->count & TIMER_MAX_COUNT32) |
 166                 t->reached;
 167         }
 168         break;
 169     case TIMER_STATUS:
 170         // only available in processor counter/timer
 171         // read start/stop status
 172         if (timer_index > 0) {
 173             ret = t->running;
 174         } else {
 175             ret = 0;
 176         }
 177         break;
 178     case TIMER_MODE:
 179         // only available in system counter
 180         // read user/system mode
 181         ret = s->cputimer_mode;
 182         break;
 183     default:
 184         trace_slavio_timer_mem_readl_invalid(addr);
 185         ret = 0;
 186         break;
 187     }
 188     trace_slavio_timer_mem_readl(addr, ret);
 189     return ret;
 190 }
 191
 192 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
 193                                     uint64_t val, unsigned size)
 194 {
 195     TimerContext *tc = opaque;
 196     SLAVIO_TIMERState *s = tc->s;
 197     uint32_t saddr;
 198     unsigned int timer_index = tc->timer_index;
 199     CPUTimerState *t = &s->cputimer[timer_index];
 200
 201     trace_slavio_timer_mem_writel(addr, val);
 202     saddr = addr >> 2;
 203     switch (saddr) {
 204     case TIMER_LIMIT:
 205         if (slavio_timer_is_user(tc)) {
 206             uint64_t count;
 207
 208             // set user counter MSW, reset counter
 209             t->limit = TIMER_MAX_COUNT64;
 210             t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
 211             t->reached = 0;
 212             count = ((uint64_t)t->counthigh << 32) | t->count;
 213             trace_slavio_timer_mem_writel_limit(timer_index, count);
 214             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 215         } else {
 216             // set limit, reset counter
 217             qemu_irq_lower(t->irq);
 218             t->limit = val & TIMER_MAX_COUNT32;
 219             if (t->timer) {
 220                 if (t->limit == 0) { /* free-run */
 221                     ptimer_set_limit(t->timer,
 222                                      LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 223                 } else {
 224                     ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
 225                 }
 226             }
 227         }
 228         break;
 229     case TIMER_COUNTER:
 230         if (slavio_timer_is_user(tc)) {
 231             uint64_t count;
 232
 233             // set user counter LSW, reset counter
 234             t->limit = TIMER_MAX_COUNT64;
 235             t->count = val & TIMER_MAX_COUNT64;
 236             t->reached = 0;
 237             count = ((uint64_t)t->counthigh) << 32 | t->count;
 238             trace_slavio_timer_mem_writel_limit(timer_index, count);
 239             ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
 240         } else {
 241             trace_slavio_timer_mem_writel_counter_invalid();
 242         }
 243         break;
 244     case TIMER_COUNTER_NORST:
 245         // set limit without resetting counter
 246         t->limit = val & TIMER_MAX_COUNT32;
 247         if (t->limit == 0) { /* free-run */
 248             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
 249         } else {
 250             ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
 251         }
 252         break;
 253     case TIMER_STATUS:
 254         if (slavio_timer_is_user(tc)) {
 255             // start/stop user counter
 256             if ((val & 1) && !t->running) {
 257                 trace_slavio_timer_mem_writel_status_start(timer_index);
 258                 ptimer_run(t->timer, 0);
 259                 t->running = 1;
 260             } else if (!(val & 1) && t->running) {
 261                 trace_slavio_timer_mem_writel_status_stop(timer_index);
 262                 ptimer_stop(t->timer);
 263                 t->running = 0;
 264             }
 265         }
 266         break;
 267     case TIMER_MODE:
 268         if (timer_index == 0) {
 269             unsigned int i;
 270
 271             for (i = 0; i < s->num_cpus; i++) {
 272                 unsigned int processor = 1 << i;
 273                 CPUTimerState *curr_timer = &s->cputimer[i + 1];
 274
 275                 // check for a change in timer mode for this processor
 276                 if ((val & processor) != (s->cputimer_mode & processor)) {
 277                     if (val & processor) { // counter -> user timer
 278                         qemu_irq_lower(curr_timer->irq);
 279                         // counters are always running
 280                         ptimer_stop(curr_timer->timer);
 281                         curr_timer->running = 0;
 282                         // user timer limit is always the same
 283                         curr_timer->limit = TIMER_MAX_COUNT64;
 284                         ptimer_set_limit(curr_timer->timer,
 285                                          LIMIT_TO_PERIODS(curr_timer->limit),
 286                                          1);
 287                         // set this processors user timer bit in config
 288                         // register
 289                         s->cputimer_mode |= processor;
 290                         trace_slavio_timer_mem_writel_mode_user(timer_index);
 291                     } else { // user timer -> counter
 292                         // stop the user timer if it is running
 293                         if (curr_timer->running) {
 294                             ptimer_stop(curr_timer->timer);
 295                         }
 296                         // start the counter
 297                         ptimer_run(curr_timer->timer, 0);
 298                         curr_timer->running = 1;
 299                         // clear this processors user timer bit in config
 300                         // register
 301                         s->cputimer_mode &= ~processor;
 302                         trace_slavio_timer_mem_writel_mode_counter(timer_index);
 303                     }
 304                 }
 305             }
 306         } else {
 307             trace_slavio_timer_mem_writel_mode_invalid();
 308         }
 309         break;
 310     default:
 311         trace_slavio_timer_mem_writel_invalid(addr);
 312         break;
 313     }
 314 }
 315
 316 static const MemoryRegionOps slavio_timer_mem_ops = {
 317     .read = slavio_timer_mem_readl,
 318     .write = slavio_timer_mem_writel,
 319     .endianness = DEVICE_NATIVE_ENDIAN,
 320     .valid = {
 321         .min_access_size = 4,
 322         .max_access_size = 4,
 323     },
 324 };
 325
 326 static const VMStateDescription vmstate_timer = {
 327     .name ="timer",
 328     .version_id = 3,
 329     .minimum_version_id = 3,
 330     .minimum_version_id_old = 3,
 331     .fields      = (VMStateField []) {
 332         VMSTATE_UINT64(limit, CPUTimerState),
 333         VMSTATE_UINT32(count, CPUTimerState),
 334         VMSTATE_UINT32(counthigh, CPUTimerState),
 335         VMSTATE_UINT32(reached, CPUTimerState),
 336         VMSTATE_UINT32(running, CPUTimerState),
 337         VMSTATE_PTIMER(timer, CPUTimerState),
 338         VMSTATE_END_OF_LIST()
 339     }
 340 };
 341
 342 static const VMStateDescription vmstate_slavio_timer = {
 343     .name ="slavio_timer",
 344     .version_id = 3,
 345     .minimum_version_id = 3,
 346     .minimum_version_id_old = 3,
 347     .fields      = (VMStateField []) {
 348         VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
 349                              vmstate_timer, CPUTimerState),
 350         VMSTATE_END_OF_LIST()
 351     }
 352 };
 353
 354 static void slavio_timer_reset(DeviceState *d)
 355 {
 356     SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
 357     unsigned int i;
 358     CPUTimerState *curr_timer;
 359
 360     for (i = 0; i <= MAX_CPUS; i++) {
 361         curr_timer = &s->cputimer[i];
 362         curr_timer->limit = 0;
 363         curr_timer->count = 0;
 364         curr_timer->reached = 0;
 365         if (i <= s->num_cpus) {
 366             ptimer_set_limit(curr_timer->timer,
 367                              LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
 368             ptimer_run(curr_timer->timer, 0);
 369             curr_timer->running = 1;
 370         }
 371     }
 372     s->cputimer_mode = 0;
 373 }
 374
 375 static int slavio_timer_init1(SysBusDevice *dev)
 376 {
 377     SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
 378     QEMUBH *bh;
 379     unsigned int i;
 380     TimerContext *tc;
 381
 382     for (i = 0; i <= MAX_CPUS; i++) {
 383         uint64_t size;
 384         char timer_name[20];
 385
 386         tc = g_malloc0(sizeof(TimerContext));
 387         tc->s = s;
 388         tc->timer_index = i;
 389
 390         bh = qemu_bh_new(slavio_timer_irq, tc);
 391         s->cputimer[i].timer = ptimer_init(bh);
 392         ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
 393
 394         size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
 395         snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
 396         memory_region_init_io(&tc->iomem, &slavio_timer_mem_ops, tc,
 397                               timer_name, size);
 398         sysbus_init_mmio(dev, &tc->iomem);
 399
 400         sysbus_init_irq(dev, &s->cputimer[i].irq);
 401     }
 402
 403     return 0;
 404 }
 405
 406 static SysBusDeviceInfo slavio_timer_info = {
 407     .init = slavio_timer_init1,
 408     .qdev.name  = "slavio_timer",
 409     .qdev.size  = sizeof(SLAVIO_TIMERState),
 410     .qdev.vmsd  = &vmstate_slavio_timer,
 411     .qdev.reset = slavio_timer_reset,
 412     .qdev.props = (Property[]) {
 413         DEFINE_PROP_UINT32("num_cpus",  SLAVIO_TIMERState, num_cpus,  0),
 414         DEFINE_PROP_END_OF_LIST(),
 415     }
 416 };
 417
 418 static void slavio_timer_register_devices(void)
 419 {
 420     sysbus_register_withprop(&slavio_timer_info);
 421 }
 422
 423 device_init(slavio_timer_register_devices)