target-xtensa/cpu.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #ifndef CPU_XTENSA_H
  29 #define CPU_XTENSA_H
  30
  31 #define TARGET_LONG_BITS 32
  32 #define ELF_MACHINE EM_XTENSA
  33
  34 #define CPUArchState struct CPUXtensaState
  35
  36 #include "config.h"
  37 #include "qemu-common.h"
  38 #include "exec/cpu-defs.h"
  39 #include "fpu/softfloat.h"
  40
  41 #define TARGET_HAS_ICE 1
  42
  43 #define NB_MMU_MODES 4
  44
  45 #define TARGET_PHYS_ADDR_SPACE_BITS 32
  46 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  47 #define TARGET_PAGE_BITS 12
  48
  49 enum {
  50     /* Additional instructions */
  51     XTENSA_OPTION_CODE_DENSITY,
  52     XTENSA_OPTION_LOOP,
  53     XTENSA_OPTION_EXTENDED_L32R,
  54     XTENSA_OPTION_16_BIT_IMUL,
  55     XTENSA_OPTION_32_BIT_IMUL,
  56     XTENSA_OPTION_32_BIT_IMUL_HIGH,
  57     XTENSA_OPTION_32_BIT_IDIV,
  58     XTENSA_OPTION_MAC16,
  59     XTENSA_OPTION_MISC_OP_NSA,
  60     XTENSA_OPTION_MISC_OP_MINMAX,
  61     XTENSA_OPTION_MISC_OP_SEXT,
  62     XTENSA_OPTION_MISC_OP_CLAMPS,
  63     XTENSA_OPTION_COPROCESSOR,
  64     XTENSA_OPTION_BOOLEAN,
  65     XTENSA_OPTION_FP_COPROCESSOR,
  66     XTENSA_OPTION_MP_SYNCHRO,
  67     XTENSA_OPTION_CONDITIONAL_STORE,
  68     XTENSA_OPTION_ATOMCTL,
  69
  70     /* Interrupts and exceptions */
  71     XTENSA_OPTION_EXCEPTION,
  72     XTENSA_OPTION_RELOCATABLE_VECTOR,
  73     XTENSA_OPTION_UNALIGNED_EXCEPTION,
  74     XTENSA_OPTION_INTERRUPT,
  75     XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT,
  76     XTENSA_OPTION_TIMER_INTERRUPT,
  77
  78     /* Local memory */
  79     XTENSA_OPTION_ICACHE,
  80     XTENSA_OPTION_ICACHE_TEST,
  81     XTENSA_OPTION_ICACHE_INDEX_LOCK,
  82     XTENSA_OPTION_DCACHE,
  83     XTENSA_OPTION_DCACHE_TEST,
  84     XTENSA_OPTION_DCACHE_INDEX_LOCK,
  85     XTENSA_OPTION_IRAM,
  86     XTENSA_OPTION_IROM,
  87     XTENSA_OPTION_DRAM,
  88     XTENSA_OPTION_DROM,
  89     XTENSA_OPTION_XLMI,
  90     XTENSA_OPTION_HW_ALIGNMENT,
  91     XTENSA_OPTION_MEMORY_ECC_PARITY,
  92
  93     /* Memory protection and translation */
  94     XTENSA_OPTION_REGION_PROTECTION,
  95     XTENSA_OPTION_REGION_TRANSLATION,
  96     XTENSA_OPTION_MMU,
  97     XTENSA_OPTION_CACHEATTR,
  98
  99     /* Other */
 100     XTENSA_OPTION_WINDOWED_REGISTER,
 101     XTENSA_OPTION_PROCESSOR_INTERFACE,
 102     XTENSA_OPTION_MISC_SR,
 103     XTENSA_OPTION_THREAD_POINTER,
 104     XTENSA_OPTION_PROCESSOR_ID,
 105     XTENSA_OPTION_DEBUG,
 106     XTENSA_OPTION_TRACE_PORT,
 107 };
 108
 109 enum {
 110     THREADPTR = 231,
 111     FCR = 232,
 112     FSR = 233,
 113 };
 114
 115 enum {
 116     LBEG = 0,
 117     LEND = 1,
 118     LCOUNT = 2,
 119     SAR = 3,
 120     BR = 4,
 121     LITBASE = 5,
 122     SCOMPARE1 = 12,
 123     ACCLO = 16,
 124     ACCHI = 17,
 125     MR = 32,
 126     WINDOW_BASE = 72,
 127     WINDOW_START = 73,
 128     PTEVADDR = 83,
 129     RASID = 90,
 130     ITLBCFG = 91,
 131     DTLBCFG = 92,
 132     IBREAKENABLE = 96,
 133     CACHEATTR = 98,
 134     ATOMCTL = 99,
 135     IBREAKA = 128,
 136     DBREAKA = 144,
 137     DBREAKC = 160,
 138     EPC1 = 177,
 139     DEPC = 192,
 140     EPS2 = 194,
 141     EXCSAVE1 = 209,
 142     CPENABLE = 224,
 143     INTSET = 226,
 144     INTCLEAR = 227,
 145     INTENABLE = 228,
 146     PS = 230,
 147     VECBASE = 231,
 148     EXCCAUSE = 232,
 149     DEBUGCAUSE = 233,
 150     CCOUNT = 234,
 151     PRID = 235,
 152     ICOUNT = 236,
 153     ICOUNTLEVEL = 237,
 154     EXCVADDR = 238,
 155     CCOMPARE = 240,
 156     MISC = 244,
 157 };
 158
 159 #define PS_INTLEVEL 0xf
 160 #define PS_INTLEVEL_SHIFT 0
 161
 162 #define PS_EXCM 0x10
 163 #define PS_UM 0x20
 164
 165 #define PS_RING 0xc0
 166 #define PS_RING_SHIFT 6
 167
 168 #define PS_OWB 0xf00
 169 #define PS_OWB_SHIFT 8
 170
 171 #define PS_CALLINC 0x30000
 172 #define PS_CALLINC_SHIFT 16
 173 #define PS_CALLINC_LEN 2
 174
 175 #define PS_WOE 0x40000
 176
 177 #define DEBUGCAUSE_IC 0x1
 178 #define DEBUGCAUSE_IB 0x2
 179 #define DEBUGCAUSE_DB 0x4
 180 #define DEBUGCAUSE_BI 0x8
 181 #define DEBUGCAUSE_BN 0x10
 182 #define DEBUGCAUSE_DI 0x20
 183 #define DEBUGCAUSE_DBNUM 0xf00
 184 #define DEBUGCAUSE_DBNUM_SHIFT 8
 185
 186 #define DBREAKC_SB 0x80000000
 187 #define DBREAKC_LB 0x40000000
 188 #define DBREAKC_SB_LB (DBREAKC_SB | DBREAKC_LB)
 189 #define DBREAKC_MASK 0x3f
 190
 191 #define MAX_NAREG 64
 192 #define MAX_NINTERRUPT 32
 193 #define MAX_NLEVEL 6
 194 #define MAX_NNMI 1
 195 #define MAX_NCCOMPARE 3
 196 #define MAX_TLB_WAY_SIZE 8
 197 #define MAX_NDBREAK 2
 198
 199 #define REGION_PAGE_MASK 0xe0000000
 200
 201 #define PAGE_CACHE_MASK    0x700
 202 #define PAGE_CACHE_SHIFT   8
 203 #define PAGE_CACHE_INVALID 0x000
 204 #define PAGE_CACHE_BYPASS  0x100
 205 #define PAGE_CACHE_WT      0x200
 206 #define PAGE_CACHE_WB      0x400
 207 #define PAGE_CACHE_ISOLATE 0x600
 208
 209 enum {
 210     /* Static vectors */
 211     EXC_RESET,
 212     EXC_MEMORY_ERROR,
 213
 214     /* Dynamic vectors */
 215     EXC_WINDOW_OVERFLOW4,
 216     EXC_WINDOW_UNDERFLOW4,
 217     EXC_WINDOW_OVERFLOW8,
 218     EXC_WINDOW_UNDERFLOW8,
 219     EXC_WINDOW_OVERFLOW12,
 220     EXC_WINDOW_UNDERFLOW12,
 221     EXC_IRQ,
 222     EXC_KERNEL,
 223     EXC_USER,
 224     EXC_DOUBLE,
 225     EXC_DEBUG,
 226     EXC_MAX
 227 };
 228
 229 enum {
 230     ILLEGAL_INSTRUCTION_CAUSE = 0,
 231     SYSCALL_CAUSE,
 232     INSTRUCTION_FETCH_ERROR_CAUSE,
 233     LOAD_STORE_ERROR_CAUSE,
 234     LEVEL1_INTERRUPT_CAUSE,
 235     ALLOCA_CAUSE,
 236     INTEGER_DIVIDE_BY_ZERO_CAUSE,
 237     PRIVILEGED_CAUSE = 8,
 238     LOAD_STORE_ALIGNMENT_CAUSE,
 239
 240     INSTR_PIF_DATA_ERROR_CAUSE = 12,
 241     LOAD_STORE_PIF_DATA_ERROR_CAUSE,
 242     INSTR_PIF_ADDR_ERROR_CAUSE,
 243     LOAD_STORE_PIF_ADDR_ERROR_CAUSE,
 244
 245     INST_TLB_MISS_CAUSE,
 246     INST_TLB_MULTI_HIT_CAUSE,
 247     INST_FETCH_PRIVILEGE_CAUSE,
 248     INST_FETCH_PROHIBITED_CAUSE = 20,
 249     LOAD_STORE_TLB_MISS_CAUSE = 24,
 250     LOAD_STORE_TLB_MULTI_HIT_CAUSE,
 251     LOAD_STORE_PRIVILEGE_CAUSE,
 252     LOAD_PROHIBITED_CAUSE = 28,
 253     STORE_PROHIBITED_CAUSE,
 254
 255     COPROCESSOR0_DISABLED = 32,
 256 };
 257
 258 typedef enum {
 259     INTTYPE_LEVEL,
 260     INTTYPE_EDGE,
 261     INTTYPE_NMI,
 262     INTTYPE_SOFTWARE,
 263     INTTYPE_TIMER,
 264     INTTYPE_DEBUG,
 265     INTTYPE_WRITE_ERR,
 266     INTTYPE_MAX
 267 } interrupt_type;
 268
 269 typedef struct xtensa_tlb_entry {
 270     uint32_t vaddr;
 271     uint32_t paddr;
 272     uint8_t asid;
 273     uint8_t attr;
 274     bool variable;
 275 } xtensa_tlb_entry;
 276
 277 typedef struct xtensa_tlb {
 278     unsigned nways;
 279     const unsigned way_size[10];
 280     bool varway56;
 281     unsigned nrefillentries;
 282 } xtensa_tlb;
 283
 284 typedef struct XtensaGdbReg {
 285     int targno;
 286     int type;
 287     int group;
 288 } XtensaGdbReg;
 289
 290 typedef struct XtensaGdbRegmap {
 291     int num_regs;
 292     int num_core_regs;
 293     /* PC + a + ar + sr + ur */
 294     XtensaGdbReg reg[1 + 16 + 64 + 256 + 256];
 295 } XtensaGdbRegmap;
 296
 297 typedef struct XtensaConfig {
 298     const char *name;
 299     uint64_t options;
 300     XtensaGdbRegmap gdb_regmap;
 301     unsigned nareg;
 302     int excm_level;
 303     int ndepc;
 304     uint32_t vecbase;
 305     uint32_t exception_vector[EXC_MAX];
 306     unsigned ninterrupt;
 307     unsigned nlevel;
 308     uint32_t interrupt_vector[MAX_NLEVEL + MAX_NNMI + 1];
 309     uint32_t level_mask[MAX_NLEVEL + MAX_NNMI + 1];
 310     uint32_t inttype_mask[INTTYPE_MAX];
 311     struct {
 312         uint32_t level;
 313         interrupt_type inttype;
 314     } interrupt[MAX_NINTERRUPT];
 315     unsigned nccompare;
 316     uint32_t timerint[MAX_NCCOMPARE];
 317     unsigned nextint;
 318     unsigned extint[MAX_NINTERRUPT];
 319
 320     unsigned debug_level;
 321     unsigned nibreak;
 322     unsigned ndbreak;
 323
 324     uint32_t clock_freq_khz;
 325
 326     xtensa_tlb itlb;
 327     xtensa_tlb dtlb;
 328 } XtensaConfig;
 329
 330 typedef struct XtensaConfigList {
 331     const XtensaConfig *config;
 332     struct XtensaConfigList *next;
 333 } XtensaConfigList;
 334
 335 typedef struct CPUXtensaState {
 336     const XtensaConfig *config;
 337     uint32_t regs[16];
 338     uint32_t pc;
 339     uint32_t sregs[256];
 340     uint32_t uregs[256];
 341     uint32_t phys_regs[MAX_NAREG];
 342     float32 fregs[16];
 343     float_status fp_status;
 344
 345     xtensa_tlb_entry itlb[7][MAX_TLB_WAY_SIZE];
 346     xtensa_tlb_entry dtlb[10][MAX_TLB_WAY_SIZE];
 347     unsigned autorefill_idx;
 348
 349     int pending_irq_level; /* level of last raised IRQ */
 350     void **irq_inputs;
 351     QEMUTimer *ccompare_timer;
 352     uint32_t wake_ccount;
 353     int64_t halt_clock;
 354
 355     int exception_taken;
 356
 357     /* Watchpoints for DBREAK registers */
 358     CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
 359
 360     CPU_COMMON
 361 } CPUXtensaState;
 362
 363 #include "cpu-qom.h"
 364
 365 #define cpu_exec cpu_xtensa_exec
 366 #define cpu_gen_code cpu_xtensa_gen_code
 367 #define cpu_signal_handler cpu_xtensa_signal_handler
 368 #define cpu_list xtensa_cpu_list
 369
 370 #ifdef TARGET_WORDS_BIGENDIAN
 371 #define XTENSA_DEFAULT_CPU_MODEL "fsf"
 372 #else
 373 #define XTENSA_DEFAULT_CPU_MODEL "dc232b"
 374 #endif
 375
 376 XtensaCPU *cpu_xtensa_init(const char *cpu_model);
 377
 378 static inline CPUXtensaState *cpu_init(const char *cpu_model)
 379 {
 380     XtensaCPU *cpu = cpu_xtensa_init(cpu_model);
 381     if (cpu == NULL) {
 382         return NULL;
 383     }
 384     return &cpu->env;
 385 }
 386
 387 void xtensa_translate_init(void);
 388 void xtensa_breakpoint_handler(CPUXtensaState *env);
 389 int cpu_xtensa_exec(CPUXtensaState *s);
 390 void xtensa_register_core(XtensaConfigList *node);
 391 void check_interrupts(CPUXtensaState *s);
 392 void xtensa_irq_init(CPUXtensaState *env);
 393 void *xtensa_get_extint(CPUXtensaState *env, unsigned extint);
 394 void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d);
 395 void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active);
 396 void xtensa_rearm_ccompare_timer(CPUXtensaState *env);
 397 int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc);
 398 void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 399 void xtensa_sync_window_from_phys(CPUXtensaState *env);
 400 void xtensa_sync_phys_from_window(CPUXtensaState *env);
 401 uint32_t xtensa_tlb_get_addr_mask(const CPUXtensaState *env, bool dtlb, uint32_t way);
 402 void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, bool dtlb,
 403         uint32_t *vpn, uint32_t wi, uint32_t *ei);
 404 int xtensa_tlb_lookup(const CPUXtensaState *env, uint32_t addr, bool dtlb,
 405         uint32_t *pwi, uint32_t *pei, uint8_t *pring);
 406 void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
 407         xtensa_tlb_entry *entry, bool dtlb,
 408         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 409 void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
 410         unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte);
 411 int xtensa_get_physical_addr(CPUXtensaState *env, bool update_tlb,
 412         uint32_t vaddr, int is_write, int mmu_idx,
 413         uint32_t *paddr, uint32_t *page_size, unsigned *access);
 414 void reset_mmu(CPUXtensaState *env);
 415 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUXtensaState *env);
 416 void debug_exception_env(CPUXtensaState *new_env, uint32_t cause);
 417
 418
 419 #define XTENSA_OPTION_BIT(opt) (((uint64_t)1) << (opt))
 420 #define XTENSA_OPTION_ALL (~(uint64_t)0)
 421
 422 static inline bool xtensa_option_bits_enabled(const XtensaConfig *config,
 423         uint64_t opt)
 424 {
 425     return (config->options & opt) != 0;
 426 }
 427
 428 static inline bool xtensa_option_enabled(const XtensaConfig *config, int opt)
 429 {
 430     return xtensa_option_bits_enabled(config, XTENSA_OPTION_BIT(opt));
 431 }
 432
 433 static inline int xtensa_get_cintlevel(const CPUXtensaState *env)
 434 {
 435     int level = (env->sregs[PS] & PS_INTLEVEL) >> PS_INTLEVEL_SHIFT;
 436     if ((env->sregs[PS] & PS_EXCM) && env->config->excm_level > level) {
 437         level = env->config->excm_level;
 438     }
 439     return level;
 440 }
 441
 442 static inline int xtensa_get_ring(const CPUXtensaState *env)
 443 {
 444     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
 445         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 446     } else {
 447         return 0;
 448     }
 449 }
 450
 451 static inline int xtensa_get_cring(const CPUXtensaState *env)
 452 {
 453     if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU) &&
 454             (env->sregs[PS] & PS_EXCM) == 0) {
 455         return (env->sregs[PS] & PS_RING) >> PS_RING_SHIFT;
 456     } else {
 457         return 0;
 458     }
 459 }
 460
 461 static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
 462         bool dtlb, unsigned wi, unsigned ei)
 463 {
 464     return dtlb ?
 465         env->dtlb[wi] + ei :
 466         env->itlb[wi] + ei;
 467 }
 468
 469 /* MMU modes definitions */
 470 #define MMU_MODE0_SUFFIX _ring0
 471 #define MMU_MODE1_SUFFIX _ring1
 472 #define MMU_MODE2_SUFFIX _ring2
 473 #define MMU_MODE3_SUFFIX _ring3
 474
 475 static inline int cpu_mmu_index(CPUXtensaState *env)
 476 {
 477     return xtensa_get_cring(env);
 478 }
 479
 480 #define XTENSA_TBFLAG_RING_MASK 0x3
 481 #define XTENSA_TBFLAG_EXCM 0x4
 482 #define XTENSA_TBFLAG_LITBASE 0x8
 483 #define XTENSA_TBFLAG_DEBUG 0x10
 484 #define XTENSA_TBFLAG_ICOUNT 0x20
 485 #define XTENSA_TBFLAG_CPENABLE_MASK 0x3fc0
 486 #define XTENSA_TBFLAG_CPENABLE_SHIFT 6
 487 #define XTENSA_TBFLAG_EXCEPTION 0x4000
 488
 489 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
 490         target_ulong *cs_base, int *flags)
 491 {
 492     *pc = env->pc;
 493     *cs_base = 0;
 494     *flags = 0;
 495     *flags |= xtensa_get_ring(env);
 496     if (env->sregs[PS] & PS_EXCM) {
 497         *flags |= XTENSA_TBFLAG_EXCM;
 498     }
 499     if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
 500             (env->sregs[LITBASE] & 1)) {
 501         *flags |= XTENSA_TBFLAG_LITBASE;
 502     }
 503     if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
 504         if (xtensa_get_cintlevel(env) < env->config->debug_level) {
 505             *flags |= XTENSA_TBFLAG_DEBUG;
 506         }
 507         if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
 508             *flags |= XTENSA_TBFLAG_ICOUNT;
 509         }
 510     }
 511     if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
 512         *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
 513     }
 514     if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) {
 515         *flags |= XTENSA_TBFLAG_EXCEPTION;
 516     }
 517 }
 518
 519 #include "exec/cpu-all.h"
 520 #include "exec/exec-all.h"
 521
 522 static inline int cpu_has_work(CPUState *cpu)
 523 {
 524     CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
 525
 526     return env->pending_irq_level;
 527 }
 528
 529 #endif