2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Gerd Hoffmann <kraxel@redhat.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-timer.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
28 /* --------------------------------------------------------------------- */
31 static struct BusInfo hda_codec_bus_info
= {
33 .size
= sizeof(HDACodecBus
),
34 .props
= (Property
[]) {
35 DEFINE_PROP_UINT32("cad", HDACodecDevice
, cad
, -1),
36 DEFINE_PROP_END_OF_LIST()
40 void hda_codec_bus_init(DeviceState
*dev
, HDACodecBus
*bus
,
41 hda_codec_response_func response
,
42 hda_codec_xfer_func xfer
)
44 qbus_create_inplace(&bus
->qbus
, &hda_codec_bus_info
, dev
, NULL
);
45 bus
->response
= response
;
49 static int hda_codec_dev_init(DeviceState
*qdev
, DeviceInfo
*base
)
51 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, qdev
->parent_bus
);
52 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
53 HDACodecDeviceInfo
*info
= DO_UPCAST(HDACodecDeviceInfo
, qdev
, base
);
57 dev
->cad
= bus
->next_cad
;
62 bus
->next_cad
= dev
->cad
+ 1;
63 return info
->init(dev
);
66 static int hda_codec_dev_exit(DeviceState
*qdev
)
68 HDACodecDevice
*dev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
70 if (dev
->info
->exit
) {
76 void hda_codec_register(HDACodecDeviceInfo
*info
)
78 info
->qdev
.init
= hda_codec_dev_init
;
79 info
->qdev
.exit
= hda_codec_dev_exit
;
80 info
->qdev
.bus_info
= &hda_codec_bus_info
;
81 qdev_register(&info
->qdev
);
84 HDACodecDevice
*hda_codec_find(HDACodecBus
*bus
, uint32_t cad
)
89 QLIST_FOREACH(qdev
, &bus
->qbus
.children
, sibling
) {
90 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
91 if (cdev
->cad
== cad
) {
98 void hda_codec_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
100 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
101 bus
->response(dev
, solicited
, response
);
104 bool hda_codec_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
105 uint8_t *buf
, uint32_t len
)
107 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
108 return bus
->xfer(dev
, stnr
, output
, buf
, len
);
111 /* --------------------------------------------------------------------- */
112 /* intel hda emulation */
114 typedef struct IntelHDAStream IntelHDAStream
;
115 typedef struct IntelHDAState IntelHDAState
;
116 typedef struct IntelHDAReg IntelHDAReg
;
124 struct IntelHDAStream
{
137 uint32_t bsize
, be
, bp
;
140 struct IntelHDAState
{
177 IntelHDAStream st
[8];
182 int64_t wall_base_ns
;
185 const IntelHDAReg
*last_reg
;
189 uint32_t repeat_count
;
197 const char *name
; /* register name */
198 uint32_t size
; /* size in bytes */
199 uint32_t reset
; /* reset value */
200 uint32_t wmask
; /* write mask */
201 uint32_t wclear
; /* write 1 to clear bits */
202 uint32_t offset
; /* location in IntelHDAState */
203 uint32_t shift
; /* byte access entries for dwords */
205 void (*whandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
);
206 void (*rhandler
)(IntelHDAState
*d
, const IntelHDAReg
*reg
);
209 static void intel_hda_reset(DeviceState
*dev
);
211 /* --------------------------------------------------------------------- */
213 static target_phys_addr_t
intel_hda_addr(uint32_t lbase
, uint32_t ubase
)
215 target_phys_addr_t addr
;
217 #if TARGET_PHYS_ADDR_BITS == 32
227 static void intel_hda_update_int_sts(IntelHDAState
*d
)
232 /* update controller status */
233 if (d
->rirb_sts
& ICH6_RBSTS_IRQ
) {
236 if (d
->rirb_sts
& ICH6_RBSTS_OVERRUN
) {
239 if (d
->state_sts
& d
->wake_en
) {
243 /* update stream status */
244 for (i
= 0; i
< 8; i
++) {
245 /* buffer completion interrupt */
246 if (d
->st
[i
].ctl
& (1 << 26)) {
251 /* update global status */
252 if (sts
& d
->int_ctl
) {
259 static void intel_hda_update_irq(IntelHDAState
*d
)
261 int msi
= d
->msi
&& msi_enabled(&d
->pci
);
264 intel_hda_update_int_sts(d
);
265 if (d
->int_sts
& (1 << 31) && d
->int_ctl
& (1 << 31)) {
270 dprint(d
, 2, "%s: level %d [%s]\n", __FUNCTION__
,
271 level
, msi
? "msi" : "intx");
274 msi_notify(&d
->pci
, 0);
277 qemu_set_irq(d
->pci
.irq
[0], level
);
281 static int intel_hda_send_command(IntelHDAState
*d
, uint32_t verb
)
283 uint32_t cad
, nid
, data
;
284 HDACodecDevice
*codec
;
286 cad
= (verb
>> 28) & 0x0f;
287 if (verb
& (1 << 27)) {
288 /* indirect node addressing, not specified in HDA 1.0 */
289 dprint(d
, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__
);
292 nid
= (verb
>> 20) & 0x7f;
293 data
= verb
& 0xfffff;
295 codec
= hda_codec_find(&d
->codecs
, cad
);
297 dprint(d
, 1, "%s: addressed non-existing codec\n", __FUNCTION__
);
300 codec
->info
->command(codec
, nid
, data
);
304 static void intel_hda_corb_run(IntelHDAState
*d
)
306 target_phys_addr_t addr
;
309 if (d
->ics
& ICH6_IRS_BUSY
) {
310 dprint(d
, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__
, d
->icw
);
311 intel_hda_send_command(d
, d
->icw
);
316 if (!(d
->corb_ctl
& ICH6_CORBCTL_RUN
)) {
317 dprint(d
, 2, "%s: !run\n", __FUNCTION__
);
320 if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
321 dprint(d
, 2, "%s: corb ring empty\n", __FUNCTION__
);
324 if (d
->rirb_count
== d
->rirb_cnt
) {
325 dprint(d
, 2, "%s: rirb count reached\n", __FUNCTION__
);
329 rp
= (d
->corb_rp
+ 1) & 0xff;
330 addr
= intel_hda_addr(d
->corb_lbase
, d
->corb_ubase
);
331 verb
= ldl_le_phys(addr
+ 4*rp
);
334 dprint(d
, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__
, rp
, verb
);
335 intel_hda_send_command(d
, verb
);
339 static void intel_hda_response(HDACodecDevice
*dev
, bool solicited
, uint32_t response
)
341 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
342 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
343 target_phys_addr_t addr
;
346 if (d
->ics
& ICH6_IRS_BUSY
) {
347 dprint(d
, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
348 __FUNCTION__
, response
, dev
->cad
);
350 d
->ics
&= ~(ICH6_IRS_BUSY
| 0xf0);
351 d
->ics
|= (ICH6_IRS_VALID
| (dev
->cad
<< 4));
355 if (!(d
->rirb_ctl
& ICH6_RBCTL_DMA_EN
)) {
356 dprint(d
, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__
);
360 ex
= (solicited
? 0 : (1 << 4)) | dev
->cad
;
361 wp
= (d
->rirb_wp
+ 1) & 0xff;
362 addr
= intel_hda_addr(d
->rirb_lbase
, d
->rirb_ubase
);
363 stl_le_phys(addr
+ 8*wp
, response
);
364 stl_le_phys(addr
+ 8*wp
+ 4, ex
);
367 dprint(d
, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
368 __FUNCTION__
, wp
, response
, ex
);
371 if (d
->rirb_count
== d
->rirb_cnt
) {
372 dprint(d
, 2, "%s: rirb count reached (%d)\n", __FUNCTION__
, d
->rirb_count
);
373 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
374 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
375 intel_hda_update_irq(d
);
377 } else if ((d
->corb_rp
& 0xff) == d
->corb_wp
) {
378 dprint(d
, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__
,
379 d
->rirb_count
, d
->rirb_cnt
);
380 if (d
->rirb_ctl
& ICH6_RBCTL_IRQ_EN
) {
381 d
->rirb_sts
|= ICH6_RBSTS_IRQ
;
382 intel_hda_update_irq(d
);
387 static bool intel_hda_xfer(HDACodecDevice
*dev
, uint32_t stnr
, bool output
,
388 uint8_t *buf
, uint32_t len
)
390 HDACodecBus
*bus
= DO_UPCAST(HDACodecBus
, qbus
, dev
->qdev
.parent_bus
);
391 IntelHDAState
*d
= container_of(bus
, IntelHDAState
, codecs
);
392 IntelHDAStream
*st
= NULL
;
393 target_phys_addr_t addr
;
394 uint32_t s
, copy
, left
;
397 for (s
= 0; s
< ARRAY_SIZE(d
->st
); s
++) {
398 if (stnr
== ((d
->st
[s
].ctl
>> 20) & 0x0f)) {
406 if (st
->bpl
== NULL
) {
409 if (st
->ctl
& (1 << 26)) {
411 * Wait with the next DMA xfer until the guest
412 * has acked the buffer completion interrupt
420 if (copy
> st
->bsize
- st
->lpib
)
421 copy
= st
->bsize
- st
->lpib
;
422 if (copy
> st
->bpl
[st
->be
].len
- st
->bp
)
423 copy
= st
->bpl
[st
->be
].len
- st
->bp
;
425 dprint(d
, 3, "dma: entry %d, pos %d/%d, copy %d\n",
426 st
->be
, st
->bp
, st
->bpl
[st
->be
].len
, copy
);
428 cpu_physical_memory_rw(st
->bpl
[st
->be
].addr
+ st
->bp
,
435 if (st
->bpl
[st
->be
].len
== st
->bp
) {
436 /* bpl entry filled */
437 if (st
->bpl
[st
->be
].flags
& 0x01) {
442 if (st
->be
== st
->bentries
) {
443 /* bpl wrap around */
449 if (d
->dp_lbase
& 0x01) {
450 addr
= intel_hda_addr(d
->dp_lbase
& ~0x01, d
->dp_ubase
);
451 stl_le_phys(addr
+ 8*s
, st
->lpib
);
453 dprint(d
, 3, "dma: --\n");
456 st
->ctl
|= (1 << 26); /* buffer completion interrupt */
457 intel_hda_update_irq(d
);
462 static void intel_hda_parse_bdl(IntelHDAState
*d
, IntelHDAStream
*st
)
464 target_phys_addr_t addr
;
468 addr
= intel_hda_addr(st
->bdlp_lbase
, st
->bdlp_ubase
);
469 st
->bentries
= st
->lvi
+1;
471 st
->bpl
= qemu_malloc(sizeof(bpl
) * st
->bentries
);
472 for (i
= 0; i
< st
->bentries
; i
++, addr
+= 16) {
473 cpu_physical_memory_read(addr
, buf
, 16);
474 st
->bpl
[i
].addr
= le64_to_cpu(*(uint64_t *)buf
);
475 st
->bpl
[i
].len
= le32_to_cpu(*(uint32_t *)(buf
+ 8));
476 st
->bpl
[i
].flags
= le32_to_cpu(*(uint32_t *)(buf
+ 12));
477 dprint(d
, 1, "bdl/%d: 0x%" PRIx64
" +0x%x, 0x%x\n",
478 i
, st
->bpl
[i
].addr
, st
->bpl
[i
].len
, st
->bpl
[i
].flags
);
487 static void intel_hda_notify_codecs(IntelHDAState
*d
, uint32_t stream
, bool running
)
490 HDACodecDevice
*cdev
;
492 QLIST_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
493 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
494 if (cdev
->info
->stream
) {
495 cdev
->info
->stream(cdev
, stream
, running
);
500 /* --------------------------------------------------------------------- */
502 static void intel_hda_set_g_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
504 if ((d
->g_ctl
& ICH6_GCTL_RESET
) == 0) {
505 intel_hda_reset(&d
->pci
.qdev
);
509 static void intel_hda_set_wake_en(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
511 intel_hda_update_irq(d
);
514 static void intel_hda_set_state_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
516 intel_hda_update_irq(d
);
519 static void intel_hda_set_int_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
521 intel_hda_update_irq(d
);
524 static void intel_hda_get_wall_clk(IntelHDAState
*d
, const IntelHDAReg
*reg
)
528 ns
= qemu_get_clock_ns(vm_clock
) - d
->wall_base_ns
;
529 d
->wall_clk
= (uint32_t)(ns
* 24 / 1000); /* 24 MHz */
532 static void intel_hda_set_corb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
534 intel_hda_corb_run(d
);
537 static void intel_hda_set_corb_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
539 intel_hda_corb_run(d
);
542 static void intel_hda_set_rirb_wp(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
544 if (d
->rirb_wp
& ICH6_RIRBWP_RST
) {
549 static void intel_hda_set_rirb_sts(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
551 intel_hda_update_irq(d
);
553 if ((old
& ICH6_RBSTS_IRQ
) && !(d
->rirb_sts
& ICH6_RBSTS_IRQ
)) {
554 /* cleared ICH6_RBSTS_IRQ */
556 intel_hda_corb_run(d
);
560 static void intel_hda_set_ics(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
562 if (d
->ics
& ICH6_IRS_BUSY
) {
563 intel_hda_corb_run(d
);
567 static void intel_hda_set_st_ctl(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t old
)
569 IntelHDAStream
*st
= d
->st
+ reg
->stream
;
571 if (st
->ctl
& 0x01) {
573 dprint(d
, 1, "st #%d: reset\n", reg
->stream
);
576 if ((st
->ctl
& 0x02) != (old
& 0x02)) {
577 uint32_t stnr
= (st
->ctl
>> 20) & 0x0f;
578 /* run bit flipped */
579 if (st
->ctl
& 0x02) {
581 dprint(d
, 1, "st #%d: start %d (ring buf %d bytes)\n",
582 reg
->stream
, stnr
, st
->cbl
);
583 intel_hda_parse_bdl(d
, st
);
584 intel_hda_notify_codecs(d
, stnr
, true);
587 dprint(d
, 1, "st #%d: stop %d\n", reg
->stream
, stnr
);
588 intel_hda_notify_codecs(d
, stnr
, false);
591 intel_hda_update_irq(d
);
594 /* --------------------------------------------------------------------- */
596 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
598 static const struct IntelHDAReg regtab
[] = {
600 [ ICH6_REG_GCAP
] = {
605 [ ICH6_REG_VMIN
] = {
609 [ ICH6_REG_VMAJ
] = {
614 [ ICH6_REG_OUTPAY
] = {
619 [ ICH6_REG_INPAY
] = {
624 [ ICH6_REG_GCTL
] = {
628 .offset
= offsetof(IntelHDAState
, g_ctl
),
629 .whandler
= intel_hda_set_g_ctl
,
631 [ ICH6_REG_WAKEEN
] = {
635 .offset
= offsetof(IntelHDAState
, wake_en
),
636 .whandler
= intel_hda_set_wake_en
,
638 [ ICH6_REG_STATESTS
] = {
643 .offset
= offsetof(IntelHDAState
, state_sts
),
644 .whandler
= intel_hda_set_state_sts
,
648 [ ICH6_REG_INTCTL
] = {
652 .offset
= offsetof(IntelHDAState
, int_ctl
),
653 .whandler
= intel_hda_set_int_ctl
,
655 [ ICH6_REG_INTSTS
] = {
659 .wclear
= 0xc00000ff,
660 .offset
= offsetof(IntelHDAState
, int_sts
),
664 [ ICH6_REG_WALLCLK
] = {
667 .offset
= offsetof(IntelHDAState
, wall_clk
),
668 .rhandler
= intel_hda_get_wall_clk
,
670 [ ICH6_REG_WALLCLK
+ 0x2000 ] = {
671 .name
= "WALLCLK(alias)",
673 .offset
= offsetof(IntelHDAState
, wall_clk
),
674 .rhandler
= intel_hda_get_wall_clk
,
678 [ ICH6_REG_CORBLBASE
] = {
682 .offset
= offsetof(IntelHDAState
, corb_lbase
),
684 [ ICH6_REG_CORBUBASE
] = {
688 .offset
= offsetof(IntelHDAState
, corb_ubase
),
690 [ ICH6_REG_CORBWP
] = {
694 .offset
= offsetof(IntelHDAState
, corb_wp
),
695 .whandler
= intel_hda_set_corb_wp
,
697 [ ICH6_REG_CORBRP
] = {
701 .offset
= offsetof(IntelHDAState
, corb_rp
),
703 [ ICH6_REG_CORBCTL
] = {
707 .offset
= offsetof(IntelHDAState
, corb_ctl
),
708 .whandler
= intel_hda_set_corb_ctl
,
710 [ ICH6_REG_CORBSTS
] = {
715 .offset
= offsetof(IntelHDAState
, corb_sts
),
717 [ ICH6_REG_CORBSIZE
] = {
721 .offset
= offsetof(IntelHDAState
, corb_size
),
723 [ ICH6_REG_RIRBLBASE
] = {
727 .offset
= offsetof(IntelHDAState
, rirb_lbase
),
729 [ ICH6_REG_RIRBUBASE
] = {
733 .offset
= offsetof(IntelHDAState
, rirb_ubase
),
735 [ ICH6_REG_RIRBWP
] = {
739 .offset
= offsetof(IntelHDAState
, rirb_wp
),
740 .whandler
= intel_hda_set_rirb_wp
,
742 [ ICH6_REG_RINTCNT
] = {
746 .offset
= offsetof(IntelHDAState
, rirb_cnt
),
748 [ ICH6_REG_RIRBCTL
] = {
752 .offset
= offsetof(IntelHDAState
, rirb_ctl
),
754 [ ICH6_REG_RIRBSTS
] = {
759 .offset
= offsetof(IntelHDAState
, rirb_sts
),
760 .whandler
= intel_hda_set_rirb_sts
,
762 [ ICH6_REG_RIRBSIZE
] = {
766 .offset
= offsetof(IntelHDAState
, rirb_size
),
769 [ ICH6_REG_DPLBASE
] = {
773 .offset
= offsetof(IntelHDAState
, dp_lbase
),
775 [ ICH6_REG_DPUBASE
] = {
779 .offset
= offsetof(IntelHDAState
, dp_ubase
),
786 .offset
= offsetof(IntelHDAState
, icw
),
791 .offset
= offsetof(IntelHDAState
, irr
),
798 .offset
= offsetof(IntelHDAState
, ics
),
799 .whandler
= intel_hda_set_ics
,
802 #define HDA_STREAM(_t, _i) \
803 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
805 .name = _t stringify(_i) " CTL", \
807 .wmask = 0x1cff001f, \
808 .offset = offsetof(IntelHDAState, st[_i].ctl), \
809 .whandler = intel_hda_set_st_ctl, \
811 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
813 .name = _t stringify(_i) " CTL(stnr)", \
816 .wmask = 0x00ff0000, \
817 .offset = offsetof(IntelHDAState, st[_i].ctl), \
818 .whandler = intel_hda_set_st_ctl, \
820 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
822 .name = _t stringify(_i) " CTL(sts)", \
825 .wmask = 0x1c000000, \
826 .wclear = 0x1c000000, \
827 .offset = offsetof(IntelHDAState, st[_i].ctl), \
828 .whandler = intel_hda_set_st_ctl, \
830 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
832 .name = _t stringify(_i) " LPIB", \
834 .offset = offsetof(IntelHDAState, st[_i].lpib), \
836 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
838 .name = _t stringify(_i) " LPIB(alias)", \
840 .offset = offsetof(IntelHDAState, st[_i].lpib), \
842 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
844 .name = _t stringify(_i) " CBL", \
846 .wmask = 0xffffffff, \
847 .offset = offsetof(IntelHDAState, st[_i].cbl), \
849 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
851 .name = _t stringify(_i) " LVI", \
854 .offset = offsetof(IntelHDAState, st[_i].lvi), \
856 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
858 .name = _t stringify(_i) " FIFOS", \
860 .reset = HDA_BUFFER_SIZE, \
862 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
864 .name = _t stringify(_i) " FMT", \
867 .offset = offsetof(IntelHDAState, st[_i].fmt), \
869 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
871 .name = _t stringify(_i) " BDLPL", \
873 .wmask = 0xffffff80, \
874 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
876 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
878 .name = _t stringify(_i) " BDLPU", \
880 .wmask = 0xffffffff, \
881 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
896 static const IntelHDAReg
*intel_hda_reg_find(IntelHDAState
*d
, target_phys_addr_t addr
)
898 const IntelHDAReg
*reg
;
900 if (addr
>= sizeof(regtab
)/sizeof(regtab
[0])) {
904 if (reg
->name
== NULL
) {
910 dprint(d
, 1, "unknown register, addr 0x%x\n", (int) addr
);
914 static uint32_t *intel_hda_reg_addr(IntelHDAState
*d
, const IntelHDAReg
*reg
)
916 uint8_t *addr
= (void*)d
;
919 return (uint32_t*)addr
;
922 static void intel_hda_reg_write(IntelHDAState
*d
, const IntelHDAReg
*reg
, uint32_t val
,
933 time_t now
= time(NULL
);
934 if (d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== val
) {
936 if (d
->last_sec
!= now
) {
937 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
942 if (d
->repeat_count
) {
943 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
945 dprint(d
, 2, "write %-16s: 0x%x (%x)\n", reg
->name
, val
, wmask
);
953 assert(reg
->offset
!= 0);
955 addr
= intel_hda_reg_addr(d
, reg
);
960 wmask
<<= reg
->shift
;
964 *addr
|= wmask
& val
;
965 *addr
&= ~(val
& reg
->wclear
);
968 reg
->whandler(d
, reg
, old
);
972 static uint32_t intel_hda_reg_read(IntelHDAState
*d
, const IntelHDAReg
*reg
,
982 reg
->rhandler(d
, reg
);
985 if (reg
->offset
== 0) {
986 /* constant read-only register */
989 addr
= intel_hda_reg_addr(d
, reg
);
997 time_t now
= time(NULL
);
998 if (!d
->last_write
&& d
->last_reg
== reg
&& d
->last_val
== ret
) {
1000 if (d
->last_sec
!= now
) {
1001 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1003 d
->repeat_count
= 0;
1006 if (d
->repeat_count
) {
1007 dprint(d
, 2, "previous register op repeated %d times\n", d
->repeat_count
);
1009 dprint(d
, 2, "read %-16s: 0x%x (%x)\n", reg
->name
, ret
, rmask
);
1014 d
->repeat_count
= 0;
1020 static void intel_hda_regs_reset(IntelHDAState
*d
)
1025 for (i
= 0; i
< sizeof(regtab
)/sizeof(regtab
[0]); i
++) {
1026 if (regtab
[i
].name
== NULL
) {
1029 if (regtab
[i
].offset
== 0) {
1032 addr
= intel_hda_reg_addr(d
, regtab
+ i
);
1033 *addr
= regtab
[i
].reset
;
1037 /* --------------------------------------------------------------------- */
1039 static void intel_hda_mmio_writeb(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1041 IntelHDAState
*d
= opaque
;
1042 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1044 intel_hda_reg_write(d
, reg
, val
, 0xff);
1047 static void intel_hda_mmio_writew(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1049 IntelHDAState
*d
= opaque
;
1050 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1052 intel_hda_reg_write(d
, reg
, val
, 0xffff);
1055 static void intel_hda_mmio_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
1057 IntelHDAState
*d
= opaque
;
1058 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1060 intel_hda_reg_write(d
, reg
, val
, 0xffffffff);
1063 static uint32_t intel_hda_mmio_readb(void *opaque
, target_phys_addr_t addr
)
1065 IntelHDAState
*d
= opaque
;
1066 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1068 return intel_hda_reg_read(d
, reg
, 0xff);
1071 static uint32_t intel_hda_mmio_readw(void *opaque
, target_phys_addr_t addr
)
1073 IntelHDAState
*d
= opaque
;
1074 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1076 return intel_hda_reg_read(d
, reg
, 0xffff);
1079 static uint32_t intel_hda_mmio_readl(void *opaque
, target_phys_addr_t addr
)
1081 IntelHDAState
*d
= opaque
;
1082 const IntelHDAReg
*reg
= intel_hda_reg_find(d
, addr
);
1084 return intel_hda_reg_read(d
, reg
, 0xffffffff);
1087 static CPUReadMemoryFunc
* const intel_hda_mmio_read
[3] = {
1088 intel_hda_mmio_readb
,
1089 intel_hda_mmio_readw
,
1090 intel_hda_mmio_readl
,
1093 static CPUWriteMemoryFunc
* const intel_hda_mmio_write
[3] = {
1094 intel_hda_mmio_writeb
,
1095 intel_hda_mmio_writew
,
1096 intel_hda_mmio_writel
,
1099 /* --------------------------------------------------------------------- */
1101 static void intel_hda_reset(DeviceState
*dev
)
1103 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
.qdev
, dev
);
1105 HDACodecDevice
*cdev
;
1107 intel_hda_regs_reset(d
);
1108 d
->wall_base_ns
= qemu_get_clock_ns(vm_clock
);
1111 QLIST_FOREACH(qdev
, &d
->codecs
.qbus
.children
, sibling
) {
1112 cdev
= DO_UPCAST(HDACodecDevice
, qdev
, qdev
);
1113 if (qdev
->info
->reset
) {
1114 qdev
->info
->reset(qdev
);
1116 d
->state_sts
|= (1 << cdev
->cad
);
1118 intel_hda_update_irq(d
);
1121 static int intel_hda_init(PCIDevice
*pci
)
1123 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1124 uint8_t *conf
= d
->pci
.config
;
1126 d
->name
= d
->pci
.qdev
.info
->name
;
1128 pci_config_set_interrupt_pin(conf
, 1);
1130 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1133 d
->mmio_addr
= cpu_register_io_memory(intel_hda_mmio_read
,
1134 intel_hda_mmio_write
, d
,
1135 DEVICE_NATIVE_ENDIAN
);
1136 pci_register_bar_simple(&d
->pci
, 0, 0x4000, 0, d
->mmio_addr
);
1138 msi_init(&d
->pci
, 0x50, 1, true, false);
1141 hda_codec_bus_init(&d
->pci
.qdev
, &d
->codecs
,
1142 intel_hda_response
, intel_hda_xfer
);
1147 static int intel_hda_exit(PCIDevice
*pci
)
1149 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1151 msi_uninit(&d
->pci
);
1152 cpu_unregister_io_memory(d
->mmio_addr
);
1156 static void intel_hda_write_config(PCIDevice
*pci
, uint32_t addr
,
1157 uint32_t val
, int len
)
1159 IntelHDAState
*d
= DO_UPCAST(IntelHDAState
, pci
, pci
);
1161 pci_default_write_config(pci
, addr
, val
, len
);
1163 msi_write_config(pci
, addr
, val
, len
);
1167 static int intel_hda_post_load(void *opaque
, int version
)
1169 IntelHDAState
* d
= opaque
;
1172 dprint(d
, 1, "%s\n", __FUNCTION__
);
1173 for (i
= 0; i
< ARRAY_SIZE(d
->st
); i
++) {
1174 if (d
->st
[i
].ctl
& 0x02) {
1175 intel_hda_parse_bdl(d
, &d
->st
[i
]);
1178 intel_hda_update_irq(d
);
1182 static const VMStateDescription vmstate_intel_hda_stream
= {
1183 .name
= "intel-hda-stream",
1185 .fields
= (VMStateField
[]) {
1186 VMSTATE_UINT32(ctl
, IntelHDAStream
),
1187 VMSTATE_UINT32(lpib
, IntelHDAStream
),
1188 VMSTATE_UINT32(cbl
, IntelHDAStream
),
1189 VMSTATE_UINT32(lvi
, IntelHDAStream
),
1190 VMSTATE_UINT32(fmt
, IntelHDAStream
),
1191 VMSTATE_UINT32(bdlp_lbase
, IntelHDAStream
),
1192 VMSTATE_UINT32(bdlp_ubase
, IntelHDAStream
),
1193 VMSTATE_END_OF_LIST()
1197 static const VMStateDescription vmstate_intel_hda
= {
1198 .name
= "intel-hda",
1200 .post_load
= intel_hda_post_load
,
1201 .fields
= (VMStateField
[]) {
1202 VMSTATE_PCI_DEVICE(pci
, IntelHDAState
),
1205 VMSTATE_UINT32(g_ctl
, IntelHDAState
),
1206 VMSTATE_UINT32(wake_en
, IntelHDAState
),
1207 VMSTATE_UINT32(state_sts
, IntelHDAState
),
1208 VMSTATE_UINT32(int_ctl
, IntelHDAState
),
1209 VMSTATE_UINT32(int_sts
, IntelHDAState
),
1210 VMSTATE_UINT32(wall_clk
, IntelHDAState
),
1211 VMSTATE_UINT32(corb_lbase
, IntelHDAState
),
1212 VMSTATE_UINT32(corb_ubase
, IntelHDAState
),
1213 VMSTATE_UINT32(corb_rp
, IntelHDAState
),
1214 VMSTATE_UINT32(corb_wp
, IntelHDAState
),
1215 VMSTATE_UINT32(corb_ctl
, IntelHDAState
),
1216 VMSTATE_UINT32(corb_sts
, IntelHDAState
),
1217 VMSTATE_UINT32(corb_size
, IntelHDAState
),
1218 VMSTATE_UINT32(rirb_lbase
, IntelHDAState
),
1219 VMSTATE_UINT32(rirb_ubase
, IntelHDAState
),
1220 VMSTATE_UINT32(rirb_wp
, IntelHDAState
),
1221 VMSTATE_UINT32(rirb_cnt
, IntelHDAState
),
1222 VMSTATE_UINT32(rirb_ctl
, IntelHDAState
),
1223 VMSTATE_UINT32(rirb_sts
, IntelHDAState
),
1224 VMSTATE_UINT32(rirb_size
, IntelHDAState
),
1225 VMSTATE_UINT32(dp_lbase
, IntelHDAState
),
1226 VMSTATE_UINT32(dp_ubase
, IntelHDAState
),
1227 VMSTATE_UINT32(icw
, IntelHDAState
),
1228 VMSTATE_UINT32(irr
, IntelHDAState
),
1229 VMSTATE_UINT32(ics
, IntelHDAState
),
1230 VMSTATE_STRUCT_ARRAY(st
, IntelHDAState
, 8, 0,
1231 vmstate_intel_hda_stream
,
1234 /* additional state info */
1235 VMSTATE_UINT32(rirb_count
, IntelHDAState
),
1236 VMSTATE_INT64(wall_base_ns
, IntelHDAState
),
1238 VMSTATE_END_OF_LIST()
1242 static PCIDeviceInfo intel_hda_info
= {
1243 .qdev
.name
= "intel-hda",
1244 .qdev
.desc
= "Intel HD Audio Controller",
1245 .qdev
.size
= sizeof(IntelHDAState
),
1246 .qdev
.vmsd
= &vmstate_intel_hda
,
1247 .qdev
.reset
= intel_hda_reset
,
1248 .init
= intel_hda_init
,
1249 .exit
= intel_hda_exit
,
1250 .config_write
= intel_hda_write_config
,
1251 .vendor_id
= PCI_VENDOR_ID_INTEL
,
1252 .device_id
= 0x2668,
1254 .class_id
= PCI_CLASS_MULTIMEDIA_HD_AUDIO
,
1255 .qdev
.props
= (Property
[]) {
1256 DEFINE_PROP_UINT32("debug", IntelHDAState
, debug
, 0),
1257 DEFINE_PROP_UINT32("msi", IntelHDAState
, msi
, 1),
1258 DEFINE_PROP_END_OF_LIST(),
1262 static void intel_hda_register(void)
1264 pci_qdev_register(&intel_hda_info
);
1266 device_init(intel_hda_register
);
1269 * create intel hda controller with codec attached to it,
1270 * so '-soundhw hda' works.
1272 int intel_hda_and_codec_init(PCIBus
*bus
)
1274 PCIDevice
*controller
;
1278 controller
= pci_create_simple(bus
, -1, "intel-hda");
1279 hdabus
= QLIST_FIRST(&controller
->qdev
.child_bus
);
1280 codec
= qdev_create(hdabus
, "hda-duplex");
1281 qdev_init_nofail(codec
);