From 6b47d21562aef178f719c5b9df474b7758018197 Mon Sep 17 00:00:00 2001 From: roybaer Date: Wed, 20 Nov 2024 21:15:00 +0000 Subject: [PATCH] Limit regression tests in ucsim to 100000000 vclk cycles. git-svn-id: https://svn.code.sf.net/p/sdcc/code/trunk@15112 4a8a32a2-be11-0410-ad9d-d568d2c75423 --- sdcc/ChangeLog | 33 ++++++++++++++++++++++ sdcc/support/regression/ports/ds390/uCsim.cmd | 2 +- sdcc/support/regression/ports/ez80-z80/uCsim.cmd | 2 +- sdcc/support/regression/ports/f8/uCsim.cmd | 2 +- sdcc/support/regression/ports/hc08/uCsim.cmd | 2 +- .../regression/ports/mcs51-common/uCsim.cmd | 2 +- sdcc/support/regression/ports/pdk13/uCsim.cmd | 2 +- sdcc/support/regression/ports/pdk14/uCsim.cmd | 2 +- .../regression/ports/pdk15-stack-auto/uCsim.cmd | 2 +- sdcc/support/regression/ports/pdk15/uCsim.cmd | 2 +- .../regression/ports/s08-stack-auto/uCsim.cmd | 2 +- sdcc/support/regression/ports/s08/uCsim.cmd | 2 +- sdcc/support/regression/ports/stm8-large/uCsim.cmd | 2 +- sdcc/support/regression/ports/stm8/uCsim.cmd | 2 +- sdcc/support/regression/ports/tlcs90/uCsim.cmd | 2 +- .../regression/ports/uc6502-stack-auto/uCsim.cmd | 2 +- sdcc/support/regression/ports/uc6502/uCsim.cmd | 2 +- sdcc/support/regression/ports/uc65c02/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucgbz80/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucr2k/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucr2ka/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucr3ka/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucr800/uCsim.cmd | 2 +- .../regression/ports/ucz180-resiy/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucz180/uCsim.cmd | 2 +- .../support/regression/ports/ucz80-resiy/uCsim.cmd | 2 +- .../support/regression/ports/ucz80-undoc/uCsim.cmd | 2 +- .../regression/ports/ucz80-unsafe-read/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucz80/uCsim.cmd | 2 +- sdcc/support/regression/ports/ucz80n/uCsim.cmd | 2 +- 30 files changed, 62 insertions(+), 29 deletions(-) diff --git a/sdcc/ChangeLog b/sdcc/ChangeLog index efdf9c12d..c1090db68 100644 --- a/sdcc/ChangeLog +++ b/sdcc/ChangeLog @@ -1,5 +1,38 @@ 2024-11-20 Benedikt Freisen + * support/regression/ports/ds390/uCsim.cmd, + support/regression/ports/ez80-z80/uCsim.cmd, + support/regression/ports/f8/uCsim.cmd, + support/regression/ports/hc08/uCsim.cmd, + support/regression/ports/mcs51-common/uCsim.cmd, + support/regression/ports/pdk13/uCsim.cmd, + support/regression/ports/pdk14/uCsim.cmd, + support/regression/ports/pdk15-stack-auto/uCsim.cmd, + support/regression/ports/pdk15/uCsim.cmd, + support/regression/ports/s08-stack-auto/uCsim.cmd, + support/regression/ports/s08/uCsim.cmd, + support/regression/ports/stm8-large/uCsim.cmd, + support/regression/ports/stm8/uCsim.cmd, + support/regression/ports/tlcs90/uCsim.cmd, + support/regression/ports/uc6502-stack-auto/uCsim.cmd, + support/regression/ports/uc6502/uCsim.cmd, + support/regression/ports/uc65c02/uCsim.cmd, + support/regression/ports/ucgbz80/uCsim.cmd, + support/regression/ports/ucr2k/uCsim.cmd, + support/regression/ports/ucr2ka/uCsim.cmd, + support/regression/ports/ucr3ka/uCsim.cmd, + support/regression/ports/ucr800/uCsim.cmd, + support/regression/ports/ucz180-resiy/uCsim.cmd, + support/regression/ports/ucz180/uCsim.cmd, + support/regression/ports/ucz80-resiy/uCsim.cmd, + support/regression/ports/ucz80-undoc/uCsim.cmd, + support/regression/ports/ucz80-unsafe-read/uCsim.cmd, + support/regression/ports/ucz80/uCsim.cmd, + support/regression/ports/ucz80n/uCsim.cmd: + Limit regression tests in ucsim to 100000000 vclk cycles. + +2024-11-20 Benedikt Freisen + * device/include/wchar.h, device/lib/incl.mk, device/lib/wcsnlen.c, diff --git a/sdcc/support/regression/ports/ds390/uCsim.cmd b/sdcc/support/regression/ports/ds390/uCsim.cmd index a3ffbe039..5c1185831 100644 --- a/sdcc/support/regression/ports/ds390/uCsim.cmd +++ b/sdcc/support/regression/ports/ds390/uCsim.cmd @@ -15,6 +15,6 @@ expr /n port1_on=0 expr /n port2_on=0 expr /n port3_on=0 expr /n irq0_on=0 -emu +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ez80-z80/uCsim.cmd b/sdcc/support/regression/ports/ez80-z80/uCsim.cmd index 657571912..7c3340634 100644 --- a/sdcc/support/regression/ports/ez80-z80/uCsim.cmd +++ b/sdcc/support/regression/ports/ez80-z80/uCsim.cmd @@ -4,7 +4,7 @@ set error memory off set error stack off set hw simif outputs 0xff show con -run +step 100000000 vclk state show con kill diff --git a/sdcc/support/regression/ports/f8/uCsim.cmd b/sdcc/support/regression/ports/f8/uCsim.cmd index e934b0319..34ad2eb44 100644 --- a/sdcc/support/regression/ports/f8/uCsim.cmd +++ b/sdcc/support/regression/ports/f8/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0x1fff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/hc08/uCsim.cmd b/sdcc/support/regression/ports/hc08/uCsim.cmd index e3761654f..e7564d89c 100644 --- a/sdcc/support/regression/ports/hc08/uCsim.cmd +++ b/sdcc/support/regression/ports/hc08/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0x7f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/mcs51-common/uCsim.cmd b/sdcc/support/regression/ports/mcs51-common/uCsim.cmd index 95bc7dfee..95c695d1a 100644 --- a/sdcc/support/regression/ports/mcs51-common/uCsim.cmd +++ b/sdcc/support/regression/ports/mcs51-common/uCsim.cmd @@ -16,6 +16,6 @@ expr /n uart0_on=0 expr /n dreg0_on=0 expr /n dport0_on=0 expr /n irq0_on=0 -emu +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/pdk13/uCsim.cmd b/sdcc/support/regression/ports/pdk13/uCsim.cmd index 6f0165c48..f52657c17 100644 --- a/sdcc/support/regression/ports/pdk13/uCsim.cmd +++ b/sdcc/support/regression/ports/pdk13/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif regs8 0x1f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/pdk14/uCsim.cmd b/sdcc/support/regression/ports/pdk14/uCsim.cmd index c48d96c8b..099a8718b 100644 --- a/sdcc/support/regression/ports/pdk14/uCsim.cmd +++ b/sdcc/support/regression/ports/pdk14/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif regs8 0x3f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/pdk15-stack-auto/uCsim.cmd b/sdcc/support/regression/ports/pdk15-stack-auto/uCsim.cmd index c48d96c8b..099a8718b 100644 --- a/sdcc/support/regression/ports/pdk15-stack-auto/uCsim.cmd +++ b/sdcc/support/regression/ports/pdk15-stack-auto/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif regs8 0x3f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/pdk15/uCsim.cmd b/sdcc/support/regression/ports/pdk15/uCsim.cmd index c48d96c8b..099a8718b 100644 --- a/sdcc/support/regression/ports/pdk15/uCsim.cmd +++ b/sdcc/support/regression/ports/pdk15/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif regs8 0x3f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/s08-stack-auto/uCsim.cmd b/sdcc/support/regression/ports/s08-stack-auto/uCsim.cmd index e3761654f..e7564d89c 100644 --- a/sdcc/support/regression/ports/s08-stack-auto/uCsim.cmd +++ b/sdcc/support/regression/ports/s08-stack-auto/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0x7f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/s08/uCsim.cmd b/sdcc/support/regression/ports/s08/uCsim.cmd index e3761654f..e7564d89c 100644 --- a/sdcc/support/regression/ports/s08/uCsim.cmd +++ b/sdcc/support/regression/ports/s08/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0x7f -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/stm8-large/uCsim.cmd b/sdcc/support/regression/ports/stm8-large/uCsim.cmd index 0f994591e..7893e2cf0 100644 --- a/sdcc/support/regression/ports/stm8-large/uCsim.cmd +++ b/sdcc/support/regression/ports/stm8-large/uCsim.cmd @@ -24,6 +24,6 @@ expr /n tim22_on=0 expr /n tim33_on=0 expr /n tim44_on=0 expr /n vcd0_on=0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/stm8/uCsim.cmd b/sdcc/support/regression/ports/stm8/uCsim.cmd index 0f994591e..7893e2cf0 100644 --- a/sdcc/support/regression/ports/stm8/uCsim.cmd +++ b/sdcc/support/regression/ports/stm8/uCsim.cmd @@ -24,6 +24,6 @@ expr /n tim22_on=0 expr /n tim33_on=0 expr /n tim44_on=0 expr /n vcd0_on=0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/tlcs90/uCsim.cmd b/sdcc/support/regression/ports/tlcs90/uCsim.cmd index 35dc5be18..bd9be30e8 100644 --- a/sdcc/support/regression/ports/tlcs90/uCsim.cmd +++ b/sdcc/support/regression/ports/tlcs90/uCsim.cmd @@ -5,6 +5,6 @@ set error stack off set hw simif nas 0xffff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/uc6502-stack-auto/uCsim.cmd b/sdcc/support/regression/ports/uc6502-stack-auto/uCsim.cmd index fbd05e26e..aca7973e8 100644 --- a/sdcc/support/regression/ports/uc6502-stack-auto/uCsim.cmd +++ b/sdcc/support/regression/ports/uc6502-stack-auto/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0xfff0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/uc6502/uCsim.cmd b/sdcc/support/regression/ports/uc6502/uCsim.cmd index fbd05e26e..aca7973e8 100644 --- a/sdcc/support/regression/ports/uc6502/uCsim.cmd +++ b/sdcc/support/regression/ports/uc6502/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0xfff0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/uc65c02/uCsim.cmd b/sdcc/support/regression/ports/uc65c02/uCsim.cmd index fbd05e26e..aca7973e8 100644 --- a/sdcc/support/regression/ports/uc65c02/uCsim.cmd +++ b/sdcc/support/regression/ports/uc65c02/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif rom 0xfff0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucgbz80/uCsim.cmd b/sdcc/support/regression/ports/ucgbz80/uCsim.cmd index 5abcf8b87..7cbd4b7b3 100755 --- a/sdcc/support/regression/ports/ucgbz80/uCsim.cmd +++ b/sdcc/support/regression/ports/ucgbz80/uCsim.cmd @@ -4,6 +4,6 @@ set error memory off set error stack off set hw simif xram 0xff03 pc 0x100 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucr2k/uCsim.cmd b/sdcc/support/regression/ports/ucr2k/uCsim.cmd index b3164e6db..7ce5d7729 100644 --- a/sdcc/support/regression/ports/ucr2k/uCsim.cmd +++ b/sdcc/support/regression/ports/ucr2k/uCsim.cmd @@ -5,6 +5,6 @@ set error stack off set hw simif rom 0x7fff vcd0_on=0 dreg0_on=0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucr2ka/uCsim.cmd b/sdcc/support/regression/ports/ucr2ka/uCsim.cmd index b3164e6db..7ce5d7729 100644 --- a/sdcc/support/regression/ports/ucr2ka/uCsim.cmd +++ b/sdcc/support/regression/ports/ucr2ka/uCsim.cmd @@ -5,6 +5,6 @@ set error stack off set hw simif rom 0x7fff vcd0_on=0 dreg0_on=0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucr3ka/uCsim.cmd b/sdcc/support/regression/ports/ucr3ka/uCsim.cmd index b3164e6db..7ce5d7729 100644 --- a/sdcc/support/regression/ports/ucr3ka/uCsim.cmd +++ b/sdcc/support/regression/ports/ucr3ka/uCsim.cmd @@ -5,6 +5,6 @@ set error stack off set hw simif rom 0x7fff vcd0_on=0 dreg0_on=0 -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucr800/uCsim.cmd b/sdcc/support/regression/ports/ucr800/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucr800/uCsim.cmd +++ b/sdcc/support/regression/ports/ucr800/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz180-resiy/uCsim.cmd b/sdcc/support/regression/ports/ucz180-resiy/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz180-resiy/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz180-resiy/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz180/uCsim.cmd b/sdcc/support/regression/ports/ucz180/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz180/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz180/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz80-resiy/uCsim.cmd b/sdcc/support/regression/ports/ucz80-resiy/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz80-resiy/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz80-resiy/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz80-undoc/uCsim.cmd b/sdcc/support/regression/ports/ucz80-undoc/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz80-undoc/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz80-undoc/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz80-unsafe-read/uCsim.cmd b/sdcc/support/regression/ports/ucz80-unsafe-read/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz80-unsafe-read/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz80-unsafe-read/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz80/uCsim.cmd b/sdcc/support/regression/ports/ucz80/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz80/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz80/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit diff --git a/sdcc/support/regression/ports/ucz80n/uCsim.cmd b/sdcc/support/regression/ports/ucz80n/uCsim.cmd index dac3914e6..2a078e2f8 100644 --- a/sdcc/support/regression/ports/ucz80n/uCsim.cmd +++ b/sdcc/support/regression/ports/ucz80n/uCsim.cmd @@ -3,6 +3,6 @@ set error unknown_code off set error memory off set error stack off set hw simif outputs 0xff -run +step 100000000 vclk state quit -- 2.11.4.GIT