From 68fa4b1994415a782279c0260460bc14638e688e Mon Sep 17 00:00:00 2001 From: lunix Date: Wed, 25 Aug 2010 22:26:24 +0800 Subject: [PATCH] The simple DMA is OK. The width of the data is set to be 16 bits. The biggest problem is a logical problem. Avanlon is no fault. --- hello_world.c | 58 +++++++++++++++++++++++++++++++++++++++++++++++++++++ sdram_master.h | 13 ++++++++++++ sdram_master.v | 31 +++++++++++++++------------- sdram_master_hw.tcl | 10 ++++----- 4 files changed, 92 insertions(+), 20 deletions(-) create mode 100644 hello_world.c create mode 100644 sdram_master.h diff --git a/hello_world.c b/hello_world.c new file mode 100644 index 0000000..12905d5 --- /dev/null +++ b/hello_world.c @@ -0,0 +1,58 @@ +/* + * "Hello World" example. + * + * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on + * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example + * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT + * device in your system's hardware. + * The memory footprint of this hosted application is ~69 kbytes by default + * using the standard reference design. + * + * For a reduced footprint version of this template, and an explanation of how + * to reduce the memory footprint for a given application, see the + * "small_hello_world" template. + * + */ +#include +#include "sdram_master.h" +#include "system.h" +#include "io.h" + +int main() +{ + unsigned char i,j; + int temp; + for(i=0;i<100;i++) + IOWR_8DIRECT(SDRAM_U1_BASE,i,i); + + IOWR(SDRAM_MASTER_INST_BASE,S_ADDR,SDRAM_U1_BASE); + IOWR(SDRAM_MASTER_INST_BASE,D_ADDR,SDRAM_U2_BASE); + IOWR(SDRAM_MASTER_INST_BASE,LONGTH,100); + IOWR(SDRAM_MASTER_INST_BASE,START_ADDR,1); + + temp=IORD(SDRAM_MASTER_INST_BASE,S_ADDR); + printf("S_ADDR:w,r==%d,%d\n",SDRAM_U1_BASE,temp); + temp=IORD(SDRAM_MASTER_INST_BASE,D_ADDR); + printf("D_ADDR:w,r==%d,%d\n",SDRAM_U2_BASE,temp); + temp=IORD(SDRAM_MASTER_INST_BASE,LONGTH); + printf("LONGTH:w,r==%d,%d\n",100,temp); + + while(IORD(SDRAM_MASTER_INST_BASE,STATUS_ADDR)!=1){ + printf("waiting...!\n"); + //break; + }; + + for(i=0;i<100;i++){ + j=IORD_8DIRECT(SDRAM_U1_BASE,i); + printf("SDRAM_U1:i,j == %d, %d\n",i,j); + } + for(i=0;i<100;i++){ + j=IORD_8DIRECT(SDRAM_U2_BASE,i); + printf("SDRAM_U2:i,j == %d, %d\n",i,j); + } + + + printf("Hello from Nios II!\n"); + + return 0; +} diff --git a/sdram_master.h b/sdram_master.h new file mode 100644 index 0000000..aff682e --- /dev/null +++ b/sdram_master.h @@ -0,0 +1,13 @@ +#ifndef SDRAM_MASTER_H_ +#define SDRAM_MASTER_H_ + +#define S_ADDR 0 +#define D_ADDR 1 +#define LONGTH 2 +#define START_ADDR 3 +#define STATUS_ADDR 4 + +#endif /*SDRAM_MASTER_H_*/ + + + diff --git a/sdram_master.v b/sdram_master.v index 1742e0e..029c349 100644 --- a/sdram_master.v +++ b/sdram_master.v @@ -22,14 +22,14 @@ module sdram_master( // read master port interface avm_read_address, avm_read_read, - avm_read_byteenable, + //avm_read_byteenable, avm_read_readdata, avm_read_waitrequest, // write master port interface avm_write_address, avm_write_write, - avm_write_byteenable, + //avm_write_byteenable, avm_write_writedata, avm_write_waitrequest @@ -49,18 +49,19 @@ output avs_s1_waitrequest; // read master port interface output reg [31:0] avm_read_address; output reg avm_read_read; -output reg [3:0] avm_read_byteenable; -input [31:0] avm_read_readdata; +//output reg [3:0] avm_read_byteenable; +//input [31:0] avm_read_readdata; +input [15:0] avm_read_readdata; input avm_read_waitrequest; // write master port interface output reg [31:0] avm_write_address; output reg avm_write_write; -output reg [3:0] avm_write_byteenable; -output reg [31:0] avm_write_writedata; +//output reg [3:0] avm_write_byteenable; +//output reg [31:0] avm_write_writedata; +output reg [15:0] avm_write_writedata; input avm_write_waitrequest; - reg [31:0] S_addr;//source address reg [31:0] D_addr;//destination address reg [31:0] Longth; @@ -68,7 +69,7 @@ reg [31:0] Longth; reg Status; //reg [31:0] DMA_DATA; -reg [7:0] DMA_DATA; +reg [15:0] DMA_DATA; reg [31:0] DMA_Cont; @@ -103,6 +104,7 @@ begin `S_ADDR: avs_s1_readdata <= S_addr; `D_ADDR: avs_s1_readdata <= D_addr; `LONGTH: avs_s1_readdata <= Longth; + `STATUS_ADDR: avs_s1_readdata <= {31'h0,Status}; default: avs_s1_readdata <= 32'h0; endcase end @@ -169,14 +171,14 @@ begin else begin case(DMA_state) DMA_IDLE: begin - DMA_Cont <= 0; - done <= 0; + DMA_Cont <= 32'h0; + done <= 1'b0; if(start) DMA_state <= READ; end READ: begin avm_read_address <= S_addr + DMA_Cont; - avm_read_byteenable <= 4'b0001; + //avm_read_byteenable <= 4'b0001; avm_read_read <= 1'b1; DMA_state <= WAIT_READ; end @@ -190,16 +192,17 @@ begin end WRITE: begin avm_write_address <= D_addr + DMA_Cont; - avm_write_byteenable <= 4'b0001; + //avm_write_byteenable <= 4'b0001; avm_write_write <= 1'b1; avm_write_writedata <= DMA_DATA; + //avm_write_writedata <= DMA_Cont;//temp test DMA_state <= WAIT_WRITE; end WAIT_WRITE: begin - DMA_Cont <= DMA_Cont + 32'h1; if(avm_write_waitrequest == 1'b0 ) begin - avm_write_address <= 0; + DMA_Cont <= DMA_Cont + 32'h2; + //avm_write_address <= 0; avm_write_write <= 1'b0; if(DMA_Cont < Longth) DMA_state <= READ; diff --git a/sdram_master_hw.tcl b/sdram_master_hw.tcl index bd11ba6..3615409 100644 --- a/sdram_master_hw.tcl +++ b/sdram_master_hw.tcl @@ -1,12 +1,12 @@ # TCL File Generated by Component Editor 9.1sp1 -# Wed Aug 25 16:45:14 CST 2010 +# Wed Aug 25 22:14:38 CST 2010 # DO NOT MODIFY # +----------------------------------- # | # | sdram_master "sdram_master" v1.0 -# | null 2010.08.25.16:45:14 +# | null 2010.08.25.22:14:38 # | # | # | J:/lab_source/test/tv_master/ip/sdram_master/sdram_master.v @@ -174,8 +174,7 @@ set_interface_property read ENABLED true add_interface_port read avm_read_address address Output 32 add_interface_port read avm_read_read read Output 1 -add_interface_port read avm_read_byteenable byteenable Output 4 -add_interface_port read avm_read_readdata readdata Input 32 +add_interface_port read avm_read_readdata readdata Input 16 add_interface_port read avm_read_waitrequest waitrequest Input 1 # | # +----------------------------------- @@ -195,8 +194,7 @@ set_interface_property write ENABLED true add_interface_port write avm_write_address address Output 32 add_interface_port write avm_write_write write Output 1 -add_interface_port write avm_write_byteenable byteenable Output 4 -add_interface_port write avm_write_writedata writedata Output 32 +add_interface_port write avm_write_writedata writedata Output 16 add_interface_port write avm_write_waitrequest waitrequest Input 1 # | # +----------------------------------- -- 2.11.4.GIT