Refactor aio callback allocation to use an aiocb pool (Avi Kivity)
[sniper_test.git] / target-mips / op_helper.c
blob0162ac17704008629112cde98b3b59d2445f78a0
1 /*
2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
20 #include <stdlib.h>
21 #include "exec.h"
23 #include "host-utils.h"
25 #include "helper.h"
26 /*****************************************************************************/
27 /* Exceptions processing helpers */
29 void helper_raise_exception_err (uint32_t exception, int error_code)
31 #if 1
32 if (exception < 0x100)
33 qemu_log("%s: %d %d\n", __func__, exception, error_code);
34 #endif
35 env->exception_index = exception;
36 env->error_code = error_code;
37 cpu_loop_exit();
40 void helper_raise_exception (uint32_t exception)
42 helper_raise_exception_err(exception, 0);
45 void helper_interrupt_restart (void)
47 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
48 !(env->CP0_Status & (1 << CP0St_ERL)) &&
49 !(env->hflags & MIPS_HFLAG_DM) &&
50 (env->CP0_Status & (1 << CP0St_IE)) &&
51 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
52 env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
53 helper_raise_exception(EXCP_EXT_INTERRUPT);
57 #if !defined(CONFIG_USER_ONLY)
58 static void do_restore_state (void *pc_ptr)
60 TranslationBlock *tb;
61 unsigned long pc = (unsigned long) pc_ptr;
63 tb = tb_find_pc (pc);
64 if (tb) {
65 cpu_restore_state (tb, env, pc, NULL);
68 #endif
70 target_ulong helper_clo (target_ulong t0)
72 return clo32(t0);
75 target_ulong helper_clz (target_ulong t0)
77 return clz32(t0);
80 #if defined(TARGET_MIPS64)
81 target_ulong helper_dclo (target_ulong t0)
83 return clo64(t0);
86 target_ulong helper_dclz (target_ulong t0)
88 return clz64(t0);
90 #endif /* TARGET_MIPS64 */
92 /* 64 bits arithmetic for 32 bits hosts */
93 static inline uint64_t get_HILO (void)
95 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
98 static inline void set_HILO (uint64_t HILO)
100 env->active_tc.LO[0] = (int32_t)HILO;
101 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
104 static inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
106 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
107 t0 = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
110 static inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
112 t0 = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
113 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
116 /* Multiplication variants of the vr54xx. */
117 target_ulong helper_muls (target_ulong t0, target_ulong t1)
119 set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
121 return t0;
124 target_ulong helper_mulsu (target_ulong t0, target_ulong t1)
126 set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
128 return t0;
131 target_ulong helper_macc (target_ulong t0, target_ulong t1)
133 set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
135 return t0;
138 target_ulong helper_macchi (target_ulong t0, target_ulong t1)
140 set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
142 return t0;
145 target_ulong helper_maccu (target_ulong t0, target_ulong t1)
147 set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
149 return t0;
152 target_ulong helper_macchiu (target_ulong t0, target_ulong t1)
154 set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
156 return t0;
159 target_ulong helper_msac (target_ulong t0, target_ulong t1)
161 set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
163 return t0;
166 target_ulong helper_msachi (target_ulong t0, target_ulong t1)
168 set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
170 return t0;
173 target_ulong helper_msacu (target_ulong t0, target_ulong t1)
175 set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
177 return t0;
180 target_ulong helper_msachiu (target_ulong t0, target_ulong t1)
182 set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
184 return t0;
187 target_ulong helper_mulhi (target_ulong t0, target_ulong t1)
189 set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
191 return t0;
194 target_ulong helper_mulhiu (target_ulong t0, target_ulong t1)
196 set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
198 return t0;
201 target_ulong helper_mulshi (target_ulong t0, target_ulong t1)
203 set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
205 return t0;
208 target_ulong helper_mulshiu (target_ulong t0, target_ulong t1)
210 set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
212 return t0;
215 #ifdef TARGET_MIPS64
216 void helper_dmult (target_ulong t0, target_ulong t1)
218 muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
221 void helper_dmultu (target_ulong t0, target_ulong t1)
223 mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), t0, t1);
225 #endif
227 #ifdef TARGET_WORDS_BIGENDIAN
228 #define GET_LMASK(v) ((v) & 3)
229 #define GET_OFFSET(addr, offset) (addr + (offset))
230 #else
231 #define GET_LMASK(v) (((v) & 3) ^ 3)
232 #define GET_OFFSET(addr, offset) (addr - (offset))
233 #endif
235 target_ulong helper_lwl(target_ulong t0, target_ulong t1, int mem_idx)
237 target_ulong tmp;
239 #ifdef CONFIG_USER_ONLY
240 #define ldfun ldub_raw
241 #else
242 int (*ldfun)(target_ulong);
244 switch (mem_idx)
246 case 0: ldfun = ldub_kernel; break;
247 case 1: ldfun = ldub_super; break;
248 default:
249 case 2: ldfun = ldub_user; break;
251 #endif
252 tmp = ldfun(t0);
253 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
255 if (GET_LMASK(t0) <= 2) {
256 tmp = ldfun(GET_OFFSET(t0, 1));
257 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
260 if (GET_LMASK(t0) <= 1) {
261 tmp = ldfun(GET_OFFSET(t0, 2));
262 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
265 if (GET_LMASK(t0) == 0) {
266 tmp = ldfun(GET_OFFSET(t0, 3));
267 t1 = (t1 & 0xFFFFFF00) | tmp;
269 return (int32_t)t1;
272 target_ulong helper_lwr(target_ulong t0, target_ulong t1, int mem_idx)
274 target_ulong tmp;
276 #ifdef CONFIG_USER_ONLY
277 #define ldfun ldub_raw
278 #else
279 int (*ldfun)(target_ulong);
281 switch (mem_idx)
283 case 0: ldfun = ldub_kernel; break;
284 case 1: ldfun = ldub_super; break;
285 default:
286 case 2: ldfun = ldub_user; break;
288 #endif
289 tmp = ldfun(t0);
290 t1 = (t1 & 0xFFFFFF00) | tmp;
292 if (GET_LMASK(t0) >= 1) {
293 tmp = ldfun(GET_OFFSET(t0, -1));
294 t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
297 if (GET_LMASK(t0) >= 2) {
298 tmp = ldfun(GET_OFFSET(t0, -2));
299 t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
302 if (GET_LMASK(t0) == 3) {
303 tmp = ldfun(GET_OFFSET(t0, -3));
304 t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
306 return (int32_t)t1;
309 void helper_swl(target_ulong t0, target_ulong t1, int mem_idx)
311 #ifdef CONFIG_USER_ONLY
312 #define stfun stb_raw
313 #else
314 void (*stfun)(target_ulong, int);
316 switch (mem_idx)
318 case 0: stfun = stb_kernel; break;
319 case 1: stfun = stb_super; break;
320 default:
321 case 2: stfun = stb_user; break;
323 #endif
324 stfun(t0, (uint8_t)(t1 >> 24));
326 if (GET_LMASK(t0) <= 2)
327 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
329 if (GET_LMASK(t0) <= 1)
330 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
332 if (GET_LMASK(t0) == 0)
333 stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
336 void helper_swr(target_ulong t0, target_ulong t1, int mem_idx)
338 #ifdef CONFIG_USER_ONLY
339 #define stfun stb_raw
340 #else
341 void (*stfun)(target_ulong, int);
343 switch (mem_idx)
345 case 0: stfun = stb_kernel; break;
346 case 1: stfun = stb_super; break;
347 default:
348 case 2: stfun = stb_user; break;
350 #endif
351 stfun(t0, (uint8_t)t1);
353 if (GET_LMASK(t0) >= 1)
354 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
356 if (GET_LMASK(t0) >= 2)
357 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
359 if (GET_LMASK(t0) == 3)
360 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
363 #if defined(TARGET_MIPS64)
364 /* "half" load and stores. We must do the memory access inline,
365 or fault handling won't work. */
367 #ifdef TARGET_WORDS_BIGENDIAN
368 #define GET_LMASK64(v) ((v) & 7)
369 #else
370 #define GET_LMASK64(v) (((v) & 7) ^ 7)
371 #endif
373 target_ulong helper_ldl(target_ulong t0, target_ulong t1, int mem_idx)
375 uint64_t tmp;
377 #ifdef CONFIG_USER_ONLY
378 #define ldfun ldub_raw
379 #else
380 int (*ldfun)(target_ulong);
382 switch (mem_idx)
384 case 0: ldfun = ldub_kernel; break;
385 case 1: ldfun = ldub_super; break;
386 default:
387 case 2: ldfun = ldub_user; break;
389 #endif
390 tmp = ldfun(t0);
391 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
393 if (GET_LMASK64(t0) <= 6) {
394 tmp = ldfun(GET_OFFSET(t0, 1));
395 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
398 if (GET_LMASK64(t0) <= 5) {
399 tmp = ldfun(GET_OFFSET(t0, 2));
400 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
403 if (GET_LMASK64(t0) <= 4) {
404 tmp = ldfun(GET_OFFSET(t0, 3));
405 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
408 if (GET_LMASK64(t0) <= 3) {
409 tmp = ldfun(GET_OFFSET(t0, 4));
410 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
413 if (GET_LMASK64(t0) <= 2) {
414 tmp = ldfun(GET_OFFSET(t0, 5));
415 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
418 if (GET_LMASK64(t0) <= 1) {
419 tmp = ldfun(GET_OFFSET(t0, 6));
420 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
423 if (GET_LMASK64(t0) == 0) {
424 tmp = ldfun(GET_OFFSET(t0, 7));
425 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
428 return t1;
431 target_ulong helper_ldr(target_ulong t0, target_ulong t1, int mem_idx)
433 uint64_t tmp;
435 #ifdef CONFIG_USER_ONLY
436 #define ldfun ldub_raw
437 #else
438 int (*ldfun)(target_ulong);
440 switch (mem_idx)
442 case 0: ldfun = ldub_kernel; break;
443 case 1: ldfun = ldub_super; break;
444 default:
445 case 2: ldfun = ldub_user; break;
447 #endif
448 tmp = ldfun(t0);
449 t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
451 if (GET_LMASK64(t0) >= 1) {
452 tmp = ldfun(GET_OFFSET(t0, -1));
453 t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
456 if (GET_LMASK64(t0) >= 2) {
457 tmp = ldfun(GET_OFFSET(t0, -2));
458 t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
461 if (GET_LMASK64(t0) >= 3) {
462 tmp = ldfun(GET_OFFSET(t0, -3));
463 t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
466 if (GET_LMASK64(t0) >= 4) {
467 tmp = ldfun(GET_OFFSET(t0, -4));
468 t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
471 if (GET_LMASK64(t0) >= 5) {
472 tmp = ldfun(GET_OFFSET(t0, -5));
473 t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
476 if (GET_LMASK64(t0) >= 6) {
477 tmp = ldfun(GET_OFFSET(t0, -6));
478 t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
481 if (GET_LMASK64(t0) == 7) {
482 tmp = ldfun(GET_OFFSET(t0, -7));
483 t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
486 return t1;
489 void helper_sdl(target_ulong t0, target_ulong t1, int mem_idx)
491 #ifdef CONFIG_USER_ONLY
492 #define stfun stb_raw
493 #else
494 void (*stfun)(target_ulong, int);
496 switch (mem_idx)
498 case 0: stfun = stb_kernel; break;
499 case 1: stfun = stb_super; break;
500 default:
501 case 2: stfun = stb_user; break;
503 #endif
504 stfun(t0, (uint8_t)(t1 >> 56));
506 if (GET_LMASK64(t0) <= 6)
507 stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
509 if (GET_LMASK64(t0) <= 5)
510 stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
512 if (GET_LMASK64(t0) <= 4)
513 stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
515 if (GET_LMASK64(t0) <= 3)
516 stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
518 if (GET_LMASK64(t0) <= 2)
519 stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
521 if (GET_LMASK64(t0) <= 1)
522 stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
524 if (GET_LMASK64(t0) <= 0)
525 stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
528 void helper_sdr(target_ulong t0, target_ulong t1, int mem_idx)
530 #ifdef CONFIG_USER_ONLY
531 #define stfun stb_raw
532 #else
533 void (*stfun)(target_ulong, int);
535 switch (mem_idx)
537 case 0: stfun = stb_kernel; break;
538 case 1: stfun = stb_super; break;
539 default:
540 case 2: stfun = stb_user; break;
542 #endif
543 stfun(t0, (uint8_t)t1);
545 if (GET_LMASK64(t0) >= 1)
546 stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
548 if (GET_LMASK64(t0) >= 2)
549 stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
551 if (GET_LMASK64(t0) >= 3)
552 stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
554 if (GET_LMASK64(t0) >= 4)
555 stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
557 if (GET_LMASK64(t0) >= 5)
558 stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
560 if (GET_LMASK64(t0) >= 6)
561 stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
563 if (GET_LMASK64(t0) == 7)
564 stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
566 #endif /* TARGET_MIPS64 */
568 #ifndef CONFIG_USER_ONLY
569 /* CP0 helpers */
570 target_ulong helper_mfc0_mvpcontrol (void)
572 return env->mvp->CP0_MVPControl;
575 target_ulong helper_mfc0_mvpconf0 (void)
577 return env->mvp->CP0_MVPConf0;
580 target_ulong helper_mfc0_mvpconf1 (void)
582 return env->mvp->CP0_MVPConf1;
585 target_ulong helper_mfc0_random (void)
587 return (int32_t)cpu_mips_get_random(env);
590 target_ulong helper_mfc0_tcstatus (void)
592 return env->active_tc.CP0_TCStatus;
595 target_ulong helper_mftc0_tcstatus(void)
597 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
599 if (other_tc == env->current_tc)
600 return env->active_tc.CP0_TCStatus;
601 else
602 return env->tcs[other_tc].CP0_TCStatus;
605 target_ulong helper_mfc0_tcbind (void)
607 return env->active_tc.CP0_TCBind;
610 target_ulong helper_mftc0_tcbind(void)
612 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
614 if (other_tc == env->current_tc)
615 return env->active_tc.CP0_TCBind;
616 else
617 return env->tcs[other_tc].CP0_TCBind;
620 target_ulong helper_mfc0_tcrestart (void)
622 return env->active_tc.PC;
625 target_ulong helper_mftc0_tcrestart(void)
627 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
629 if (other_tc == env->current_tc)
630 return env->active_tc.PC;
631 else
632 return env->tcs[other_tc].PC;
635 target_ulong helper_mfc0_tchalt (void)
637 return env->active_tc.CP0_TCHalt;
640 target_ulong helper_mftc0_tchalt(void)
642 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
644 if (other_tc == env->current_tc)
645 return env->active_tc.CP0_TCHalt;
646 else
647 return env->tcs[other_tc].CP0_TCHalt;
650 target_ulong helper_mfc0_tccontext (void)
652 return env->active_tc.CP0_TCContext;
655 target_ulong helper_mftc0_tccontext(void)
657 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
659 if (other_tc == env->current_tc)
660 return env->active_tc.CP0_TCContext;
661 else
662 return env->tcs[other_tc].CP0_TCContext;
665 target_ulong helper_mfc0_tcschedule (void)
667 return env->active_tc.CP0_TCSchedule;
670 target_ulong helper_mftc0_tcschedule(void)
672 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
674 if (other_tc == env->current_tc)
675 return env->active_tc.CP0_TCSchedule;
676 else
677 return env->tcs[other_tc].CP0_TCSchedule;
680 target_ulong helper_mfc0_tcschefback (void)
682 return env->active_tc.CP0_TCScheFBack;
685 target_ulong helper_mftc0_tcschefback(void)
687 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
689 if (other_tc == env->current_tc)
690 return env->active_tc.CP0_TCScheFBack;
691 else
692 return env->tcs[other_tc].CP0_TCScheFBack;
695 target_ulong helper_mfc0_count (void)
697 return (int32_t)cpu_mips_get_count(env);
700 target_ulong helper_mftc0_entryhi(void)
702 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
703 int32_t tcstatus;
705 if (other_tc == env->current_tc)
706 tcstatus = env->active_tc.CP0_TCStatus;
707 else
708 tcstatus = env->tcs[other_tc].CP0_TCStatus;
710 return (env->CP0_EntryHi & ~0xff) | (tcstatus & 0xff);
713 target_ulong helper_mftc0_status(void)
715 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
716 target_ulong t0;
717 int32_t tcstatus;
719 if (other_tc == env->current_tc)
720 tcstatus = env->active_tc.CP0_TCStatus;
721 else
722 tcstatus = env->tcs[other_tc].CP0_TCStatus;
724 t0 = env->CP0_Status & ~0xf1000018;
725 t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
726 t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
727 t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
729 return t0;
732 target_ulong helper_mfc0_lladdr (void)
734 return (int32_t)env->CP0_LLAddr >> 4;
737 target_ulong helper_mfc0_watchlo (uint32_t sel)
739 return (int32_t)env->CP0_WatchLo[sel];
742 target_ulong helper_mfc0_watchhi (uint32_t sel)
744 return env->CP0_WatchHi[sel];
747 target_ulong helper_mfc0_debug (void)
749 target_ulong t0 = env->CP0_Debug;
750 if (env->hflags & MIPS_HFLAG_DM)
751 t0 |= 1 << CP0DB_DM;
753 return t0;
756 target_ulong helper_mftc0_debug(void)
758 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
759 int32_t tcstatus;
761 if (other_tc == env->current_tc)
762 tcstatus = env->active_tc.CP0_Debug_tcstatus;
763 else
764 tcstatus = env->tcs[other_tc].CP0_Debug_tcstatus;
766 /* XXX: Might be wrong, check with EJTAG spec. */
767 return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
768 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
771 #if defined(TARGET_MIPS64)
772 target_ulong helper_dmfc0_tcrestart (void)
774 return env->active_tc.PC;
777 target_ulong helper_dmfc0_tchalt (void)
779 return env->active_tc.CP0_TCHalt;
782 target_ulong helper_dmfc0_tccontext (void)
784 return env->active_tc.CP0_TCContext;
787 target_ulong helper_dmfc0_tcschedule (void)
789 return env->active_tc.CP0_TCSchedule;
792 target_ulong helper_dmfc0_tcschefback (void)
794 return env->active_tc.CP0_TCScheFBack;
797 target_ulong helper_dmfc0_lladdr (void)
799 return env->CP0_LLAddr >> 4;
802 target_ulong helper_dmfc0_watchlo (uint32_t sel)
804 return env->CP0_WatchLo[sel];
806 #endif /* TARGET_MIPS64 */
808 void helper_mtc0_index (target_ulong t0)
810 int num = 1;
811 unsigned int tmp = env->tlb->nb_tlb;
813 do {
814 tmp >>= 1;
815 num <<= 1;
816 } while (tmp);
817 env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
820 void helper_mtc0_mvpcontrol (target_ulong t0)
822 uint32_t mask = 0;
823 uint32_t newval;
825 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
826 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
827 (1 << CP0MVPCo_EVP);
828 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
829 mask |= (1 << CP0MVPCo_STLB);
830 newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
832 // TODO: Enable/disable shared TLB, enable/disable VPEs.
834 env->mvp->CP0_MVPControl = newval;
837 void helper_mtc0_vpecontrol (target_ulong t0)
839 uint32_t mask;
840 uint32_t newval;
842 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
843 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
844 newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
846 /* Yield scheduler intercept not implemented. */
847 /* Gating storage scheduler intercept not implemented. */
849 // TODO: Enable/disable TCs.
851 env->CP0_VPEControl = newval;
854 void helper_mtc0_vpeconf0 (target_ulong t0)
856 uint32_t mask = 0;
857 uint32_t newval;
859 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
860 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
861 mask |= (0xff << CP0VPEC0_XTC);
862 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
864 newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
866 // TODO: TC exclusive handling due to ERL/EXL.
868 env->CP0_VPEConf0 = newval;
871 void helper_mtc0_vpeconf1 (target_ulong t0)
873 uint32_t mask = 0;
874 uint32_t newval;
876 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
877 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
878 (0xff << CP0VPEC1_NCP1);
879 newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
881 /* UDI not implemented. */
882 /* CP2 not implemented. */
884 // TODO: Handle FPU (CP1) binding.
886 env->CP0_VPEConf1 = newval;
889 void helper_mtc0_yqmask (target_ulong t0)
891 /* Yield qualifier inputs not implemented. */
892 env->CP0_YQMask = 0x00000000;
895 void helper_mtc0_vpeopt (target_ulong t0)
897 env->CP0_VPEOpt = t0 & 0x0000ffff;
900 void helper_mtc0_entrylo0 (target_ulong t0)
902 /* Large physaddr (PABITS) not implemented */
903 /* 1k pages not implemented */
904 env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
907 void helper_mtc0_tcstatus (target_ulong t0)
909 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
910 uint32_t newval;
912 newval = (env->active_tc.CP0_TCStatus & ~mask) | (t0 & mask);
914 // TODO: Sync with CP0_Status.
916 env->active_tc.CP0_TCStatus = newval;
919 void helper_mttc0_tcstatus (target_ulong t0)
921 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
923 // TODO: Sync with CP0_Status.
925 if (other_tc == env->current_tc)
926 env->active_tc.CP0_TCStatus = t0;
927 else
928 env->tcs[other_tc].CP0_TCStatus = t0;
931 void helper_mtc0_tcbind (target_ulong t0)
933 uint32_t mask = (1 << CP0TCBd_TBE);
934 uint32_t newval;
936 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
937 mask |= (1 << CP0TCBd_CurVPE);
938 newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
939 env->active_tc.CP0_TCBind = newval;
942 void helper_mttc0_tcbind (target_ulong t0)
944 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
945 uint32_t mask = (1 << CP0TCBd_TBE);
946 uint32_t newval;
948 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
949 mask |= (1 << CP0TCBd_CurVPE);
950 if (other_tc == env->current_tc) {
951 newval = (env->active_tc.CP0_TCBind & ~mask) | (t0 & mask);
952 env->active_tc.CP0_TCBind = newval;
953 } else {
954 newval = (env->tcs[other_tc].CP0_TCBind & ~mask) | (t0 & mask);
955 env->tcs[other_tc].CP0_TCBind = newval;
959 void helper_mtc0_tcrestart (target_ulong t0)
961 env->active_tc.PC = t0;
962 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
963 env->CP0_LLAddr = 0ULL;
964 /* MIPS16 not implemented. */
967 void helper_mttc0_tcrestart (target_ulong t0)
969 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
971 if (other_tc == env->current_tc) {
972 env->active_tc.PC = t0;
973 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
974 env->CP0_LLAddr = 0ULL;
975 /* MIPS16 not implemented. */
976 } else {
977 env->tcs[other_tc].PC = t0;
978 env->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
979 env->CP0_LLAddr = 0ULL;
980 /* MIPS16 not implemented. */
984 void helper_mtc0_tchalt (target_ulong t0)
986 env->active_tc.CP0_TCHalt = t0 & 0x1;
988 // TODO: Halt TC / Restart (if allocated+active) TC.
991 void helper_mttc0_tchalt (target_ulong t0)
993 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
995 // TODO: Halt TC / Restart (if allocated+active) TC.
997 if (other_tc == env->current_tc)
998 env->active_tc.CP0_TCHalt = t0;
999 else
1000 env->tcs[other_tc].CP0_TCHalt = t0;
1003 void helper_mtc0_tccontext (target_ulong t0)
1005 env->active_tc.CP0_TCContext = t0;
1008 void helper_mttc0_tccontext (target_ulong t0)
1010 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1012 if (other_tc == env->current_tc)
1013 env->active_tc.CP0_TCContext = t0;
1014 else
1015 env->tcs[other_tc].CP0_TCContext = t0;
1018 void helper_mtc0_tcschedule (target_ulong t0)
1020 env->active_tc.CP0_TCSchedule = t0;
1023 void helper_mttc0_tcschedule (target_ulong t0)
1025 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1027 if (other_tc == env->current_tc)
1028 env->active_tc.CP0_TCSchedule = t0;
1029 else
1030 env->tcs[other_tc].CP0_TCSchedule = t0;
1033 void helper_mtc0_tcschefback (target_ulong t0)
1035 env->active_tc.CP0_TCScheFBack = t0;
1038 void helper_mttc0_tcschefback (target_ulong t0)
1040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1042 if (other_tc == env->current_tc)
1043 env->active_tc.CP0_TCScheFBack = t0;
1044 else
1045 env->tcs[other_tc].CP0_TCScheFBack = t0;
1048 void helper_mtc0_entrylo1 (target_ulong t0)
1050 /* Large physaddr (PABITS) not implemented */
1051 /* 1k pages not implemented */
1052 env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
1055 void helper_mtc0_context (target_ulong t0)
1057 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
1060 void helper_mtc0_pagemask (target_ulong t0)
1062 /* 1k pages not implemented */
1063 env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1066 void helper_mtc0_pagegrain (target_ulong t0)
1068 /* SmartMIPS not implemented */
1069 /* Large physaddr (PABITS) not implemented */
1070 /* 1k pages not implemented */
1071 env->CP0_PageGrain = 0;
1074 void helper_mtc0_wired (target_ulong t0)
1076 env->CP0_Wired = t0 % env->tlb->nb_tlb;
1079 void helper_mtc0_srsconf0 (target_ulong t0)
1081 env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
1084 void helper_mtc0_srsconf1 (target_ulong t0)
1086 env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
1089 void helper_mtc0_srsconf2 (target_ulong t0)
1091 env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
1094 void helper_mtc0_srsconf3 (target_ulong t0)
1096 env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
1099 void helper_mtc0_srsconf4 (target_ulong t0)
1101 env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
1104 void helper_mtc0_hwrena (target_ulong t0)
1106 env->CP0_HWREna = t0 & 0x0000000F;
1109 void helper_mtc0_count (target_ulong t0)
1111 cpu_mips_store_count(env, t0);
1114 void helper_mtc0_entryhi (target_ulong t0)
1116 target_ulong old, val;
1118 /* 1k pages not implemented */
1119 val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
1120 #if defined(TARGET_MIPS64)
1121 val &= env->SEGMask;
1122 #endif
1123 old = env->CP0_EntryHi;
1124 env->CP0_EntryHi = val;
1125 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1126 uint32_t tcst = env->active_tc.CP0_TCStatus & ~0xff;
1127 env->active_tc.CP0_TCStatus = tcst | (val & 0xff);
1129 /* If the ASID changes, flush qemu's TLB. */
1130 if ((old & 0xFF) != (val & 0xFF))
1131 cpu_mips_tlb_flush(env, 1);
1134 void helper_mttc0_entryhi(target_ulong t0)
1136 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1137 int32_t tcstatus;
1139 env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
1140 if (other_tc == env->current_tc) {
1141 tcstatus = (env->active_tc.CP0_TCStatus & ~0xff) | (t0 & 0xff);
1142 env->active_tc.CP0_TCStatus = tcstatus;
1143 } else {
1144 tcstatus = (env->tcs[other_tc].CP0_TCStatus & ~0xff) | (t0 & 0xff);
1145 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1149 void helper_mtc0_compare (target_ulong t0)
1151 cpu_mips_store_compare(env, t0);
1154 void helper_mtc0_status (target_ulong t0)
1156 uint32_t val, old;
1157 uint32_t mask = env->CP0_Status_rw_bitmask;
1159 val = t0 & mask;
1160 old = env->CP0_Status;
1161 env->CP0_Status = (env->CP0_Status & ~mask) | val;
1162 compute_hflags(env);
1163 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1164 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1165 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1166 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1167 env->CP0_Cause);
1168 switch (env->hflags & MIPS_HFLAG_KSU) {
1169 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1170 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1171 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1172 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1175 cpu_mips_update_irq(env);
1178 void helper_mttc0_status(target_ulong t0)
1180 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1181 int32_t tcstatus = env->tcs[other_tc].CP0_TCStatus;
1183 env->CP0_Status = t0 & ~0xf1000018;
1184 tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
1185 tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1186 tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1187 if (other_tc == env->current_tc)
1188 env->active_tc.CP0_TCStatus = tcstatus;
1189 else
1190 env->tcs[other_tc].CP0_TCStatus = tcstatus;
1193 void helper_mtc0_intctl (target_ulong t0)
1195 /* vectored interrupts not implemented, no performance counters. */
1196 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
1199 void helper_mtc0_srsctl (target_ulong t0)
1201 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1202 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
1205 void helper_mtc0_cause (target_ulong t0)
1207 uint32_t mask = 0x00C00300;
1208 uint32_t old = env->CP0_Cause;
1210 if (env->insn_flags & ISA_MIPS32R2)
1211 mask |= 1 << CP0Ca_DC;
1213 env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
1215 if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1216 if (env->CP0_Cause & (1 << CP0Ca_DC))
1217 cpu_mips_stop_count(env);
1218 else
1219 cpu_mips_start_count(env);
1222 /* Handle the software interrupt as an hardware one, as they
1223 are very similar */
1224 if (t0 & CP0Ca_IP_mask) {
1225 cpu_mips_update_irq(env);
1229 void helper_mtc0_ebase (target_ulong t0)
1231 /* vectored interrupts not implemented */
1232 /* Multi-CPU not implemented */
1233 env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
1236 void helper_mtc0_config0 (target_ulong t0)
1238 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
1241 void helper_mtc0_config2 (target_ulong t0)
1243 /* tertiary/secondary caches not implemented */
1244 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1247 void helper_mtc0_watchlo (target_ulong t0, uint32_t sel)
1249 /* Watch exceptions for instructions, data loads, data stores
1250 not implemented. */
1251 env->CP0_WatchLo[sel] = (t0 & ~0x7);
1254 void helper_mtc0_watchhi (target_ulong t0, uint32_t sel)
1256 env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
1257 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
1260 void helper_mtc0_xcontext (target_ulong t0)
1262 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1263 env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
1266 void helper_mtc0_framemask (target_ulong t0)
1268 env->CP0_Framemask = t0; /* XXX */
1271 void helper_mtc0_debug (target_ulong t0)
1273 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
1274 if (t0 & (1 << CP0DB_DM))
1275 env->hflags |= MIPS_HFLAG_DM;
1276 else
1277 env->hflags &= ~MIPS_HFLAG_DM;
1280 void helper_mttc0_debug(target_ulong t0)
1282 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1283 uint32_t val = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1285 /* XXX: Might be wrong, check with EJTAG spec. */
1286 if (other_tc == env->current_tc)
1287 env->active_tc.CP0_Debug_tcstatus = val;
1288 else
1289 env->tcs[other_tc].CP0_Debug_tcstatus = val;
1290 env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1291 (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1294 void helper_mtc0_performance0 (target_ulong t0)
1296 env->CP0_Performance0 = t0 & 0x000007ff;
1299 void helper_mtc0_taglo (target_ulong t0)
1301 env->CP0_TagLo = t0 & 0xFFFFFCF6;
1304 void helper_mtc0_datalo (target_ulong t0)
1306 env->CP0_DataLo = t0; /* XXX */
1309 void helper_mtc0_taghi (target_ulong t0)
1311 env->CP0_TagHi = t0; /* XXX */
1314 void helper_mtc0_datahi (target_ulong t0)
1316 env->CP0_DataHi = t0; /* XXX */
1319 /* MIPS MT functions */
1320 target_ulong helper_mftgpr(uint32_t sel)
1322 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1324 if (other_tc == env->current_tc)
1325 return env->active_tc.gpr[sel];
1326 else
1327 return env->tcs[other_tc].gpr[sel];
1330 target_ulong helper_mftlo(uint32_t sel)
1332 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1334 if (other_tc == env->current_tc)
1335 return env->active_tc.LO[sel];
1336 else
1337 return env->tcs[other_tc].LO[sel];
1340 target_ulong helper_mfthi(uint32_t sel)
1342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1344 if (other_tc == env->current_tc)
1345 return env->active_tc.HI[sel];
1346 else
1347 return env->tcs[other_tc].HI[sel];
1350 target_ulong helper_mftacx(uint32_t sel)
1352 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1354 if (other_tc == env->current_tc)
1355 return env->active_tc.ACX[sel];
1356 else
1357 return env->tcs[other_tc].ACX[sel];
1360 target_ulong helper_mftdsp(void)
1362 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1364 if (other_tc == env->current_tc)
1365 return env->active_tc.DSPControl;
1366 else
1367 return env->tcs[other_tc].DSPControl;
1370 void helper_mttgpr(target_ulong t0, uint32_t sel)
1372 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1374 if (other_tc == env->current_tc)
1375 env->active_tc.gpr[sel] = t0;
1376 else
1377 env->tcs[other_tc].gpr[sel] = t0;
1380 void helper_mttlo(target_ulong t0, uint32_t sel)
1382 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1384 if (other_tc == env->current_tc)
1385 env->active_tc.LO[sel] = t0;
1386 else
1387 env->tcs[other_tc].LO[sel] = t0;
1390 void helper_mtthi(target_ulong t0, uint32_t sel)
1392 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1394 if (other_tc == env->current_tc)
1395 env->active_tc.HI[sel] = t0;
1396 else
1397 env->tcs[other_tc].HI[sel] = t0;
1400 void helper_mttacx(target_ulong t0, uint32_t sel)
1402 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1404 if (other_tc == env->current_tc)
1405 env->active_tc.ACX[sel] = t0;
1406 else
1407 env->tcs[other_tc].ACX[sel] = t0;
1410 void helper_mttdsp(target_ulong t0)
1412 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1414 if (other_tc == env->current_tc)
1415 env->active_tc.DSPControl = t0;
1416 else
1417 env->tcs[other_tc].DSPControl = t0;
1420 /* MIPS MT functions */
1421 target_ulong helper_dmt(target_ulong t0)
1423 // TODO
1424 t0 = 0;
1425 // rt = t0
1427 return t0;
1430 target_ulong helper_emt(target_ulong t0)
1432 // TODO
1433 t0 = 0;
1434 // rt = t0
1436 return t0;
1439 target_ulong helper_dvpe(target_ulong t0)
1441 // TODO
1442 t0 = 0;
1443 // rt = t0
1445 return t0;
1448 target_ulong helper_evpe(target_ulong t0)
1450 // TODO
1451 t0 = 0;
1452 // rt = t0
1454 return t0;
1456 #endif /* !CONFIG_USER_ONLY */
1458 void helper_fork(target_ulong t0, target_ulong t1)
1460 // t0 = rt, t1 = rs
1461 t0 = 0;
1462 // TODO: store to TC register
1465 target_ulong helper_yield(target_ulong t0)
1467 if (t0 < 0) {
1468 /* No scheduling policy implemented. */
1469 if (t0 != -2) {
1470 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1471 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1472 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1473 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1474 helper_raise_exception(EXCP_THREAD);
1477 } else if (t0 == 0) {
1478 if (0 /* TODO: TC underflow */) {
1479 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1480 helper_raise_exception(EXCP_THREAD);
1481 } else {
1482 // TODO: Deallocate TC
1484 } else if (t0 > 0) {
1485 /* Yield qualifier inputs not implemented. */
1486 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1487 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1488 helper_raise_exception(EXCP_THREAD);
1490 return env->CP0_YQMask;
1493 #ifndef CONFIG_USER_ONLY
1494 /* TLB management */
1495 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
1497 /* Flush qemu's TLB and discard all shadowed entries. */
1498 tlb_flush (env, flush_global);
1499 env->tlb->tlb_in_use = env->tlb->nb_tlb;
1502 static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
1504 /* Discard entries from env->tlb[first] onwards. */
1505 while (env->tlb->tlb_in_use > first) {
1506 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1510 static void r4k_fill_tlb (int idx)
1512 r4k_tlb_t *tlb;
1514 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1515 tlb = &env->tlb->mmu.r4k.tlb[idx];
1516 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1517 #if defined(TARGET_MIPS64)
1518 tlb->VPN &= env->SEGMask;
1519 #endif
1520 tlb->ASID = env->CP0_EntryHi & 0xFF;
1521 tlb->PageMask = env->CP0_PageMask;
1522 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1523 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1524 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1525 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1526 tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1527 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1528 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1529 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1530 tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1533 void r4k_helper_tlbwi (void)
1535 int idx;
1537 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1539 /* Discard cached TLB entries. We could avoid doing this if the
1540 tlbwi is just upgrading access permissions on the current entry;
1541 that might be a further win. */
1542 r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
1544 r4k_invalidate_tlb(env, idx, 0);
1545 r4k_fill_tlb(idx);
1548 void r4k_helper_tlbwr (void)
1550 int r = cpu_mips_get_random(env);
1552 r4k_invalidate_tlb(env, r, 1);
1553 r4k_fill_tlb(r);
1556 void r4k_helper_tlbp (void)
1558 r4k_tlb_t *tlb;
1559 target_ulong mask;
1560 target_ulong tag;
1561 target_ulong VPN;
1562 uint8_t ASID;
1563 int i;
1565 ASID = env->CP0_EntryHi & 0xFF;
1566 for (i = 0; i < env->tlb->nb_tlb; i++) {
1567 tlb = &env->tlb->mmu.r4k.tlb[i];
1568 /* 1k pages are not supported. */
1569 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1570 tag = env->CP0_EntryHi & ~mask;
1571 VPN = tlb->VPN & ~mask;
1572 /* Check ASID, virtual page number & size */
1573 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1574 /* TLB match */
1575 env->CP0_Index = i;
1576 break;
1579 if (i == env->tlb->nb_tlb) {
1580 /* No match. Discard any shadow entries, if any of them match. */
1581 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1582 tlb = &env->tlb->mmu.r4k.tlb[i];
1583 /* 1k pages are not supported. */
1584 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1585 tag = env->CP0_EntryHi & ~mask;
1586 VPN = tlb->VPN & ~mask;
1587 /* Check ASID, virtual page number & size */
1588 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1589 r4k_mips_tlb_flush_extra (env, i);
1590 break;
1594 env->CP0_Index |= 0x80000000;
1598 void r4k_helper_tlbr (void)
1600 r4k_tlb_t *tlb;
1601 uint8_t ASID;
1602 int idx;
1604 ASID = env->CP0_EntryHi & 0xFF;
1605 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1606 tlb = &env->tlb->mmu.r4k.tlb[idx];
1608 /* If this will change the current ASID, flush qemu's TLB. */
1609 if (ASID != tlb->ASID)
1610 cpu_mips_tlb_flush (env, 1);
1612 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1614 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
1615 env->CP0_PageMask = tlb->PageMask;
1616 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
1617 (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
1618 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
1619 (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
1622 void helper_tlbwi(void)
1624 env->tlb->helper_tlbwi();
1627 void helper_tlbwr(void)
1629 env->tlb->helper_tlbwr();
1632 void helper_tlbp(void)
1634 env->tlb->helper_tlbp();
1637 void helper_tlbr(void)
1639 env->tlb->helper_tlbr();
1642 /* Specials */
1643 target_ulong helper_di (void)
1645 target_ulong t0 = env->CP0_Status;
1647 env->CP0_Status = t0 & ~(1 << CP0St_IE);
1648 cpu_mips_update_irq(env);
1650 return t0;
1653 target_ulong helper_ei (void)
1655 target_ulong t0 = env->CP0_Status;
1657 env->CP0_Status = t0 | (1 << CP0St_IE);
1658 cpu_mips_update_irq(env);
1660 return t0;
1663 static void debug_pre_eret (void)
1665 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1666 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1667 env->active_tc.PC, env->CP0_EPC);
1668 if (env->CP0_Status & (1 << CP0St_ERL))
1669 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1670 if (env->hflags & MIPS_HFLAG_DM)
1671 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1672 qemu_log("\n");
1676 static void debug_post_eret (void)
1678 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1679 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
1680 env->active_tc.PC, env->CP0_EPC);
1681 if (env->CP0_Status & (1 << CP0St_ERL))
1682 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
1683 if (env->hflags & MIPS_HFLAG_DM)
1684 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
1685 switch (env->hflags & MIPS_HFLAG_KSU) {
1686 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1687 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1688 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1689 default: cpu_abort(env, "Invalid MMU mode!\n"); break;
1694 void helper_eret (void)
1696 debug_pre_eret();
1697 if (env->CP0_Status & (1 << CP0St_ERL)) {
1698 env->active_tc.PC = env->CP0_ErrorEPC;
1699 env->CP0_Status &= ~(1 << CP0St_ERL);
1700 } else {
1701 env->active_tc.PC = env->CP0_EPC;
1702 env->CP0_Status &= ~(1 << CP0St_EXL);
1704 compute_hflags(env);
1705 debug_post_eret();
1706 env->CP0_LLAddr = 1;
1709 void helper_deret (void)
1711 debug_pre_eret();
1712 env->active_tc.PC = env->CP0_DEPC;
1713 env->hflags &= MIPS_HFLAG_DM;
1714 compute_hflags(env);
1715 debug_post_eret();
1716 env->CP0_LLAddr = 1;
1718 #endif /* !CONFIG_USER_ONLY */
1720 target_ulong helper_rdhwr_cpunum(void)
1722 if ((env->hflags & MIPS_HFLAG_CP0) ||
1723 (env->CP0_HWREna & (1 << 0)))
1724 return env->CP0_EBase & 0x3ff;
1725 else
1726 helper_raise_exception(EXCP_RI);
1728 return 0;
1731 target_ulong helper_rdhwr_synci_step(void)
1733 if ((env->hflags & MIPS_HFLAG_CP0) ||
1734 (env->CP0_HWREna & (1 << 1)))
1735 return env->SYNCI_Step;
1736 else
1737 helper_raise_exception(EXCP_RI);
1739 return 0;
1742 target_ulong helper_rdhwr_cc(void)
1744 if ((env->hflags & MIPS_HFLAG_CP0) ||
1745 (env->CP0_HWREna & (1 << 2)))
1746 return env->CP0_Count;
1747 else
1748 helper_raise_exception(EXCP_RI);
1750 return 0;
1753 target_ulong helper_rdhwr_ccres(void)
1755 if ((env->hflags & MIPS_HFLAG_CP0) ||
1756 (env->CP0_HWREna & (1 << 3)))
1757 return env->CCRes;
1758 else
1759 helper_raise_exception(EXCP_RI);
1761 return 0;
1764 void helper_pmon (int function)
1766 function /= 2;
1767 switch (function) {
1768 case 2: /* TODO: char inbyte(int waitflag); */
1769 if (env->active_tc.gpr[4] == 0)
1770 env->active_tc.gpr[2] = -1;
1771 /* Fall through */
1772 case 11: /* TODO: char inbyte (void); */
1773 env->active_tc.gpr[2] = -1;
1774 break;
1775 case 3:
1776 case 12:
1777 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
1778 break;
1779 case 17:
1780 break;
1781 case 158:
1783 unsigned char *fmt = (void *)(unsigned long)env->active_tc.gpr[4];
1784 printf("%s", fmt);
1786 break;
1790 void helper_wait (void)
1792 env->halted = 1;
1793 helper_raise_exception(EXCP_HLT);
1796 #if !defined(CONFIG_USER_ONLY)
1798 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr);
1800 #define MMUSUFFIX _mmu
1801 #define ALIGNED_ONLY
1803 #define SHIFT 0
1804 #include "softmmu_template.h"
1806 #define SHIFT 1
1807 #include "softmmu_template.h"
1809 #define SHIFT 2
1810 #include "softmmu_template.h"
1812 #define SHIFT 3
1813 #include "softmmu_template.h"
1815 static void do_unaligned_access (target_ulong addr, int is_write, int is_user, void *retaddr)
1817 env->CP0_BadVAddr = addr;
1818 do_restore_state (retaddr);
1819 helper_raise_exception ((is_write == 1) ? EXCP_AdES : EXCP_AdEL);
1822 void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
1824 TranslationBlock *tb;
1825 CPUState *saved_env;
1826 unsigned long pc;
1827 int ret;
1829 /* XXX: hack to restore env in all cases, even if not called from
1830 generated code */
1831 saved_env = env;
1832 env = cpu_single_env;
1833 ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
1834 if (ret) {
1835 if (retaddr) {
1836 /* now we have a real cpu fault */
1837 pc = (unsigned long)retaddr;
1838 tb = tb_find_pc(pc);
1839 if (tb) {
1840 /* the PC is inside the translated code. It means that we have
1841 a virtual CPU fault */
1842 cpu_restore_state(tb, env, pc, NULL);
1845 helper_raise_exception_err(env->exception_index, env->error_code);
1847 env = saved_env;
1850 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
1851 int unused, int size)
1853 if (is_exec)
1854 helper_raise_exception(EXCP_IBE);
1855 else
1856 helper_raise_exception(EXCP_DBE);
1858 #endif /* !CONFIG_USER_ONLY */
1860 /* Complex FPU operations which may need stack space. */
1862 #define FLOAT_ONE32 make_float32(0x3f8 << 20)
1863 #define FLOAT_ONE64 make_float64(0x3ffULL << 52)
1864 #define FLOAT_TWO32 make_float32(1 << 30)
1865 #define FLOAT_TWO64 make_float64(1ULL << 62)
1866 #define FLOAT_QNAN32 0x7fbfffff
1867 #define FLOAT_QNAN64 0x7ff7ffffffffffffULL
1868 #define FLOAT_SNAN32 0x7fffffff
1869 #define FLOAT_SNAN64 0x7fffffffffffffffULL
1871 /* convert MIPS rounding mode in FCR31 to IEEE library */
1872 unsigned int ieee_rm[] = {
1873 float_round_nearest_even,
1874 float_round_to_zero,
1875 float_round_up,
1876 float_round_down
1879 #define RESTORE_ROUNDING_MODE \
1880 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1882 target_ulong helper_cfc1 (uint32_t reg)
1884 target_ulong t0;
1886 switch (reg) {
1887 case 0:
1888 t0 = (int32_t)env->active_fpu.fcr0;
1889 break;
1890 case 25:
1891 t0 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
1892 break;
1893 case 26:
1894 t0 = env->active_fpu.fcr31 & 0x0003f07c;
1895 break;
1896 case 28:
1897 t0 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
1898 break;
1899 default:
1900 t0 = (int32_t)env->active_fpu.fcr31;
1901 break;
1904 return t0;
1907 void helper_ctc1 (target_ulong t0, uint32_t reg)
1909 switch(reg) {
1910 case 25:
1911 if (t0 & 0xffffff00)
1912 return;
1913 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
1914 ((t0 & 0x1) << 23);
1915 break;
1916 case 26:
1917 if (t0 & 0x007c0000)
1918 return;
1919 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
1920 break;
1921 case 28:
1922 if (t0 & 0x007c0000)
1923 return;
1924 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
1925 ((t0 & 0x4) << 22);
1926 break;
1927 case 31:
1928 if (t0 & 0x007c0000)
1929 return;
1930 env->active_fpu.fcr31 = t0;
1931 break;
1932 default:
1933 return;
1935 /* set rounding mode */
1936 RESTORE_ROUNDING_MODE;
1937 set_float_exception_flags(0, &env->active_fpu.fp_status);
1938 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
1939 helper_raise_exception(EXCP_FPE);
1942 static inline char ieee_ex_to_mips(char xcpt)
1944 return (xcpt & float_flag_inexact) >> 5 |
1945 (xcpt & float_flag_underflow) >> 3 |
1946 (xcpt & float_flag_overflow) >> 1 |
1947 (xcpt & float_flag_divbyzero) << 1 |
1948 (xcpt & float_flag_invalid) << 4;
1951 static inline char mips_ex_to_ieee(char xcpt)
1953 return (xcpt & FP_INEXACT) << 5 |
1954 (xcpt & FP_UNDERFLOW) << 3 |
1955 (xcpt & FP_OVERFLOW) << 1 |
1956 (xcpt & FP_DIV0) >> 1 |
1957 (xcpt & FP_INVALID) >> 4;
1960 static inline void update_fcr31(void)
1962 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
1964 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
1965 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp)
1966 helper_raise_exception(EXCP_FPE);
1967 else
1968 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
1971 /* Float support.
1972 Single precition routines have a "s" suffix, double precision a
1973 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
1974 paired single lower "pl", paired single upper "pu". */
1976 /* unary operations, modifying fp status */
1977 uint64_t helper_float_sqrt_d(uint64_t fdt0)
1979 return float64_sqrt(fdt0, &env->active_fpu.fp_status);
1982 uint32_t helper_float_sqrt_s(uint32_t fst0)
1984 return float32_sqrt(fst0, &env->active_fpu.fp_status);
1987 uint64_t helper_float_cvtd_s(uint32_t fst0)
1989 uint64_t fdt2;
1991 set_float_exception_flags(0, &env->active_fpu.fp_status);
1992 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
1993 update_fcr31();
1994 return fdt2;
1997 uint64_t helper_float_cvtd_w(uint32_t wt0)
1999 uint64_t fdt2;
2001 set_float_exception_flags(0, &env->active_fpu.fp_status);
2002 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2003 update_fcr31();
2004 return fdt2;
2007 uint64_t helper_float_cvtd_l(uint64_t dt0)
2009 uint64_t fdt2;
2011 set_float_exception_flags(0, &env->active_fpu.fp_status);
2012 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2013 update_fcr31();
2014 return fdt2;
2017 uint64_t helper_float_cvtl_d(uint64_t fdt0)
2019 uint64_t dt2;
2021 set_float_exception_flags(0, &env->active_fpu.fp_status);
2022 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2023 update_fcr31();
2024 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2025 dt2 = FLOAT_SNAN64;
2026 return dt2;
2029 uint64_t helper_float_cvtl_s(uint32_t fst0)
2031 uint64_t dt2;
2033 set_float_exception_flags(0, &env->active_fpu.fp_status);
2034 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2035 update_fcr31();
2036 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2037 dt2 = FLOAT_SNAN64;
2038 return dt2;
2041 uint64_t helper_float_cvtps_pw(uint64_t dt0)
2043 uint32_t fst2;
2044 uint32_t fsth2;
2046 set_float_exception_flags(0, &env->active_fpu.fp_status);
2047 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2048 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2049 update_fcr31();
2050 return ((uint64_t)fsth2 << 32) | fst2;
2053 uint64_t helper_float_cvtpw_ps(uint64_t fdt0)
2055 uint32_t wt2;
2056 uint32_t wth2;
2058 set_float_exception_flags(0, &env->active_fpu.fp_status);
2059 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2060 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2061 update_fcr31();
2062 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) {
2063 wt2 = FLOAT_SNAN32;
2064 wth2 = FLOAT_SNAN32;
2066 return ((uint64_t)wth2 << 32) | wt2;
2069 uint32_t helper_float_cvts_d(uint64_t fdt0)
2071 uint32_t fst2;
2073 set_float_exception_flags(0, &env->active_fpu.fp_status);
2074 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2075 update_fcr31();
2076 return fst2;
2079 uint32_t helper_float_cvts_w(uint32_t wt0)
2081 uint32_t fst2;
2083 set_float_exception_flags(0, &env->active_fpu.fp_status);
2084 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2085 update_fcr31();
2086 return fst2;
2089 uint32_t helper_float_cvts_l(uint64_t dt0)
2091 uint32_t fst2;
2093 set_float_exception_flags(0, &env->active_fpu.fp_status);
2094 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2095 update_fcr31();
2096 return fst2;
2099 uint32_t helper_float_cvts_pl(uint32_t wt0)
2101 uint32_t wt2;
2103 set_float_exception_flags(0, &env->active_fpu.fp_status);
2104 wt2 = wt0;
2105 update_fcr31();
2106 return wt2;
2109 uint32_t helper_float_cvts_pu(uint32_t wth0)
2111 uint32_t wt2;
2113 set_float_exception_flags(0, &env->active_fpu.fp_status);
2114 wt2 = wth0;
2115 update_fcr31();
2116 return wt2;
2119 uint32_t helper_float_cvtw_s(uint32_t fst0)
2121 uint32_t wt2;
2123 set_float_exception_flags(0, &env->active_fpu.fp_status);
2124 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2125 update_fcr31();
2126 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2127 wt2 = FLOAT_SNAN32;
2128 return wt2;
2131 uint32_t helper_float_cvtw_d(uint64_t fdt0)
2133 uint32_t wt2;
2135 set_float_exception_flags(0, &env->active_fpu.fp_status);
2136 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2137 update_fcr31();
2138 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2139 wt2 = FLOAT_SNAN32;
2140 return wt2;
2143 uint64_t helper_float_roundl_d(uint64_t fdt0)
2145 uint64_t dt2;
2147 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2148 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2149 RESTORE_ROUNDING_MODE;
2150 update_fcr31();
2151 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2152 dt2 = FLOAT_SNAN64;
2153 return dt2;
2156 uint64_t helper_float_roundl_s(uint32_t fst0)
2158 uint64_t dt2;
2160 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2161 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2162 RESTORE_ROUNDING_MODE;
2163 update_fcr31();
2164 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2165 dt2 = FLOAT_SNAN64;
2166 return dt2;
2169 uint32_t helper_float_roundw_d(uint64_t fdt0)
2171 uint32_t wt2;
2173 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2174 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2175 RESTORE_ROUNDING_MODE;
2176 update_fcr31();
2177 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2178 wt2 = FLOAT_SNAN32;
2179 return wt2;
2182 uint32_t helper_float_roundw_s(uint32_t fst0)
2184 uint32_t wt2;
2186 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2187 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2188 RESTORE_ROUNDING_MODE;
2189 update_fcr31();
2190 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2191 wt2 = FLOAT_SNAN32;
2192 return wt2;
2195 uint64_t helper_float_truncl_d(uint64_t fdt0)
2197 uint64_t dt2;
2199 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2200 update_fcr31();
2201 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2202 dt2 = FLOAT_SNAN64;
2203 return dt2;
2206 uint64_t helper_float_truncl_s(uint32_t fst0)
2208 uint64_t dt2;
2210 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2211 update_fcr31();
2212 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2213 dt2 = FLOAT_SNAN64;
2214 return dt2;
2217 uint32_t helper_float_truncw_d(uint64_t fdt0)
2219 uint32_t wt2;
2221 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2222 update_fcr31();
2223 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2224 wt2 = FLOAT_SNAN32;
2225 return wt2;
2228 uint32_t helper_float_truncw_s(uint32_t fst0)
2230 uint32_t wt2;
2232 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2233 update_fcr31();
2234 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2235 wt2 = FLOAT_SNAN32;
2236 return wt2;
2239 uint64_t helper_float_ceill_d(uint64_t fdt0)
2241 uint64_t dt2;
2243 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2244 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2245 RESTORE_ROUNDING_MODE;
2246 update_fcr31();
2247 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2248 dt2 = FLOAT_SNAN64;
2249 return dt2;
2252 uint64_t helper_float_ceill_s(uint32_t fst0)
2254 uint64_t dt2;
2256 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2257 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2258 RESTORE_ROUNDING_MODE;
2259 update_fcr31();
2260 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2261 dt2 = FLOAT_SNAN64;
2262 return dt2;
2265 uint32_t helper_float_ceilw_d(uint64_t fdt0)
2267 uint32_t wt2;
2269 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2270 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2271 RESTORE_ROUNDING_MODE;
2272 update_fcr31();
2273 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2274 wt2 = FLOAT_SNAN32;
2275 return wt2;
2278 uint32_t helper_float_ceilw_s(uint32_t fst0)
2280 uint32_t wt2;
2282 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2283 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2284 RESTORE_ROUNDING_MODE;
2285 update_fcr31();
2286 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2287 wt2 = FLOAT_SNAN32;
2288 return wt2;
2291 uint64_t helper_float_floorl_d(uint64_t fdt0)
2293 uint64_t dt2;
2295 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2296 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2297 RESTORE_ROUNDING_MODE;
2298 update_fcr31();
2299 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2300 dt2 = FLOAT_SNAN64;
2301 return dt2;
2304 uint64_t helper_float_floorl_s(uint32_t fst0)
2306 uint64_t dt2;
2308 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2309 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2310 RESTORE_ROUNDING_MODE;
2311 update_fcr31();
2312 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2313 dt2 = FLOAT_SNAN64;
2314 return dt2;
2317 uint32_t helper_float_floorw_d(uint64_t fdt0)
2319 uint32_t wt2;
2321 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2322 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2323 RESTORE_ROUNDING_MODE;
2324 update_fcr31();
2325 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2326 wt2 = FLOAT_SNAN32;
2327 return wt2;
2330 uint32_t helper_float_floorw_s(uint32_t fst0)
2332 uint32_t wt2;
2334 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2335 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2336 RESTORE_ROUNDING_MODE;
2337 update_fcr31();
2338 if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID))
2339 wt2 = FLOAT_SNAN32;
2340 return wt2;
2343 /* unary operations, not modifying fp status */
2344 #define FLOAT_UNOP(name) \
2345 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2347 return float64_ ## name(fdt0); \
2349 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2351 return float32_ ## name(fst0); \
2353 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2355 uint32_t wt0; \
2356 uint32_t wth0; \
2358 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2359 wth0 = float32_ ## name(fdt0 >> 32); \
2360 return ((uint64_t)wth0 << 32) | wt0; \
2362 FLOAT_UNOP(abs)
2363 FLOAT_UNOP(chs)
2364 #undef FLOAT_UNOP
2366 /* MIPS specific unary operations */
2367 uint64_t helper_float_recip_d(uint64_t fdt0)
2369 uint64_t fdt2;
2371 set_float_exception_flags(0, &env->active_fpu.fp_status);
2372 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2373 update_fcr31();
2374 return fdt2;
2377 uint32_t helper_float_recip_s(uint32_t fst0)
2379 uint32_t fst2;
2381 set_float_exception_flags(0, &env->active_fpu.fp_status);
2382 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2383 update_fcr31();
2384 return fst2;
2387 uint64_t helper_float_rsqrt_d(uint64_t fdt0)
2389 uint64_t fdt2;
2391 set_float_exception_flags(0, &env->active_fpu.fp_status);
2392 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2393 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2394 update_fcr31();
2395 return fdt2;
2398 uint32_t helper_float_rsqrt_s(uint32_t fst0)
2400 uint32_t fst2;
2402 set_float_exception_flags(0, &env->active_fpu.fp_status);
2403 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2404 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2405 update_fcr31();
2406 return fst2;
2409 uint64_t helper_float_recip1_d(uint64_t fdt0)
2411 uint64_t fdt2;
2413 set_float_exception_flags(0, &env->active_fpu.fp_status);
2414 fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status);
2415 update_fcr31();
2416 return fdt2;
2419 uint32_t helper_float_recip1_s(uint32_t fst0)
2421 uint32_t fst2;
2423 set_float_exception_flags(0, &env->active_fpu.fp_status);
2424 fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status);
2425 update_fcr31();
2426 return fst2;
2429 uint64_t helper_float_recip1_ps(uint64_t fdt0)
2431 uint32_t fst2;
2432 uint32_t fsth2;
2434 set_float_exception_flags(0, &env->active_fpu.fp_status);
2435 fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2436 fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status);
2437 update_fcr31();
2438 return ((uint64_t)fsth2 << 32) | fst2;
2441 uint64_t helper_float_rsqrt1_d(uint64_t fdt0)
2443 uint64_t fdt2;
2445 set_float_exception_flags(0, &env->active_fpu.fp_status);
2446 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2447 fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status);
2448 update_fcr31();
2449 return fdt2;
2452 uint32_t helper_float_rsqrt1_s(uint32_t fst0)
2454 uint32_t fst2;
2456 set_float_exception_flags(0, &env->active_fpu.fp_status);
2457 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2458 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2459 update_fcr31();
2460 return fst2;
2463 uint64_t helper_float_rsqrt1_ps(uint64_t fdt0)
2465 uint32_t fst2;
2466 uint32_t fsth2;
2468 set_float_exception_flags(0, &env->active_fpu.fp_status);
2469 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2470 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
2471 fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status);
2472 fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status);
2473 update_fcr31();
2474 return ((uint64_t)fsth2 << 32) | fst2;
2477 #define FLOAT_OP(name, p) void helper_float_##name##_##p(void)
2479 /* binary operations */
2480 #define FLOAT_BINOP(name) \
2481 uint64_t helper_float_ ## name ## _d(uint64_t fdt0, uint64_t fdt1) \
2483 uint64_t dt2; \
2485 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2486 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
2487 update_fcr31(); \
2488 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2489 dt2 = FLOAT_QNAN64; \
2490 return dt2; \
2493 uint32_t helper_float_ ## name ## _s(uint32_t fst0, uint32_t fst1) \
2495 uint32_t wt2; \
2497 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2498 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2499 update_fcr31(); \
2500 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \
2501 wt2 = FLOAT_QNAN32; \
2502 return wt2; \
2505 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0, uint64_t fdt1) \
2507 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2508 uint32_t fsth0 = fdt0 >> 32; \
2509 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2510 uint32_t fsth1 = fdt1 >> 32; \
2511 uint32_t wt2; \
2512 uint32_t wth2; \
2514 set_float_exception_flags(0, &env->active_fpu.fp_status); \
2515 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
2516 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
2517 update_fcr31(); \
2518 if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \
2519 wt2 = FLOAT_QNAN32; \
2520 wth2 = FLOAT_QNAN32; \
2522 return ((uint64_t)wth2 << 32) | wt2; \
2525 FLOAT_BINOP(add)
2526 FLOAT_BINOP(sub)
2527 FLOAT_BINOP(mul)
2528 FLOAT_BINOP(div)
2529 #undef FLOAT_BINOP
2531 /* ternary operations */
2532 #define FLOAT_TERNOP(name1, name2) \
2533 uint64_t helper_float_ ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2534 uint64_t fdt2) \
2536 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2537 return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2540 uint32_t helper_float_ ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2541 uint32_t fst2) \
2543 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2544 return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2547 uint64_t helper_float_ ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1, \
2548 uint64_t fdt2) \
2550 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2551 uint32_t fsth0 = fdt0 >> 32; \
2552 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2553 uint32_t fsth1 = fdt1 >> 32; \
2554 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2555 uint32_t fsth2 = fdt2 >> 32; \
2557 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2558 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2559 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2560 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2561 return ((uint64_t)fsth2 << 32) | fst2; \
2564 FLOAT_TERNOP(mul, add)
2565 FLOAT_TERNOP(mul, sub)
2566 #undef FLOAT_TERNOP
2568 /* negated ternary operations */
2569 #define FLOAT_NTERNOP(name1, name2) \
2570 uint64_t helper_float_n ## name1 ## name2 ## _d(uint64_t fdt0, uint64_t fdt1, \
2571 uint64_t fdt2) \
2573 fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \
2574 fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \
2575 return float64_chs(fdt2); \
2578 uint32_t helper_float_n ## name1 ## name2 ## _s(uint32_t fst0, uint32_t fst1, \
2579 uint32_t fst2) \
2581 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2582 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2583 return float32_chs(fst2); \
2586 uint64_t helper_float_n ## name1 ## name2 ## _ps(uint64_t fdt0, uint64_t fdt1,\
2587 uint64_t fdt2) \
2589 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
2590 uint32_t fsth0 = fdt0 >> 32; \
2591 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
2592 uint32_t fsth1 = fdt1 >> 32; \
2593 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
2594 uint32_t fsth2 = fdt2 >> 32; \
2596 fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \
2597 fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \
2598 fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \
2599 fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \
2600 fst2 = float32_chs(fst2); \
2601 fsth2 = float32_chs(fsth2); \
2602 return ((uint64_t)fsth2 << 32) | fst2; \
2605 FLOAT_NTERNOP(mul, add)
2606 FLOAT_NTERNOP(mul, sub)
2607 #undef FLOAT_NTERNOP
2609 /* MIPS specific binary operations */
2610 uint64_t helper_float_recip2_d(uint64_t fdt0, uint64_t fdt2)
2612 set_float_exception_flags(0, &env->active_fpu.fp_status);
2613 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2614 fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status));
2615 update_fcr31();
2616 return fdt2;
2619 uint32_t helper_float_recip2_s(uint32_t fst0, uint32_t fst2)
2621 set_float_exception_flags(0, &env->active_fpu.fp_status);
2622 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2623 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2624 update_fcr31();
2625 return fst2;
2628 uint64_t helper_float_recip2_ps(uint64_t fdt0, uint64_t fdt2)
2630 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2631 uint32_t fsth0 = fdt0 >> 32;
2632 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2633 uint32_t fsth2 = fdt2 >> 32;
2635 set_float_exception_flags(0, &env->active_fpu.fp_status);
2636 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2637 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2638 fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status));
2639 fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status));
2640 update_fcr31();
2641 return ((uint64_t)fsth2 << 32) | fst2;
2644 uint64_t helper_float_rsqrt2_d(uint64_t fdt0, uint64_t fdt2)
2646 set_float_exception_flags(0, &env->active_fpu.fp_status);
2647 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
2648 fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status);
2649 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
2650 update_fcr31();
2651 return fdt2;
2654 uint32_t helper_float_rsqrt2_s(uint32_t fst0, uint32_t fst2)
2656 set_float_exception_flags(0, &env->active_fpu.fp_status);
2657 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2658 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2659 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2660 update_fcr31();
2661 return fst2;
2664 uint64_t helper_float_rsqrt2_ps(uint64_t fdt0, uint64_t fdt2)
2666 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2667 uint32_t fsth0 = fdt0 >> 32;
2668 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
2669 uint32_t fsth2 = fdt2 >> 32;
2671 set_float_exception_flags(0, &env->active_fpu.fp_status);
2672 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
2673 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
2674 fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status);
2675 fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status);
2676 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
2677 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
2678 update_fcr31();
2679 return ((uint64_t)fsth2 << 32) | fst2;
2682 uint64_t helper_float_addr_ps(uint64_t fdt0, uint64_t fdt1)
2684 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2685 uint32_t fsth0 = fdt0 >> 32;
2686 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2687 uint32_t fsth1 = fdt1 >> 32;
2688 uint32_t fst2;
2689 uint32_t fsth2;
2691 set_float_exception_flags(0, &env->active_fpu.fp_status);
2692 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
2693 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
2694 update_fcr31();
2695 return ((uint64_t)fsth2 << 32) | fst2;
2698 uint64_t helper_float_mulr_ps(uint64_t fdt0, uint64_t fdt1)
2700 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
2701 uint32_t fsth0 = fdt0 >> 32;
2702 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
2703 uint32_t fsth1 = fdt1 >> 32;
2704 uint32_t fst2;
2705 uint32_t fsth2;
2707 set_float_exception_flags(0, &env->active_fpu.fp_status);
2708 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
2709 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
2710 update_fcr31();
2711 return ((uint64_t)fsth2 << 32) | fst2;
2714 /* compare operations */
2715 #define FOP_COND_D(op, cond) \
2716 void helper_cmp_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2718 int c = cond; \
2719 update_fcr31(); \
2720 if (c) \
2721 SET_FP_COND(cc, env->active_fpu); \
2722 else \
2723 CLEAR_FP_COND(cc, env->active_fpu); \
2725 void helper_cmpabs_d_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2727 int c; \
2728 fdt0 = float64_abs(fdt0); \
2729 fdt1 = float64_abs(fdt1); \
2730 c = cond; \
2731 update_fcr31(); \
2732 if (c) \
2733 SET_FP_COND(cc, env->active_fpu); \
2734 else \
2735 CLEAR_FP_COND(cc, env->active_fpu); \
2738 static int float64_is_unordered(int sig, float64 a, float64 b STATUS_PARAM)
2740 if (float64_is_signaling_nan(a) ||
2741 float64_is_signaling_nan(b) ||
2742 (sig && (float64_is_nan(a) || float64_is_nan(b)))) {
2743 float_raise(float_flag_invalid, status);
2744 return 1;
2745 } else if (float64_is_nan(a) || float64_is_nan(b)) {
2746 return 1;
2747 } else {
2748 return 0;
2752 /* NOTE: the comma operator will make "cond" to eval to false,
2753 * but float*_is_unordered() is still called. */
2754 FOP_COND_D(f, (float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2755 FOP_COND_D(un, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status))
2756 FOP_COND_D(eq, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2757 FOP_COND_D(ueq, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2758 FOP_COND_D(olt, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2759 FOP_COND_D(ult, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2760 FOP_COND_D(ole, !float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2761 FOP_COND_D(ule, float64_is_unordered(0, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2762 /* NOTE: the comma operator will make "cond" to eval to false,
2763 * but float*_is_unordered() is still called. */
2764 FOP_COND_D(sf, (float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status), 0))
2765 FOP_COND_D(ngle,float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status))
2766 FOP_COND_D(seq, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2767 FOP_COND_D(ngl, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
2768 FOP_COND_D(lt, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2769 FOP_COND_D(nge, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
2770 FOP_COND_D(le, !float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) && float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2771 FOP_COND_D(ngt, float64_is_unordered(1, fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
2773 #define FOP_COND_S(op, cond) \
2774 void helper_cmp_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2776 int c = cond; \
2777 update_fcr31(); \
2778 if (c) \
2779 SET_FP_COND(cc, env->active_fpu); \
2780 else \
2781 CLEAR_FP_COND(cc, env->active_fpu); \
2783 void helper_cmpabs_s_ ## op (uint32_t fst0, uint32_t fst1, int cc) \
2785 int c; \
2786 fst0 = float32_abs(fst0); \
2787 fst1 = float32_abs(fst1); \
2788 c = cond; \
2789 update_fcr31(); \
2790 if (c) \
2791 SET_FP_COND(cc, env->active_fpu); \
2792 else \
2793 CLEAR_FP_COND(cc, env->active_fpu); \
2796 static flag float32_is_unordered(int sig, float32 a, float32 b STATUS_PARAM)
2798 if (float32_is_signaling_nan(a) ||
2799 float32_is_signaling_nan(b) ||
2800 (sig && (float32_is_nan(a) || float32_is_nan(b)))) {
2801 float_raise(float_flag_invalid, status);
2802 return 1;
2803 } else if (float32_is_nan(a) || float32_is_nan(b)) {
2804 return 1;
2805 } else {
2806 return 0;
2810 /* NOTE: the comma operator will make "cond" to eval to false,
2811 * but float*_is_unordered() is still called. */
2812 FOP_COND_S(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0))
2813 FOP_COND_S(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status))
2814 FOP_COND_S(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2815 FOP_COND_S(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2816 FOP_COND_S(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2817 FOP_COND_S(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2818 FOP_COND_S(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2819 FOP_COND_S(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2820 /* NOTE: the comma operator will make "cond" to eval to false,
2821 * but float*_is_unordered() is still called. */
2822 FOP_COND_S(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0))
2823 FOP_COND_S(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status))
2824 FOP_COND_S(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2825 FOP_COND_S(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
2826 FOP_COND_S(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2827 FOP_COND_S(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
2828 FOP_COND_S(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status))
2829 FOP_COND_S(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
2831 #define FOP_COND_PS(op, condl, condh) \
2832 void helper_cmp_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2834 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2835 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2836 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2837 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2838 int cl = condl; \
2839 int ch = condh; \
2841 update_fcr31(); \
2842 if (cl) \
2843 SET_FP_COND(cc, env->active_fpu); \
2844 else \
2845 CLEAR_FP_COND(cc, env->active_fpu); \
2846 if (ch) \
2847 SET_FP_COND(cc + 1, env->active_fpu); \
2848 else \
2849 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2851 void helper_cmpabs_ps_ ## op (uint64_t fdt0, uint64_t fdt1, int cc) \
2853 uint32_t fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
2854 uint32_t fsth0 = float32_abs(fdt0 >> 32); \
2855 uint32_t fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
2856 uint32_t fsth1 = float32_abs(fdt1 >> 32); \
2857 int cl = condl; \
2858 int ch = condh; \
2860 update_fcr31(); \
2861 if (cl) \
2862 SET_FP_COND(cc, env->active_fpu); \
2863 else \
2864 CLEAR_FP_COND(cc, env->active_fpu); \
2865 if (ch) \
2866 SET_FP_COND(cc + 1, env->active_fpu); \
2867 else \
2868 CLEAR_FP_COND(cc + 1, env->active_fpu); \
2871 /* NOTE: the comma operator will make "cond" to eval to false,
2872 * but float*_is_unordered() is still called. */
2873 FOP_COND_PS(f, (float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status), 0),
2874 (float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2875 FOP_COND_PS(un, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status),
2876 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status))
2877 FOP_COND_PS(eq, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2878 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2879 FOP_COND_PS(ueq, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2880 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2881 FOP_COND_PS(olt, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2882 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2883 FOP_COND_PS(ult, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2884 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2885 FOP_COND_PS(ole, !float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2886 !float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2887 FOP_COND_PS(ule, float32_is_unordered(0, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2888 float32_is_unordered(0, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2889 /* NOTE: the comma operator will make "cond" to eval to false,
2890 * but float*_is_unordered() is still called. */
2891 FOP_COND_PS(sf, (float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status), 0),
2892 (float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status), 0))
2893 FOP_COND_PS(ngle,float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status),
2894 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status))
2895 FOP_COND_PS(seq, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2896 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2897 FOP_COND_PS(ngl, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
2898 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
2899 FOP_COND_PS(lt, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2900 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2901 FOP_COND_PS(nge, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
2902 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
2903 FOP_COND_PS(le, !float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) && float32_le(fst0, fst1, &env->active_fpu.fp_status),
2904 !float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) && float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
2905 FOP_COND_PS(ngt, float32_is_unordered(1, fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
2906 float32_is_unordered(1, fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))