Fix GPE registers read/write handling. (Gleb Natapov)
[sniper_test.git] / cache-utils.c
blob45d62c91c5030393aa1b2cd4838eaee88cfda746
1 #include "cache-utils.h"
3 #if defined(_ARCH_PPC)
4 struct qemu_cache_conf qemu_cache_conf = {
5 .dcache_bsize = 16,
6 .icache_bsize = 16
7 };
9 #if defined _AIX
10 #include <sys/systemcfg.h>
12 static void ppc_init_cacheline_sizes(void)
14 qemu_cache_conf.icache_bsize = _system_configuration.icache_line;
15 qemu_cache_conf.dcache_bsize = _system_configuration.dcache_line;
18 #elif defined __linux__
20 #define QEMU_AT_NULL 0
21 #define QEMU_AT_DCACHEBSIZE 19
22 #define QEMU_AT_ICACHEBSIZE 20
24 static void ppc_init_cacheline_sizes(char **envp)
26 unsigned long *auxv;
28 while (*envp++);
30 for (auxv = (unsigned long *) envp; *auxv != QEMU_AT_NULL; auxv += 2) {
31 switch (*auxv) {
32 case QEMU_AT_DCACHEBSIZE: qemu_cache_conf.dcache_bsize = auxv[1]; break;
33 case QEMU_AT_ICACHEBSIZE: qemu_cache_conf.icache_bsize = auxv[1]; break;
34 default: break;
39 #elif defined __APPLE__
40 #include <stdio.h>
41 #include <sys/types.h>
42 #include <sys/sysctl.h>
44 static void ppc_init_cacheline_sizes(void)
46 size_t len;
47 unsigned cacheline;
48 int name[2] = { CTL_HW, HW_CACHELINE };
50 len = sizeof(cacheline);
51 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
52 perror("sysctl CTL_HW HW_CACHELINE failed");
53 } else {
54 qemu_cache_conf.dcache_bsize = cacheline;
55 qemu_cache_conf.icache_bsize = cacheline;
58 #endif
60 #ifdef __linux__
61 void qemu_cache_utils_init(char **envp)
63 ppc_init_cacheline_sizes(envp);
65 #else
66 void qemu_cache_utils_init(char **envp)
68 (void) envp;
69 ppc_init_cacheline_sizes();
71 #endif
73 #endif /* _ARCH_PPC */