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DisplayAllocator interface (Stefano Stabellini)
[sniper_test.git] / hw / cirrus_vga.c
blobec0297fc583e455af478100b33ac92e52fe4019e
1 /*
2 * QEMU Cirrus CLGD 54xx VGA Emulator.
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 * Copyright (c) 2004 Makoto Suzuki (suzu)
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * Reference: Finn Thogersons' VGADOC4b
27 * available at http://home.worldonline.dk/~finth/
28 */
29 #include "hw.h"
30 #include "pc.h"
31 #include "pci.h"
32 #include "console.h"
33 #include "vga_int.h"
34 #include "kvm.h"
35
36 /*
37 * TODO:
38 * - destination write mask support not complete (bits 5..7)
39 * - optimize linear mappings
40 * - optimize bitblt functions
41 */
42
43 //#define DEBUG_CIRRUS
44 //#define DEBUG_BITBLT
45
46 /***************************************
47 *
48 * definitions
49 *
50 ***************************************/
51
52 #define qemu_MIN(a,b) ((a) < (b) ? (a) : (b))
53
54 // ID
55 #define CIRRUS_ID_CLGD5422 (0x23<<2)
56 #define CIRRUS_ID_CLGD5426 (0x24<<2)
57 #define CIRRUS_ID_CLGD5424 (0x25<<2)
58 #define CIRRUS_ID_CLGD5428 (0x26<<2)
59 #define CIRRUS_ID_CLGD5430 (0x28<<2)
60 #define CIRRUS_ID_CLGD5434 (0x2A<<2)
61 #define CIRRUS_ID_CLGD5436 (0x2B<<2)
62 #define CIRRUS_ID_CLGD5446 (0x2E<<2)
63
64 // sequencer 0x07
65 #define CIRRUS_SR7_BPP_VGA 0x00
66 #define CIRRUS_SR7_BPP_SVGA 0x01
67 #define CIRRUS_SR7_BPP_MASK 0x0e
68 #define CIRRUS_SR7_BPP_8 0x00
69 #define CIRRUS_SR7_BPP_16_DOUBLEVCLK 0x02
70 #define CIRRUS_SR7_BPP_24 0x04
71 #define CIRRUS_SR7_BPP_16 0x06
72 #define CIRRUS_SR7_BPP_32 0x08
73 #define CIRRUS_SR7_ISAADDR_MASK 0xe0
74
75 // sequencer 0x0f
76 #define CIRRUS_MEMSIZE_512k 0x08
77 #define CIRRUS_MEMSIZE_1M 0x10
78 #define CIRRUS_MEMSIZE_2M 0x18
79 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.
80
81 // sequencer 0x12
82 #define CIRRUS_CURSOR_SHOW 0x01
83 #define CIRRUS_CURSOR_HIDDENPEL 0x02
84 #define CIRRUS_CURSOR_LARGE 0x04 // 64x64 if set, 32x32 if clear
85
86 // sequencer 0x17
87 #define CIRRUS_BUSTYPE_VLBFAST 0x10
88 #define CIRRUS_BUSTYPE_PCI 0x20
89 #define CIRRUS_BUSTYPE_VLBSLOW 0x30
90 #define CIRRUS_BUSTYPE_ISA 0x38
91 #define CIRRUS_MMIO_ENABLE 0x04
92 #define CIRRUS_MMIO_USE_PCIADDR 0x40 // 0xb8000 if cleared.
93 #define CIRRUS_MEMSIZEEXT_DOUBLE 0x80
94
95 // control 0x0b
96 #define CIRRUS_BANKING_DUAL 0x01
97 #define CIRRUS_BANKING_GRANULARITY_16K 0x20 // set:16k, clear:4k
98
99 // control 0x30
100 #define CIRRUS_BLTMODE_BACKWARDS 0x01
101 #define CIRRUS_BLTMODE_MEMSYSDEST 0x02
102 #define CIRRUS_BLTMODE_MEMSYSSRC 0x04
103 #define CIRRUS_BLTMODE_TRANSPARENTCOMP 0x08
104 #define CIRRUS_BLTMODE_PATTERNCOPY 0x40
105 #define CIRRUS_BLTMODE_COLOREXPAND 0x80
106 #define CIRRUS_BLTMODE_PIXELWIDTHMASK 0x30
107 #define CIRRUS_BLTMODE_PIXELWIDTH8 0x00
108 #define CIRRUS_BLTMODE_PIXELWIDTH16 0x10
109 #define CIRRUS_BLTMODE_PIXELWIDTH24 0x20
110 #define CIRRUS_BLTMODE_PIXELWIDTH32 0x30
111
112 // control 0x31
113 #define CIRRUS_BLT_BUSY 0x01
114 #define CIRRUS_BLT_START 0x02
115 #define CIRRUS_BLT_RESET 0x04
116 #define CIRRUS_BLT_FIFOUSED 0x10
117 #define CIRRUS_BLT_AUTOSTART 0x80
118
119 // control 0x32
120 #define CIRRUS_ROP_0 0x00
121 #define CIRRUS_ROP_SRC_AND_DST 0x05
122 #define CIRRUS_ROP_NOP 0x06
123 #define CIRRUS_ROP_SRC_AND_NOTDST 0x09
124 #define CIRRUS_ROP_NOTDST 0x0b
125 #define CIRRUS_ROP_SRC 0x0d
126 #define CIRRUS_ROP_1 0x0e
127 #define CIRRUS_ROP_NOTSRC_AND_DST 0x50
128 #define CIRRUS_ROP_SRC_XOR_DST 0x59
129 #define CIRRUS_ROP_SRC_OR_DST 0x6d
130 #define CIRRUS_ROP_NOTSRC_OR_NOTDST 0x90
131 #define CIRRUS_ROP_SRC_NOTXOR_DST 0x95
132 #define CIRRUS_ROP_SRC_OR_NOTDST 0xad
133 #define CIRRUS_ROP_NOTSRC 0xd0
134 #define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
135 #define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
136
137 #define CIRRUS_ROP_NOP_INDEX 2
138 #define CIRRUS_ROP_SRC_INDEX 5
139
140 // control 0x33
141 #define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
142 #define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
143 #define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
144
145 // memory-mapped IO
146 #define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
147 #define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
148 #define CIRRUS_MMIO_BLTWIDTH 0x08 // word
149 #define CIRRUS_MMIO_BLTHEIGHT 0x0a // word
150 #define CIRRUS_MMIO_BLTDESTPITCH 0x0c // word
151 #define CIRRUS_MMIO_BLTSRCPITCH 0x0e // word
152 #define CIRRUS_MMIO_BLTDESTADDR 0x10 // dword
153 #define CIRRUS_MMIO_BLTSRCADDR 0x14 // dword
154 #define CIRRUS_MMIO_BLTWRITEMASK 0x17 // byte
155 #define CIRRUS_MMIO_BLTMODE 0x18 // byte
156 #define CIRRUS_MMIO_BLTROP 0x1a // byte
157 #define CIRRUS_MMIO_BLTMODEEXT 0x1b // byte
158 #define CIRRUS_MMIO_BLTTRANSPARENTCOLOR 0x1c // word?
159 #define CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK 0x20 // word?
160 #define CIRRUS_MMIO_LINEARDRAW_START_X 0x24 // word
161 #define CIRRUS_MMIO_LINEARDRAW_START_Y 0x26 // word
162 #define CIRRUS_MMIO_LINEARDRAW_END_X 0x28 // word
163 #define CIRRUS_MMIO_LINEARDRAW_END_Y 0x2a // word
164 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_INC 0x2c // byte
165 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ROLLOVER 0x2d // byte
166 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_MASK 0x2e // byte
167 #define CIRRUS_MMIO_LINEARDRAW_LINESTYLE_ACCUM 0x2f // byte
168 #define CIRRUS_MMIO_BRESENHAM_K1 0x30 // word
169 #define CIRRUS_MMIO_BRESENHAM_K3 0x32 // word
170 #define CIRRUS_MMIO_BRESENHAM_ERROR 0x34 // word
171 #define CIRRUS_MMIO_BRESENHAM_DELTA_MAJOR 0x36 // word
172 #define CIRRUS_MMIO_BRESENHAM_DIRECTION 0x38 // byte
173 #define CIRRUS_MMIO_LINEDRAW_MODE 0x39 // byte
174 #define CIRRUS_MMIO_BLTSTATUS 0x40 // byte
175
176 // PCI 0x02: device
177 #define PCI_DEVICE_CLGD5462 0x00d0
178 #define PCI_DEVICE_CLGD5465 0x00d6
179
180 // PCI 0x04: command(word), 0x06(word): status
181 #define PCI_COMMAND_IOACCESS 0x0001
182 #define PCI_COMMAND_MEMACCESS 0x0002
183 #define PCI_COMMAND_BUSMASTER 0x0004
184 #define PCI_COMMAND_SPECIALCYCLE 0x0008
185 #define PCI_COMMAND_MEMWRITEINVALID 0x0010
186 #define PCI_COMMAND_PALETTESNOOPING 0x0020
187 #define PCI_COMMAND_PARITYDETECTION 0x0040
188 #define PCI_COMMAND_ADDRESSDATASTEPPING 0x0080
189 #define PCI_COMMAND_SERR 0x0100
190 #define PCI_COMMAND_BACKTOBACKTRANS 0x0200
191 // PCI 0x08, 0xff000000 (0x09-0x0b:class,0x08:rev)
192 #define PCI_CLASS_BASE_DISPLAY 0x03
193 // PCI 0x08, 0x00ff0000
194 #define PCI_CLASS_SUB_VGA 0x00
195 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
196 #define PCI_CLASS_HEADERTYPE_00h 0x00
197 // 0x10-0x3f (headertype 00h)
198 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
199 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
200 #define PCI_MAP_MEM 0x0
201 #define PCI_MAP_IO 0x1
202 #define PCI_MAP_MEM_ADDR_MASK (~0xf)
203 #define PCI_MAP_IO_ADDR_MASK (~0x3)
204 #define PCI_MAP_MEMFLAGS_32BIT 0x0
205 #define PCI_MAP_MEMFLAGS_32BIT_1M 0x1
206 #define PCI_MAP_MEMFLAGS_64BIT 0x4
207 #define PCI_MAP_MEMFLAGS_CACHEABLE 0x8
208 // PCI 0x28: cardbus CIS pointer
209 // PCI 0x2c: subsystem vendor id, 0x2e: subsystem id
210 // PCI 0x30: expansion ROM base address
211 #define PCI_ROMBIOS_ENABLED 0x1
212 // PCI 0x34: 0xffffff00=reserved, 0x000000ff=capabilities pointer
213 // PCI 0x38: reserved
214 // PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
215
216 #define CIRRUS_PNPMMIO_SIZE 0x1000
217
218
219 /* I/O and memory hook */
220 #define CIRRUS_HOOK_NOT_HANDLED 0
221 #define CIRRUS_HOOK_HANDLED 1
222
223 #define ABS(a) ((signed)(a) > 0 ? a : -a)
224
225 #define BLTUNSAFE(s) \
226 ( \
227 ( /* check dst is within bounds */ \
228 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_dstpitch) \
229 + ((s)->cirrus_blt_dstaddr & (s)->cirrus_addr_mask) > \
230 (s)->vram_size \
231 ) || \
232 ( /* check src is within bounds */ \
233 (s)->cirrus_blt_height * ABS((s)->cirrus_blt_srcpitch) \
234 + ((s)->cirrus_blt_srcaddr & (s)->cirrus_addr_mask) > \
235 (s)->vram_size \
236 ) \
237 )
238
239 struct CirrusVGAState;
240 typedef void (*cirrus_bitblt_rop_t) (struct CirrusVGAState *s,
241 uint8_t * dst, const uint8_t * src,
242 int dstpitch, int srcpitch,
243 int bltwidth, int bltheight);
244 typedef void (*cirrus_fill_t)(struct CirrusVGAState *s,
245 uint8_t *dst, int dst_pitch, int width, int height);
246
247 typedef struct CirrusVGAState {
248 VGA_STATE_COMMON
249
250 int cirrus_linear_io_addr;
251 int cirrus_linear_bitblt_io_addr;
252 int cirrus_mmio_io_addr;
253 uint32_t cirrus_addr_mask;
254 uint32_t linear_mmio_mask;
255 uint8_t cirrus_shadow_gr0;
256 uint8_t cirrus_shadow_gr1;
257 uint8_t cirrus_hidden_dac_lockindex;
258 uint8_t cirrus_hidden_dac_data;
259 uint32_t cirrus_bank_base[2];
260 uint32_t cirrus_bank_limit[2];
261 uint8_t cirrus_hidden_palette[48];
262 uint32_t hw_cursor_x;
263 uint32_t hw_cursor_y;
264 int cirrus_blt_pixelwidth;
265 int cirrus_blt_width;
266 int cirrus_blt_height;
267 int cirrus_blt_dstpitch;
268 int cirrus_blt_srcpitch;
269 uint32_t cirrus_blt_fgcol;
270 uint32_t cirrus_blt_bgcol;
271 uint32_t cirrus_blt_dstaddr;
272 uint32_t cirrus_blt_srcaddr;
273 uint8_t cirrus_blt_mode;
274 uint8_t cirrus_blt_modeext;
275 cirrus_bitblt_rop_t cirrus_rop;
276 #define CIRRUS_BLTBUFSIZE (2048 * 4) /* one line width */
277 uint8_t cirrus_bltbuf[CIRRUS_BLTBUFSIZE];
278 uint8_t *cirrus_srcptr;
279 uint8_t *cirrus_srcptr_end;
280 uint32_t cirrus_srccounter;
281 /* hwcursor display state */
282 int last_hw_cursor_size;
283 int last_hw_cursor_x;
284 int last_hw_cursor_y;
285 int last_hw_cursor_y_start;
286 int last_hw_cursor_y_end;
287 int real_vram_size; /* XXX: suppress that */
288 CPUWriteMemoryFunc **cirrus_linear_write;
289 int device_id;
290 int bustype;
291 } CirrusVGAState;
292
293 typedef struct PCICirrusVGAState {
294 PCIDevice dev;
295 CirrusVGAState cirrus_vga;
296 } PCICirrusVGAState;
297
298 static uint8_t rop_to_index[256];
299
300 /***************************************
301 *
302 * prototypes.
303 *
304 ***************************************/
305
306
307 static void cirrus_bitblt_reset(CirrusVGAState *s);
308 static void cirrus_update_memory_access(CirrusVGAState *s);
309
310 /***************************************
311 *
312 * raster operations
313 *
314 ***************************************/
315
316 static void cirrus_bitblt_rop_nop(CirrusVGAState *s,
317 uint8_t *dst,const uint8_t *src,
318 int dstpitch,int srcpitch,
319 int bltwidth,int bltheight)
320 {
321 }
322
323 static void cirrus_bitblt_fill_nop(CirrusVGAState *s,
324 uint8_t *dst,
325 int dstpitch, int bltwidth,int bltheight)
326 {
327 }
328
329 #define ROP_NAME 0
330 #define ROP_OP(d, s) d = 0
331 #include "cirrus_vga_rop.h"
332
333 #define ROP_NAME src_and_dst
334 #define ROP_OP(d, s) d = (s) & (d)
335 #include "cirrus_vga_rop.h"
336
337 #define ROP_NAME src_and_notdst
338 #define ROP_OP(d, s) d = (s) & (~(d))
339 #include "cirrus_vga_rop.h"
340
341 #define ROP_NAME notdst
342 #define ROP_OP(d, s) d = ~(d)
343 #include "cirrus_vga_rop.h"
344
345 #define ROP_NAME src
346 #define ROP_OP(d, s) d = s
347 #include "cirrus_vga_rop.h"
348
349 #define ROP_NAME 1
350 #define ROP_OP(d, s) d = ~0
351 #include "cirrus_vga_rop.h"
352
353 #define ROP_NAME notsrc_and_dst
354 #define ROP_OP(d, s) d = (~(s)) & (d)
355 #include "cirrus_vga_rop.h"
356
357 #define ROP_NAME src_xor_dst
358 #define ROP_OP(d, s) d = (s) ^ (d)
359 #include "cirrus_vga_rop.h"
360
361 #define ROP_NAME src_or_dst
362 #define ROP_OP(d, s) d = (s) | (d)
363 #include "cirrus_vga_rop.h"
364
365 #define ROP_NAME notsrc_or_notdst
366 #define ROP_OP(d, s) d = (~(s)) | (~(d))
367 #include "cirrus_vga_rop.h"
368
369 #define ROP_NAME src_notxor_dst
370 #define ROP_OP(d, s) d = ~((s) ^ (d))
371 #include "cirrus_vga_rop.h"
372
373 #define ROP_NAME src_or_notdst
374 #define ROP_OP(d, s) d = (s) | (~(d))
375 #include "cirrus_vga_rop.h"
376
377 #define ROP_NAME notsrc
378 #define ROP_OP(d, s) d = (~(s))
379 #include "cirrus_vga_rop.h"
380
381 #define ROP_NAME notsrc_or_dst
382 #define ROP_OP(d, s) d = (~(s)) | (d)
383 #include "cirrus_vga_rop.h"
384
385 #define ROP_NAME notsrc_and_notdst
386 #define ROP_OP(d, s) d = (~(s)) & (~(d))
387 #include "cirrus_vga_rop.h"
388
389 static const cirrus_bitblt_rop_t cirrus_fwd_rop[16] = {
390 cirrus_bitblt_rop_fwd_0,
391 cirrus_bitblt_rop_fwd_src_and_dst,
392 cirrus_bitblt_rop_nop,
393 cirrus_bitblt_rop_fwd_src_and_notdst,
394 cirrus_bitblt_rop_fwd_notdst,
395 cirrus_bitblt_rop_fwd_src,
396 cirrus_bitblt_rop_fwd_1,
397 cirrus_bitblt_rop_fwd_notsrc_and_dst,
398 cirrus_bitblt_rop_fwd_src_xor_dst,
399 cirrus_bitblt_rop_fwd_src_or_dst,
400 cirrus_bitblt_rop_fwd_notsrc_or_notdst,
401 cirrus_bitblt_rop_fwd_src_notxor_dst,
402 cirrus_bitblt_rop_fwd_src_or_notdst,
403 cirrus_bitblt_rop_fwd_notsrc,
404 cirrus_bitblt_rop_fwd_notsrc_or_dst,
405 cirrus_bitblt_rop_fwd_notsrc_and_notdst,
406 };
407
408 static const cirrus_bitblt_rop_t cirrus_bkwd_rop[16] = {
409 cirrus_bitblt_rop_bkwd_0,
410 cirrus_bitblt_rop_bkwd_src_and_dst,
411 cirrus_bitblt_rop_nop,
412 cirrus_bitblt_rop_bkwd_src_and_notdst,
413 cirrus_bitblt_rop_bkwd_notdst,
414 cirrus_bitblt_rop_bkwd_src,
415 cirrus_bitblt_rop_bkwd_1,
416 cirrus_bitblt_rop_bkwd_notsrc_and_dst,
417 cirrus_bitblt_rop_bkwd_src_xor_dst,
418 cirrus_bitblt_rop_bkwd_src_or_dst,
419 cirrus_bitblt_rop_bkwd_notsrc_or_notdst,
420 cirrus_bitblt_rop_bkwd_src_notxor_dst,
421 cirrus_bitblt_rop_bkwd_src_or_notdst,
422 cirrus_bitblt_rop_bkwd_notsrc,
423 cirrus_bitblt_rop_bkwd_notsrc_or_dst,
424 cirrus_bitblt_rop_bkwd_notsrc_and_notdst,
425 };
426
427 #define TRANSP_ROP(name) {\
428 name ## _8,\
429 name ## _16,\
430 }
431 #define TRANSP_NOP(func) {\
432 func,\
433 func,\
434 }
435
436 static const cirrus_bitblt_rop_t cirrus_fwd_transp_rop[16][2] = {
437 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_0),
438 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_dst),
439 TRANSP_NOP(cirrus_bitblt_rop_nop),
440 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_and_notdst),
441 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notdst),
442 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src),
443 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_1),
444 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_dst),
445 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_xor_dst),
446 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_dst),
447 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_notdst),
448 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_notxor_dst),
449 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_src_or_notdst),
450 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc),
451 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_or_dst),
452 TRANSP_ROP(cirrus_bitblt_rop_fwd_transp_notsrc_and_notdst),
453 };
454
455 static const cirrus_bitblt_rop_t cirrus_bkwd_transp_rop[16][2] = {
456 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_0),
457 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_dst),
458 TRANSP_NOP(cirrus_bitblt_rop_nop),
459 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_and_notdst),
460 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notdst),
461 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src),
462 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_1),
463 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_dst),
464 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_xor_dst),
465 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_dst),
466 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_notdst),
467 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_notxor_dst),
468 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_src_or_notdst),
469 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc),
470 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_or_dst),
471 TRANSP_ROP(cirrus_bitblt_rop_bkwd_transp_notsrc_and_notdst),
472 };
473
474 #define ROP2(name) {\
475 name ## _8,\
476 name ## _16,\
477 name ## _24,\
478 name ## _32,\
479 }
480
481 #define ROP_NOP2(func) {\
482 func,\
483 func,\
484 func,\
485 func,\
486 }
487
488 static const cirrus_bitblt_rop_t cirrus_patternfill[16][4] = {
489 ROP2(cirrus_patternfill_0),
490 ROP2(cirrus_patternfill_src_and_dst),
491 ROP_NOP2(cirrus_bitblt_rop_nop),
492 ROP2(cirrus_patternfill_src_and_notdst),
493 ROP2(cirrus_patternfill_notdst),
494 ROP2(cirrus_patternfill_src),
495 ROP2(cirrus_patternfill_1),
496 ROP2(cirrus_patternfill_notsrc_and_dst),
497 ROP2(cirrus_patternfill_src_xor_dst),
498 ROP2(cirrus_patternfill_src_or_dst),
499 ROP2(cirrus_patternfill_notsrc_or_notdst),
500 ROP2(cirrus_patternfill_src_notxor_dst),
501 ROP2(cirrus_patternfill_src_or_notdst),
502 ROP2(cirrus_patternfill_notsrc),
503 ROP2(cirrus_patternfill_notsrc_or_dst),
504 ROP2(cirrus_patternfill_notsrc_and_notdst),
505 };
506
507 static const cirrus_bitblt_rop_t cirrus_colorexpand_transp[16][4] = {
508 ROP2(cirrus_colorexpand_transp_0),
509 ROP2(cirrus_colorexpand_transp_src_and_dst),
510 ROP_NOP2(cirrus_bitblt_rop_nop),
511 ROP2(cirrus_colorexpand_transp_src_and_notdst),
512 ROP2(cirrus_colorexpand_transp_notdst),
513 ROP2(cirrus_colorexpand_transp_src),
514 ROP2(cirrus_colorexpand_transp_1),
515 ROP2(cirrus_colorexpand_transp_notsrc_and_dst),
516 ROP2(cirrus_colorexpand_transp_src_xor_dst),
517 ROP2(cirrus_colorexpand_transp_src_or_dst),
518 ROP2(cirrus_colorexpand_transp_notsrc_or_notdst),
519 ROP2(cirrus_colorexpand_transp_src_notxor_dst),
520 ROP2(cirrus_colorexpand_transp_src_or_notdst),
521 ROP2(cirrus_colorexpand_transp_notsrc),
522 ROP2(cirrus_colorexpand_transp_notsrc_or_dst),
523 ROP2(cirrus_colorexpand_transp_notsrc_and_notdst),
524 };
525
526 static const cirrus_bitblt_rop_t cirrus_colorexpand[16][4] = {
527 ROP2(cirrus_colorexpand_0),
528 ROP2(cirrus_colorexpand_src_and_dst),
529 ROP_NOP2(cirrus_bitblt_rop_nop),
530 ROP2(cirrus_colorexpand_src_and_notdst),
531 ROP2(cirrus_colorexpand_notdst),
532 ROP2(cirrus_colorexpand_src),
533 ROP2(cirrus_colorexpand_1),
534 ROP2(cirrus_colorexpand_notsrc_and_dst),
535 ROP2(cirrus_colorexpand_src_xor_dst),
536 ROP2(cirrus_colorexpand_src_or_dst),
537 ROP2(cirrus_colorexpand_notsrc_or_notdst),
538 ROP2(cirrus_colorexpand_src_notxor_dst),
539 ROP2(cirrus_colorexpand_src_or_notdst),
540 ROP2(cirrus_colorexpand_notsrc),
541 ROP2(cirrus_colorexpand_notsrc_or_dst),
542 ROP2(cirrus_colorexpand_notsrc_and_notdst),
543 };
544
545 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern_transp[16][4] = {
546 ROP2(cirrus_colorexpand_pattern_transp_0),
547 ROP2(cirrus_colorexpand_pattern_transp_src_and_dst),
548 ROP_NOP2(cirrus_bitblt_rop_nop),
549 ROP2(cirrus_colorexpand_pattern_transp_src_and_notdst),
550 ROP2(cirrus_colorexpand_pattern_transp_notdst),
551 ROP2(cirrus_colorexpand_pattern_transp_src),
552 ROP2(cirrus_colorexpand_pattern_transp_1),
553 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_dst),
554 ROP2(cirrus_colorexpand_pattern_transp_src_xor_dst),
555 ROP2(cirrus_colorexpand_pattern_transp_src_or_dst),
556 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_notdst),
557 ROP2(cirrus_colorexpand_pattern_transp_src_notxor_dst),
558 ROP2(cirrus_colorexpand_pattern_transp_src_or_notdst),
559 ROP2(cirrus_colorexpand_pattern_transp_notsrc),
560 ROP2(cirrus_colorexpand_pattern_transp_notsrc_or_dst),
561 ROP2(cirrus_colorexpand_pattern_transp_notsrc_and_notdst),
562 };
563
564 static const cirrus_bitblt_rop_t cirrus_colorexpand_pattern[16][4] = {
565 ROP2(cirrus_colorexpand_pattern_0),
566 ROP2(cirrus_colorexpand_pattern_src_and_dst),
567 ROP_NOP2(cirrus_bitblt_rop_nop),
568 ROP2(cirrus_colorexpand_pattern_src_and_notdst),
569 ROP2(cirrus_colorexpand_pattern_notdst),
570 ROP2(cirrus_colorexpand_pattern_src),
571 ROP2(cirrus_colorexpand_pattern_1),
572 ROP2(cirrus_colorexpand_pattern_notsrc_and_dst),
573 ROP2(cirrus_colorexpand_pattern_src_xor_dst),
574 ROP2(cirrus_colorexpand_pattern_src_or_dst),
575 ROP2(cirrus_colorexpand_pattern_notsrc_or_notdst),
576 ROP2(cirrus_colorexpand_pattern_src_notxor_dst),
577 ROP2(cirrus_colorexpand_pattern_src_or_notdst),
578 ROP2(cirrus_colorexpand_pattern_notsrc),
579 ROP2(cirrus_colorexpand_pattern_notsrc_or_dst),
580 ROP2(cirrus_colorexpand_pattern_notsrc_and_notdst),
581 };
582
583 static const cirrus_fill_t cirrus_fill[16][4] = {
584 ROP2(cirrus_fill_0),
585 ROP2(cirrus_fill_src_and_dst),
586 ROP_NOP2(cirrus_bitblt_fill_nop),
587 ROP2(cirrus_fill_src_and_notdst),
588 ROP2(cirrus_fill_notdst),
589 ROP2(cirrus_fill_src),
590 ROP2(cirrus_fill_1),
591 ROP2(cirrus_fill_notsrc_and_dst),
592 ROP2(cirrus_fill_src_xor_dst),
593 ROP2(cirrus_fill_src_or_dst),
594 ROP2(cirrus_fill_notsrc_or_notdst),
595 ROP2(cirrus_fill_src_notxor_dst),
596 ROP2(cirrus_fill_src_or_notdst),
597 ROP2(cirrus_fill_notsrc),
598 ROP2(cirrus_fill_notsrc_or_dst),
599 ROP2(cirrus_fill_notsrc_and_notdst),
600 };
601
602 static inline void cirrus_bitblt_fgcol(CirrusVGAState *s)
603 {
604 unsigned int color;
605 switch (s->cirrus_blt_pixelwidth) {
606 case 1:
607 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1;
608 break;
609 case 2:
610 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
611 s->cirrus_blt_fgcol = le16_to_cpu(color);
612 break;
613 case 3:
614 s->cirrus_blt_fgcol = s->cirrus_shadow_gr1 |
615 (s->gr[0x11] << 8) | (s->gr[0x13] << 16);
616 break;
617 default:
618 case 4:
619 color = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
620 (s->gr[0x13] << 16) | (s->gr[0x15] << 24);
621 s->cirrus_blt_fgcol = le32_to_cpu(color);
622 break;
623 }
624 }
625
626 static inline void cirrus_bitblt_bgcol(CirrusVGAState *s)
627 {
628 unsigned int color;
629 switch (s->cirrus_blt_pixelwidth) {
630 case 1:
631 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0;
632 break;
633 case 2:
634 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8);
635 s->cirrus_blt_bgcol = le16_to_cpu(color);
636 break;
637 case 3:
638 s->cirrus_blt_bgcol = s->cirrus_shadow_gr0 |
639 (s->gr[0x10] << 8) | (s->gr[0x12] << 16);
640 break;
641 default:
642 case 4:
643 color = s->cirrus_shadow_gr0 | (s->gr[0x10] << 8) |
644 (s->gr[0x12] << 16) | (s->gr[0x14] << 24);
645 s->cirrus_blt_bgcol = le32_to_cpu(color);
646 break;
647 }
648 }
649
650 static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin,
651 int off_pitch, int bytesperline,
652 int lines)
653 {
654 int y;
655 int off_cur;
656 int off_cur_end;
657
658 for (y = 0; y < lines; y++) {
659 off_cur = off_begin;
660 off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask;
661 off_cur &= TARGET_PAGE_MASK;
662 while (off_cur < off_cur_end) {
663 cpu_physical_memory_set_dirty(s->vram_offset + off_cur);
664 off_cur += TARGET_PAGE_SIZE;
665 }
666 off_begin += off_pitch;
667 }
668 }
669
670 static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
671 const uint8_t * src)
672 {
673 uint8_t *dst;
674
675 dst = s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask);
676
677 if (BLTUNSAFE(s))
678 return 0;
679
680 (*s->cirrus_rop) (s, dst, src,
681 s->cirrus_blt_dstpitch, 0,
682 s->cirrus_blt_width, s->cirrus_blt_height);
683 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
684 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
685 s->cirrus_blt_height);
686 return 1;
687 }
688
689 /* fill */
690
691 static int cirrus_bitblt_solidfill(CirrusVGAState *s, int blt_rop)
692 {
693 cirrus_fill_t rop_func;
694
695 if (BLTUNSAFE(s))
696 return 0;
697 rop_func = cirrus_fill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
698 rop_func(s, s->vram_ptr + (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
699 s->cirrus_blt_dstpitch,
700 s->cirrus_blt_width, s->cirrus_blt_height);
701 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
702 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
703 s->cirrus_blt_height);
704 cirrus_bitblt_reset(s);
705 return 1;
706 }
707
708 /***************************************
709 *
710 * bitblt (video-to-video)
711 *
712 ***************************************/
713
714 static int cirrus_bitblt_videotovideo_patterncopy(CirrusVGAState * s)
715 {
716 return cirrus_bitblt_common_patterncopy(s,
717 s->vram_ptr + ((s->cirrus_blt_srcaddr & ~7) &
718 s->cirrus_addr_mask));
719 }
720
721 static void cirrus_do_copy(CirrusVGAState *s, int dst, int src, int w, int h)
722 {
723 int sx, sy;
724 int dx, dy;
725 int width, height;
726 int depth;
727 int notify = 0;
728
729 depth = s->get_bpp((VGAState *)s) / 8;
730 s->get_resolution((VGAState *)s, &width, &height);
731
732 /* extra x, y */
733 sx = (src % ABS(s->cirrus_blt_srcpitch)) / depth;
734 sy = (src / ABS(s->cirrus_blt_srcpitch));
735 dx = (dst % ABS(s->cirrus_blt_dstpitch)) / depth;
736 dy = (dst / ABS(s->cirrus_blt_dstpitch));
737
738 /* normalize width */
739 w /= depth;
740
741 /* if we're doing a backward copy, we have to adjust
742 our x/y to be the upper left corner (instead of the lower
743 right corner) */
744 if (s->cirrus_blt_dstpitch < 0) {
745 sx -= (s->cirrus_blt_width / depth) - 1;
746 dx -= (s->cirrus_blt_width / depth) - 1;
747 sy -= s->cirrus_blt_height - 1;
748 dy -= s->cirrus_blt_height - 1;
749 }
750
751 /* are we in the visible portion of memory? */
752 if (sx >= 0 && sy >= 0 && dx >= 0 && dy >= 0 &&
753 (sx + w) <= width && (sy + h) <= height &&
754 (dx + w) <= width && (dy + h) <= height) {
755 notify = 1;
756 }
757
758 /* make to sure only copy if it's a plain copy ROP */
759 if (*s->cirrus_rop != cirrus_bitblt_rop_fwd_src &&
760 *s->cirrus_rop != cirrus_bitblt_rop_bkwd_src)
761 notify = 0;
762
763 /* we have to flush all pending changes so that the copy
764 is generated at the appropriate moment in time */
765 if (notify)
766 vga_hw_update();
767
768 (*s->cirrus_rop) (s, s->vram_ptr +
769 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
770 s->vram_ptr +
771 (s->cirrus_blt_srcaddr & s->cirrus_addr_mask),
772 s->cirrus_blt_dstpitch, s->cirrus_blt_srcpitch,
773 s->cirrus_blt_width, s->cirrus_blt_height);
774
775 if (notify)
776 qemu_console_copy(s->ds,
777 sx, sy, dx, dy,
778 s->cirrus_blt_width / depth,
779 s->cirrus_blt_height);
780
781 /* we don't have to notify the display that this portion has
782 changed since qemu_console_copy implies this */
783
784 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
785 s->cirrus_blt_dstpitch, s->cirrus_blt_width,
786 s->cirrus_blt_height);
787 }
788
789 static int cirrus_bitblt_videotovideo_copy(CirrusVGAState * s)
790 {
791 if (BLTUNSAFE(s))
792 return 0;
793
794 cirrus_do_copy(s, s->cirrus_blt_dstaddr - s->start_addr,
795 s->cirrus_blt_srcaddr - s->start_addr,
796 s->cirrus_blt_width, s->cirrus_blt_height);
797
798 return 1;
799 }
800
801 /***************************************
802 *
803 * bitblt (cpu-to-video)
804 *
805 ***************************************/
806
807 static void cirrus_bitblt_cputovideo_next(CirrusVGAState * s)
808 {
809 int copy_count;
810 uint8_t *end_ptr;
811
812 if (s->cirrus_srccounter > 0) {
813 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
814 cirrus_bitblt_common_patterncopy(s, s->cirrus_bltbuf);
815 the_end:
816 s->cirrus_srccounter = 0;
817 cirrus_bitblt_reset(s);
818 } else {
819 /* at least one scan line */
820 do {
821 (*s->cirrus_rop)(s, s->vram_ptr +
822 (s->cirrus_blt_dstaddr & s->cirrus_addr_mask),
823 s->cirrus_bltbuf, 0, 0, s->cirrus_blt_width, 1);
824 cirrus_invalidate_region(s, s->cirrus_blt_dstaddr, 0,
825 s->cirrus_blt_width, 1);
826 s->cirrus_blt_dstaddr += s->cirrus_blt_dstpitch;
827 s->cirrus_srccounter -= s->cirrus_blt_srcpitch;
828 if (s->cirrus_srccounter <= 0)
829 goto the_end;
830 /* more bytes than needed can be transfered because of
831 word alignment, so we keep them for the next line */
832 /* XXX: keep alignment to speed up transfer */
833 end_ptr = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
834 copy_count = s->cirrus_srcptr_end - end_ptr;
835 memmove(s->cirrus_bltbuf, end_ptr, copy_count);
836 s->cirrus_srcptr = s->cirrus_bltbuf + copy_count;
837 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
838 } while (s->cirrus_srcptr >= s->cirrus_srcptr_end);
839 }
840 }
841 }
842
843 /***************************************
844 *
845 * bitblt wrapper
846 *
847 ***************************************/
848
849 static void cirrus_bitblt_reset(CirrusVGAState * s)
850 {
851 int need_update;
852
853 s->gr[0x31] &=
854 ~(CIRRUS_BLT_START | CIRRUS_BLT_BUSY | CIRRUS_BLT_FIFOUSED);
855 need_update = s->cirrus_srcptr != &s->cirrus_bltbuf[0]
856 || s->cirrus_srcptr_end != &s->cirrus_bltbuf[0];
857 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
858 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
859 s->cirrus_srccounter = 0;
860 if (!need_update)
861 return;
862 cirrus_update_memory_access(s);
863 }
864
865 static int cirrus_bitblt_cputovideo(CirrusVGAState * s)
866 {
867 int w;
868
869 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_MEMSYSSRC;
870 s->cirrus_srcptr = &s->cirrus_bltbuf[0];
871 s->cirrus_srcptr_end = &s->cirrus_bltbuf[0];
872
873 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
874 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
875 s->cirrus_blt_srcpitch = 8;
876 } else {
877 /* XXX: check for 24 bpp */
878 s->cirrus_blt_srcpitch = 8 * 8 * s->cirrus_blt_pixelwidth;
879 }
880 s->cirrus_srccounter = s->cirrus_blt_srcpitch;
881 } else {
882 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
883 w = s->cirrus_blt_width / s->cirrus_blt_pixelwidth;
884 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_DWORDGRANULARITY)
885 s->cirrus_blt_srcpitch = ((w + 31) >> 5);
886 else
887 s->cirrus_blt_srcpitch = ((w + 7) >> 3);
888 } else {
889 /* always align input size to 32 bits */
890 s->cirrus_blt_srcpitch = (s->cirrus_blt_width + 3) & ~3;
891 }
892 s->cirrus_srccounter = s->cirrus_blt_srcpitch * s->cirrus_blt_height;
893 }
894 s->cirrus_srcptr = s->cirrus_bltbuf;
895 s->cirrus_srcptr_end = s->cirrus_bltbuf + s->cirrus_blt_srcpitch;
896 cirrus_update_memory_access(s);
897 return 1;
898 }
899
900 static int cirrus_bitblt_videotocpu(CirrusVGAState * s)
901 {
902 /* XXX */
903 #ifdef DEBUG_BITBLT
904 printf("cirrus: bitblt (video to cpu) is not implemented yet\n");
905 #endif
906 return 0;
907 }
908
909 static int cirrus_bitblt_videotovideo(CirrusVGAState * s)
910 {
911 int ret;
912
913 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
914 ret = cirrus_bitblt_videotovideo_patterncopy(s);
915 } else {
916 ret = cirrus_bitblt_videotovideo_copy(s);
917 }
918 if (ret)
919 cirrus_bitblt_reset(s);
920 return ret;
921 }
922
923 static void cirrus_bitblt_start(CirrusVGAState * s)
924 {
925 uint8_t blt_rop;
926
927 s->gr[0x31] |= CIRRUS_BLT_BUSY;
928
929 s->cirrus_blt_width = (s->gr[0x20] | (s->gr[0x21] << 8)) + 1;
930 s->cirrus_blt_height = (s->gr[0x22] | (s->gr[0x23] << 8)) + 1;
931 s->cirrus_blt_dstpitch = (s->gr[0x24] | (s->gr[0x25] << 8));
932 s->cirrus_blt_srcpitch = (s->gr[0x26] | (s->gr[0x27] << 8));
933 s->cirrus_blt_dstaddr =
934 (s->gr[0x28] | (s->gr[0x29] << 8) | (s->gr[0x2a] << 16));
935 s->cirrus_blt_srcaddr =
936 (s->gr[0x2c] | (s->gr[0x2d] << 8) | (s->gr[0x2e] << 16));
937 s->cirrus_blt_mode = s->gr[0x30];
938 s->cirrus_blt_modeext = s->gr[0x33];
939 blt_rop = s->gr[0x32];
940
941 #ifdef DEBUG_BITBLT
942 printf("rop=0x%02x mode=0x%02x modeext=0x%02x w=%d h=%d dpitch=%d spitch=%d daddr=0x%08x saddr=0x%08x writemask=0x%02x\n",
943 blt_rop,
944 s->cirrus_blt_mode,
945 s->cirrus_blt_modeext,
946 s->cirrus_blt_width,
947 s->cirrus_blt_height,
948 s->cirrus_blt_dstpitch,
949 s->cirrus_blt_srcpitch,
950 s->cirrus_blt_dstaddr,
951 s->cirrus_blt_srcaddr,
952 s->gr[0x2f]);
953 #endif
954
955 switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
956 case CIRRUS_BLTMODE_PIXELWIDTH8:
957 s->cirrus_blt_pixelwidth = 1;
958 break;
959 case CIRRUS_BLTMODE_PIXELWIDTH16:
960 s->cirrus_blt_pixelwidth = 2;
961 break;
962 case CIRRUS_BLTMODE_PIXELWIDTH24:
963 s->cirrus_blt_pixelwidth = 3;
964 break;
965 case CIRRUS_BLTMODE_PIXELWIDTH32:
966 s->cirrus_blt_pixelwidth = 4;
967 break;
968 default:
969 #ifdef DEBUG_BITBLT
970 printf("cirrus: bitblt - pixel width is unknown\n");
971 #endif
972 goto bitblt_ignore;
973 }
974 s->cirrus_blt_mode &= ~CIRRUS_BLTMODE_PIXELWIDTHMASK;
975
976 if ((s->
977 cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSSRC |
978 CIRRUS_BLTMODE_MEMSYSDEST))
979 == (CIRRUS_BLTMODE_MEMSYSSRC | CIRRUS_BLTMODE_MEMSYSDEST)) {
980 #ifdef DEBUG_BITBLT
981 printf("cirrus: bitblt - memory-to-memory copy is requested\n");
982 #endif
983 goto bitblt_ignore;
984 }
985
986 if ((s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
987 (s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
988 CIRRUS_BLTMODE_TRANSPARENTCOMP |
989 CIRRUS_BLTMODE_PATTERNCOPY |
990 CIRRUS_BLTMODE_COLOREXPAND)) ==
991 (CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
992 cirrus_bitblt_fgcol(s);
993 cirrus_bitblt_solidfill(s, blt_rop);
994 } else {
995 if ((s->cirrus_blt_mode & (CIRRUS_BLTMODE_COLOREXPAND |
996 CIRRUS_BLTMODE_PATTERNCOPY)) ==
997 CIRRUS_BLTMODE_COLOREXPAND) {
998
999 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1000 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1001 cirrus_bitblt_bgcol(s);
1002 else
1003 cirrus_bitblt_fgcol(s);
1004 s->cirrus_rop = cirrus_colorexpand_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1005 } else {
1006 cirrus_bitblt_fgcol(s);
1007 cirrus_bitblt_bgcol(s);
1008 s->cirrus_rop = cirrus_colorexpand[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1009 }
1010 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_PATTERNCOPY) {
1011 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_COLOREXPAND) {
1012 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1013 if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV)
1014 cirrus_bitblt_bgcol(s);
1015 else
1016 cirrus_bitblt_fgcol(s);
1017 s->cirrus_rop = cirrus_colorexpand_pattern_transp[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1018 } else {
1019 cirrus_bitblt_fgcol(s);
1020 cirrus_bitblt_bgcol(s);
1021 s->cirrus_rop = cirrus_colorexpand_pattern[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1022 }
1023 } else {
1024 s->cirrus_rop = cirrus_patternfill[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1025 }
1026 } else {
1027 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_TRANSPARENTCOMP) {
1028 if (s->cirrus_blt_pixelwidth > 2) {
1029 printf("src transparent without colorexpand must be 8bpp or 16bpp\n");
1030 goto bitblt_ignore;
1031 }
1032 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1033 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1034 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1035 s->cirrus_rop = cirrus_bkwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1036 } else {
1037 s->cirrus_rop = cirrus_fwd_transp_rop[rop_to_index[blt_rop]][s->cirrus_blt_pixelwidth - 1];
1038 }
1039 } else {
1040 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
1041 s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
1042 s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
1043 s->cirrus_rop = cirrus_bkwd_rop[rop_to_index[blt_rop]];
1044 } else {
1045 s->cirrus_rop = cirrus_fwd_rop[rop_to_index[blt_rop]];
1046 }
1047 }
1048 }
1049 // setup bitblt engine.
1050 if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
1051 if (!cirrus_bitblt_cputovideo(s))
1052 goto bitblt_ignore;
1053 } else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
1054 if (!cirrus_bitblt_videotocpu(s))
1055 goto bitblt_ignore;
1056 } else {
1057 if (!cirrus_bitblt_videotovideo(s))
1058 goto bitblt_ignore;
1059 }
1060 }
1061 return;
1062 bitblt_ignore:;
1063 cirrus_bitblt_reset(s);
1064 }
1065
1066 static void cirrus_write_bitblt(CirrusVGAState * s, unsigned reg_value)
1067 {
1068 unsigned old_value;
1069
1070 old_value = s->gr[0x31];
1071 s->gr[0x31] = reg_value;
1072
1073 if (((old_value & CIRRUS_BLT_RESET) != 0) &&
1074 ((reg_value & CIRRUS_BLT_RESET) == 0)) {
1075 cirrus_bitblt_reset(s);
1076 } else if (((old_value & CIRRUS_BLT_START) == 0) &&
1077 ((reg_value & CIRRUS_BLT_START) != 0)) {
1078 cirrus_bitblt_start(s);
1079 }
1080 }
1081
1082
1083 /***************************************
1084 *
1085 * basic parameters
1086 *
1087 ***************************************/
1088
1089 static void cirrus_get_offsets(VGAState *s1,
1090 uint32_t *pline_offset,
1091 uint32_t *pstart_addr,
1092 uint32_t *pline_compare)
1093 {
1094 CirrusVGAState * s = (CirrusVGAState *)s1;
1095 uint32_t start_addr, line_offset, line_compare;
1096
1097 line_offset = s->cr[0x13]
1098 | ((s->cr[0x1b] & 0x10) << 4);
1099 line_offset <<= 3;
1100 *pline_offset = line_offset;
1101
1102 start_addr = (s->cr[0x0c] << 8)
1103 | s->cr[0x0d]
1104 | ((s->cr[0x1b] & 0x01) << 16)
1105 | ((s->cr[0x1b] & 0x0c) << 15)
1106 | ((s->cr[0x1d] & 0x80) << 12);
1107 *pstart_addr = start_addr;
1108
1109 line_compare = s->cr[0x18] |
1110 ((s->cr[0x07] & 0x10) << 4) |
1111 ((s->cr[0x09] & 0x40) << 3);
1112 *pline_compare = line_compare;
1113 }
1114
1115 static uint32_t cirrus_get_bpp16_depth(CirrusVGAState * s)
1116 {
1117 uint32_t ret = 16;
1118
1119 switch (s->cirrus_hidden_dac_data & 0xf) {
1120 case 0:
1121 ret = 15;
1122 break; /* Sierra HiColor */
1123 case 1:
1124 ret = 16;
1125 break; /* XGA HiColor */
1126 default:
1127 #ifdef DEBUG_CIRRUS
1128 printf("cirrus: invalid DAC value %x in 16bpp\n",
1129 (s->cirrus_hidden_dac_data & 0xf));
1130 #endif
1131 ret = 15; /* XXX */
1132 break;
1133 }
1134 return ret;
1135 }
1136
1137 static int cirrus_get_bpp(VGAState *s1)
1138 {
1139 CirrusVGAState * s = (CirrusVGAState *)s1;
1140 uint32_t ret = 8;
1141
1142 if ((s->sr[0x07] & 0x01) != 0) {
1143 /* Cirrus SVGA */
1144 switch (s->sr[0x07] & CIRRUS_SR7_BPP_MASK) {
1145 case CIRRUS_SR7_BPP_8:
1146 ret = 8;
1147 break;
1148 case CIRRUS_SR7_BPP_16_DOUBLEVCLK:
1149 ret = cirrus_get_bpp16_depth(s);
1150 break;
1151 case CIRRUS_SR7_BPP_24:
1152 ret = 24;
1153 break;
1154 case CIRRUS_SR7_BPP_16:
1155 ret = cirrus_get_bpp16_depth(s);
1156 break;
1157 case CIRRUS_SR7_BPP_32:
1158 ret = 32;
1159 break;
1160 default:
1161 #ifdef DEBUG_CIRRUS
1162 printf("cirrus: unknown bpp - sr7=%x\n", s->sr[0x7]);
1163 #endif
1164 ret = 8;
1165 break;
1166 }
1167 } else {
1168 /* VGA */
1169 ret = 0;
1170 }
1171
1172 return ret;
1173 }
1174
1175 static void cirrus_get_resolution(VGAState *s, int *pwidth, int *pheight)
1176 {
1177 int width, height;
1178
1179 width = (s->cr[0x01] + 1) * 8;
1180 height = s->cr[0x12] |
1181 ((s->cr[0x07] & 0x02) << 7) |
1182 ((s->cr[0x07] & 0x40) << 3);
1183 height = (height + 1);
1184 /* interlace support */
1185 if (s->cr[0x1a] & 0x01)
1186 height = height * 2;
1187 *pwidth = width;
1188 *pheight = height;
1189 }
1190
1191 /***************************************
1192 *
1193 * bank memory
1194 *
1195 ***************************************/
1196
1197 static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index)
1198 {
1199 unsigned offset;
1200 unsigned limit;
1201
1202 if ((s->gr[0x0b] & 0x01) != 0) /* dual bank */
1203 offset = s->gr[0x09 + bank_index];
1204 else /* single bank */
1205 offset = s->gr[0x09];
1206
1207 if ((s->gr[0x0b] & 0x20) != 0)
1208 offset <<= 14;
1209 else
1210 offset <<= 12;
1211
1212 if (s->real_vram_size <= offset)
1213 limit = 0;
1214 else
1215 limit = s->real_vram_size - offset;
1216
1217 if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) {
1218 if (limit > 0x8000) {
1219 offset += 0x8000;
1220 limit -= 0x8000;
1221 } else {
1222 limit = 0;
1223 }
1224 }
1225
1226 if (limit > 0) {
1227 /* Thinking about changing bank base? First, drop the dirty bitmap information
1228 * on the current location, otherwise we lose this pointer forever */
1229 if (s->lfb_vram_mapped) {
1230 target_phys_addr_t base_addr = isa_mem_base + 0xa0000 + bank_index * 0x8000;
1231 cpu_physical_sync_dirty_bitmap(base_addr, base_addr + 0x8000);
1232 }
1233 s->cirrus_bank_base[bank_index] = offset;
1234 s->cirrus_bank_limit[bank_index] = limit;
1235 } else {
1236 s->cirrus_bank_base[bank_index] = 0;
1237 s->cirrus_bank_limit[bank_index] = 0;
1238 }
1239 }
1240
1241 /***************************************
1242 *
1243 * I/O access between 0x3c4-0x3c5
1244 *
1245 ***************************************/
1246
1247 static int
1248 cirrus_hook_read_sr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1249 {
1250 switch (reg_index) {
1251 case 0x00: // Standard VGA
1252 case 0x01: // Standard VGA
1253 case 0x02: // Standard VGA
1254 case 0x03: // Standard VGA
1255 case 0x04: // Standard VGA
1256 return CIRRUS_HOOK_NOT_HANDLED;
1257 case 0x06: // Unlock Cirrus extensions
1258 *reg_value = s->sr[reg_index];
1259 break;
1260 case 0x10:
1261 case 0x30:
1262 case 0x50:
1263 case 0x70: // Graphics Cursor X
1264 case 0x90:
1265 case 0xb0:
1266 case 0xd0:
1267 case 0xf0: // Graphics Cursor X
1268 *reg_value = s->sr[0x10];
1269 break;
1270 case 0x11:
1271 case 0x31:
1272 case 0x51:
1273 case 0x71: // Graphics Cursor Y
1274 case 0x91:
1275 case 0xb1:
1276 case 0xd1:
1277 case 0xf1: // Graphics Cursor Y
1278 *reg_value = s->sr[0x11];
1279 break;
1280 case 0x05: // ???
1281 case 0x07: // Extended Sequencer Mode
1282 case 0x08: // EEPROM Control
1283 case 0x09: // Scratch Register 0
1284 case 0x0a: // Scratch Register 1
1285 case 0x0b: // VCLK 0
1286 case 0x0c: // VCLK 1
1287 case 0x0d: // VCLK 2
1288 case 0x0e: // VCLK 3
1289 case 0x0f: // DRAM Control
1290 case 0x12: // Graphics Cursor Attribute
1291 case 0x13: // Graphics Cursor Pattern Address
1292 case 0x14: // Scratch Register 2
1293 case 0x15: // Scratch Register 3
1294 case 0x16: // Performance Tuning Register
1295 case 0x17: // Configuration Readback and Extended Control
1296 case 0x18: // Signature Generator Control
1297 case 0x19: // Signal Generator Result
1298 case 0x1a: // Signal Generator Result
1299 case 0x1b: // VCLK 0 Denominator & Post
1300 case 0x1c: // VCLK 1 Denominator & Post
1301 case 0x1d: // VCLK 2 Denominator & Post
1302 case 0x1e: // VCLK 3 Denominator & Post
1303 case 0x1f: // BIOS Write Enable and MCLK select
1304 #ifdef DEBUG_CIRRUS
1305 printf("cirrus: handled inport sr_index %02x\n", reg_index);
1306 #endif
1307 *reg_value = s->sr[reg_index];
1308 break;
1309 default:
1310 #ifdef DEBUG_CIRRUS
1311 printf("cirrus: inport sr_index %02x\n", reg_index);
1312 #endif
1313 *reg_value = 0xff;
1314 break;
1315 }
1316
1317 return CIRRUS_HOOK_HANDLED;
1318 }
1319
1320 static int
1321 cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1322 {
1323 switch (reg_index) {
1324 case 0x00: // Standard VGA
1325 case 0x01: // Standard VGA
1326 case 0x02: // Standard VGA
1327 case 0x03: // Standard VGA
1328 case 0x04: // Standard VGA
1329 return CIRRUS_HOOK_NOT_HANDLED;
1330 case 0x06: // Unlock Cirrus extensions
1331 reg_value &= 0x17;
1332 if (reg_value == 0x12) {
1333 s->sr[reg_index] = 0x12;
1334 } else {
1335 s->sr[reg_index] = 0x0f;
1336 }
1337 break;
1338 case 0x10:
1339 case 0x30:
1340 case 0x50:
1341 case 0x70: // Graphics Cursor X
1342 case 0x90:
1343 case 0xb0:
1344 case 0xd0:
1345 case 0xf0: // Graphics Cursor X
1346 s->sr[0x10] = reg_value;
1347 s->hw_cursor_x = (reg_value << 3) | (reg_index >> 5);
1348 break;
1349 case 0x11:
1350 case 0x31:
1351 case 0x51:
1352 case 0x71: // Graphics Cursor Y
1353 case 0x91:
1354 case 0xb1:
1355 case 0xd1:
1356 case 0xf1: // Graphics Cursor Y
1357 s->sr[0x11] = reg_value;
1358 s->hw_cursor_y = (reg_value << 3) | (reg_index >> 5);
1359 break;
1360 case 0x07: // Extended Sequencer Mode
1361 cirrus_update_memory_access(s);
1362 case 0x08: // EEPROM Control
1363 case 0x09: // Scratch Register 0
1364 case 0x0a: // Scratch Register 1
1365 case 0x0b: // VCLK 0
1366 case 0x0c: // VCLK 1
1367 case 0x0d: // VCLK 2
1368 case 0x0e: // VCLK 3
1369 case 0x0f: // DRAM Control
1370 case 0x12: // Graphics Cursor Attribute
1371 case 0x13: // Graphics Cursor Pattern Address
1372 case 0x14: // Scratch Register 2
1373 case 0x15: // Scratch Register 3
1374 case 0x16: // Performance Tuning Register
1375 case 0x18: // Signature Generator Control
1376 case 0x19: // Signature Generator Result
1377 case 0x1a: // Signature Generator Result
1378 case 0x1b: // VCLK 0 Denominator & Post
1379 case 0x1c: // VCLK 1 Denominator & Post
1380 case 0x1d: // VCLK 2 Denominator & Post
1381 case 0x1e: // VCLK 3 Denominator & Post
1382 case 0x1f: // BIOS Write Enable and MCLK select
1383 s->sr[reg_index] = reg_value;
1384 #ifdef DEBUG_CIRRUS
1385 printf("cirrus: handled outport sr_index %02x, sr_value %02x\n",
1386 reg_index, reg_value);
1387 #endif
1388 break;
1389 case 0x17: // Configuration Readback and Extended Control
1390 s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7);
1391 cirrus_update_memory_access(s);
1392 break;
1393 default:
1394 #ifdef DEBUG_CIRRUS
1395 printf("cirrus: outport sr_index %02x, sr_value %02x\n", reg_index,
1396 reg_value);
1397 #endif
1398 break;
1399 }
1400
1401 return CIRRUS_HOOK_HANDLED;
1402 }
1403
1404 /***************************************
1405 *
1406 * I/O access at 0x3c6
1407 *
1408 ***************************************/
1409
1410 static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
1411 {
1412 *reg_value = 0xff;
1413 if (++s->cirrus_hidden_dac_lockindex == 5) {
1414 *reg_value = s->cirrus_hidden_dac_data;
1415 s->cirrus_hidden_dac_lockindex = 0;
1416 }
1417 }
1418
1419 static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
1420 {
1421 if (s->cirrus_hidden_dac_lockindex == 4) {
1422 s->cirrus_hidden_dac_data = reg_value;
1423 #if defined(DEBUG_CIRRUS)
1424 printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
1425 #endif
1426 }
1427 s->cirrus_hidden_dac_lockindex = 0;
1428 }
1429
1430 /***************************************
1431 *
1432 * I/O access at 0x3c9
1433 *
1434 ***************************************/
1435
1436 static int cirrus_hook_read_palette(CirrusVGAState * s, int *reg_value)
1437 {
1438 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1439 return CIRRUS_HOOK_NOT_HANDLED;
1440 *reg_value =
1441 s->cirrus_hidden_palette[(s->dac_read_index & 0x0f) * 3 +
1442 s->dac_sub_index];
1443 if (++s->dac_sub_index == 3) {
1444 s->dac_sub_index = 0;
1445 s->dac_read_index++;
1446 }
1447 return CIRRUS_HOOK_HANDLED;
1448 }
1449
1450 static int cirrus_hook_write_palette(CirrusVGAState * s, int reg_value)
1451 {
1452 if (!(s->sr[0x12] & CIRRUS_CURSOR_HIDDENPEL))
1453 return CIRRUS_HOOK_NOT_HANDLED;
1454 s->dac_cache[s->dac_sub_index] = reg_value;
1455 if (++s->dac_sub_index == 3) {
1456 memcpy(&s->cirrus_hidden_palette[(s->dac_write_index & 0x0f) * 3],
1457 s->dac_cache, 3);
1458 /* XXX update cursor */
1459 s->dac_sub_index = 0;
1460 s->dac_write_index++;
1461 }
1462 return CIRRUS_HOOK_HANDLED;
1463 }
1464
1465 /***************************************
1466 *
1467 * I/O access between 0x3ce-0x3cf
1468 *
1469 ***************************************/
1470
1471 static int
1472 cirrus_hook_read_gr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1473 {
1474 switch (reg_index) {
1475 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1476 *reg_value = s->cirrus_shadow_gr0;
1477 return CIRRUS_HOOK_HANDLED;
1478 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1479 *reg_value = s->cirrus_shadow_gr1;
1480 return CIRRUS_HOOK_HANDLED;
1481 case 0x02: // Standard VGA
1482 case 0x03: // Standard VGA
1483 case 0x04: // Standard VGA
1484 case 0x06: // Standard VGA
1485 case 0x07: // Standard VGA
1486 case 0x08: // Standard VGA
1487 return CIRRUS_HOOK_NOT_HANDLED;
1488 case 0x05: // Standard VGA, Cirrus extended mode
1489 default:
1490 break;
1491 }
1492
1493 if (reg_index < 0x3a) {
1494 *reg_value = s->gr[reg_index];
1495 } else {
1496 #ifdef DEBUG_CIRRUS
1497 printf("cirrus: inport gr_index %02x\n", reg_index);
1498 #endif
1499 *reg_value = 0xff;
1500 }
1501
1502 return CIRRUS_HOOK_HANDLED;
1503 }
1504
1505 static int
1506 cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1507 {
1508 #if defined(DEBUG_BITBLT) && 0
1509 printf("gr%02x: %02x\n", reg_index, reg_value);
1510 #endif
1511 switch (reg_index) {
1512 case 0x00: // Standard VGA, BGCOLOR 0x000000ff
1513 s->cirrus_shadow_gr0 = reg_value;
1514 return CIRRUS_HOOK_NOT_HANDLED;
1515 case 0x01: // Standard VGA, FGCOLOR 0x000000ff
1516 s->cirrus_shadow_gr1 = reg_value;
1517 return CIRRUS_HOOK_NOT_HANDLED;
1518 case 0x02: // Standard VGA
1519 case 0x03: // Standard VGA
1520 case 0x04: // Standard VGA
1521 case 0x06: // Standard VGA
1522 case 0x07: // Standard VGA
1523 case 0x08: // Standard VGA
1524 return CIRRUS_HOOK_NOT_HANDLED;
1525 case 0x05: // Standard VGA, Cirrus extended mode
1526 s->gr[reg_index] = reg_value & 0x7f;
1527 cirrus_update_memory_access(s);
1528 break;
1529 case 0x09: // bank offset #0
1530 case 0x0A: // bank offset #1
1531 s->gr[reg_index] = reg_value;
1532 cirrus_update_bank_ptr(s, 0);
1533 cirrus_update_bank_ptr(s, 1);
1534 cirrus_update_memory_access(s);
1535 break;
1536 case 0x0B:
1537 s->gr[reg_index] = reg_value;
1538 cirrus_update_bank_ptr(s, 0);
1539 cirrus_update_bank_ptr(s, 1);
1540 cirrus_update_memory_access(s);
1541 break;
1542 case 0x10: // BGCOLOR 0x0000ff00
1543 case 0x11: // FGCOLOR 0x0000ff00
1544 case 0x12: // BGCOLOR 0x00ff0000
1545 case 0x13: // FGCOLOR 0x00ff0000
1546 case 0x14: // BGCOLOR 0xff000000
1547 case 0x15: // FGCOLOR 0xff000000
1548 case 0x20: // BLT WIDTH 0x0000ff
1549 case 0x22: // BLT HEIGHT 0x0000ff
1550 case 0x24: // BLT DEST PITCH 0x0000ff
1551 case 0x26: // BLT SRC PITCH 0x0000ff
1552 case 0x28: // BLT DEST ADDR 0x0000ff
1553 case 0x29: // BLT DEST ADDR 0x00ff00
1554 case 0x2c: // BLT SRC ADDR 0x0000ff
1555 case 0x2d: // BLT SRC ADDR 0x00ff00
1556 case 0x2f: // BLT WRITEMASK
1557 case 0x30: // BLT MODE
1558 case 0x32: // RASTER OP
1559 case 0x33: // BLT MODEEXT
1560 case 0x34: // BLT TRANSPARENT COLOR 0x00ff
1561 case 0x35: // BLT TRANSPARENT COLOR 0xff00
1562 case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
1563 case 0x39: // BLT TRANSPARENT COLOR MASK 0xff00
1564 s->gr[reg_index] = reg_value;
1565 break;
1566 case 0x21: // BLT WIDTH 0x001f00
1567 case 0x23: // BLT HEIGHT 0x001f00
1568 case 0x25: // BLT DEST PITCH 0x001f00
1569 case 0x27: // BLT SRC PITCH 0x001f00
1570 s->gr[reg_index] = reg_value & 0x1f;
1571 break;
1572 case 0x2a: // BLT DEST ADDR 0x3f0000
1573 s->gr[reg_index] = reg_value & 0x3f;
1574 /* if auto start mode, starts bit blt now */
1575 if (s->gr[0x31] & CIRRUS_BLT_AUTOSTART) {
1576 cirrus_bitblt_start(s);
1577 }
1578 break;
1579 case 0x2e: // BLT SRC ADDR 0x3f0000
1580 s->gr[reg_index] = reg_value & 0x3f;
1581 break;
1582 case 0x31: // BLT STATUS/START
1583 cirrus_write_bitblt(s, reg_value);
1584 break;
1585 default:
1586 #ifdef DEBUG_CIRRUS
1587 printf("cirrus: outport gr_index %02x, gr_value %02x\n", reg_index,
1588 reg_value);
1589 #endif
1590 break;
1591 }
1592
1593 return CIRRUS_HOOK_HANDLED;
1594 }
1595
1596 /***************************************
1597 *
1598 * I/O access between 0x3d4-0x3d5
1599 *
1600 ***************************************/
1601
1602 static int
1603 cirrus_hook_read_cr(CirrusVGAState * s, unsigned reg_index, int *reg_value)
1604 {
1605 switch (reg_index) {
1606 case 0x00: // Standard VGA
1607 case 0x01: // Standard VGA
1608 case 0x02: // Standard VGA
1609 case 0x03: // Standard VGA
1610 case 0x04: // Standard VGA
1611 case 0x05: // Standard VGA
1612 case 0x06: // Standard VGA
1613 case 0x07: // Standard VGA
1614 case 0x08: // Standard VGA
1615 case 0x09: // Standard VGA
1616 case 0x0a: // Standard VGA
1617 case 0x0b: // Standard VGA
1618 case 0x0c: // Standard VGA
1619 case 0x0d: // Standard VGA
1620 case 0x0e: // Standard VGA
1621 case 0x0f: // Standard VGA
1622 case 0x10: // Standard VGA
1623 case 0x11: // Standard VGA
1624 case 0x12: // Standard VGA
1625 case 0x13: // Standard VGA
1626 case 0x14: // Standard VGA
1627 case 0x15: // Standard VGA
1628 case 0x16: // Standard VGA
1629 case 0x17: // Standard VGA
1630 case 0x18: // Standard VGA
1631 return CIRRUS_HOOK_NOT_HANDLED;
1632 case 0x24: // Attribute Controller Toggle Readback (R)
1633 *reg_value = (s->ar_flip_flop << 7);
1634 break;
1635 case 0x19: // Interlace End
1636 case 0x1a: // Miscellaneous Control
1637 case 0x1b: // Extended Display Control
1638 case 0x1c: // Sync Adjust and Genlock
1639 case 0x1d: // Overlay Extended Control
1640 case 0x22: // Graphics Data Latches Readback (R)
1641 case 0x25: // Part Status
1642 case 0x27: // Part ID (R)
1643 *reg_value = s->cr[reg_index];
1644 break;
1645 case 0x26: // Attribute Controller Index Readback (R)
1646 *reg_value = s->ar_index & 0x3f;
1647 break;
1648 default:
1649 #ifdef DEBUG_CIRRUS
1650 printf("cirrus: inport cr_index %02x\n", reg_index);
1651 *reg_value = 0xff;
1652 #endif
1653 break;
1654 }
1655
1656 return CIRRUS_HOOK_HANDLED;
1657 }
1658
1659 static int
1660 cirrus_hook_write_cr(CirrusVGAState * s, unsigned reg_index, int reg_value)
1661 {
1662 switch (reg_index) {
1663 case 0x00: // Standard VGA
1664 case 0x01: // Standard VGA
1665 case 0x02: // Standard VGA
1666 case 0x03: // Standard VGA
1667 case 0x04: // Standard VGA
1668 case 0x05: // Standard VGA
1669 case 0x06: // Standard VGA
1670 case 0x07: // Standard VGA
1671 case 0x08: // Standard VGA
1672 case 0x09: // Standard VGA
1673 case 0x0a: // Standard VGA
1674 case 0x0b: // Standard VGA
1675 case 0x0c: // Standard VGA
1676 case 0x0d: // Standard VGA
1677 case 0x0e: // Standard VGA
1678 case 0x0f: // Standard VGA
1679 case 0x10: // Standard VGA
1680 case 0x11: // Standard VGA
1681 case 0x12: // Standard VGA
1682 case 0x13: // Standard VGA
1683 case 0x14: // Standard VGA
1684 case 0x15: // Standard VGA
1685 case 0x16: // Standard VGA
1686 case 0x17: // Standard VGA
1687 case 0x18: // Standard VGA
1688 return CIRRUS_HOOK_NOT_HANDLED;
1689 case 0x19: // Interlace End
1690 case 0x1a: // Miscellaneous Control
1691 case 0x1b: // Extended Display Control
1692 case 0x1c: // Sync Adjust and Genlock
1693 case 0x1d: // Overlay Extended Control
1694 s->cr[reg_index] = reg_value;
1695 #ifdef DEBUG_CIRRUS
1696 printf("cirrus: handled outport cr_index %02x, cr_value %02x\n",
1697 reg_index, reg_value);
1698 #endif
1699 break;
1700 case 0x22: // Graphics Data Latches Readback (R)
1701 case 0x24: // Attribute Controller Toggle Readback (R)
1702 case 0x26: // Attribute Controller Index Readback (R)
1703 case 0x27: // Part ID (R)
1704 break;
1705 case 0x25: // Part Status
1706 default:
1707 #ifdef DEBUG_CIRRUS
1708 printf("cirrus: outport cr_index %02x, cr_value %02x\n", reg_index,
1709 reg_value);
1710 #endif
1711 break;
1712 }
1713
1714 return CIRRUS_HOOK_HANDLED;
1715 }
1716
1717 /***************************************
1718 *
1719 * memory-mapped I/O (bitblt)
1720 *
1721 ***************************************/
1722
1723 static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
1724 {
1725 int value = 0xff;
1726
1727 switch (address) {
1728 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1729 cirrus_hook_read_gr(s, 0x00, &value);
1730 break;
1731 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1732 cirrus_hook_read_gr(s, 0x10, &value);
1733 break;
1734 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1735 cirrus_hook_read_gr(s, 0x12, &value);
1736 break;
1737 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1738 cirrus_hook_read_gr(s, 0x14, &value);
1739 break;
1740 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1741 cirrus_hook_read_gr(s, 0x01, &value);
1742 break;
1743 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1744 cirrus_hook_read_gr(s, 0x11, &value);
1745 break;
1746 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1747 cirrus_hook_read_gr(s, 0x13, &value);
1748 break;
1749 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1750 cirrus_hook_read_gr(s, 0x15, &value);
1751 break;
1752 case (CIRRUS_MMIO_BLTWIDTH + 0):
1753 cirrus_hook_read_gr(s, 0x20, &value);
1754 break;
1755 case (CIRRUS_MMIO_BLTWIDTH + 1):
1756 cirrus_hook_read_gr(s, 0x21, &value);
1757 break;
1758 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1759 cirrus_hook_read_gr(s, 0x22, &value);
1760 break;
1761 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1762 cirrus_hook_read_gr(s, 0x23, &value);
1763 break;
1764 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1765 cirrus_hook_read_gr(s, 0x24, &value);
1766 break;
1767 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1768 cirrus_hook_read_gr(s, 0x25, &value);
1769 break;
1770 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1771 cirrus_hook_read_gr(s, 0x26, &value);
1772 break;
1773 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1774 cirrus_hook_read_gr(s, 0x27, &value);
1775 break;
1776 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1777 cirrus_hook_read_gr(s, 0x28, &value);
1778 break;
1779 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1780 cirrus_hook_read_gr(s, 0x29, &value);
1781 break;
1782 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1783 cirrus_hook_read_gr(s, 0x2a, &value);
1784 break;
1785 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1786 cirrus_hook_read_gr(s, 0x2c, &value);
1787 break;
1788 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1789 cirrus_hook_read_gr(s, 0x2d, &value);
1790 break;
1791 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1792 cirrus_hook_read_gr(s, 0x2e, &value);
1793 break;
1794 case CIRRUS_MMIO_BLTWRITEMASK:
1795 cirrus_hook_read_gr(s, 0x2f, &value);
1796 break;
1797 case CIRRUS_MMIO_BLTMODE:
1798 cirrus_hook_read_gr(s, 0x30, &value);
1799 break;
1800 case CIRRUS_MMIO_BLTROP:
1801 cirrus_hook_read_gr(s, 0x32, &value);
1802 break;
1803 case CIRRUS_MMIO_BLTMODEEXT:
1804 cirrus_hook_read_gr(s, 0x33, &value);
1805 break;
1806 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1807 cirrus_hook_read_gr(s, 0x34, &value);
1808 break;
1809 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1810 cirrus_hook_read_gr(s, 0x35, &value);
1811 break;
1812 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1813 cirrus_hook_read_gr(s, 0x38, &value);
1814 break;
1815 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1816 cirrus_hook_read_gr(s, 0x39, &value);
1817 break;
1818 case CIRRUS_MMIO_BLTSTATUS:
1819 cirrus_hook_read_gr(s, 0x31, &value);
1820 break;
1821 default:
1822 #ifdef DEBUG_CIRRUS
1823 printf("cirrus: mmio read - address 0x%04x\n", address);
1824 #endif
1825 break;
1826 }
1827
1828 return (uint8_t) value;
1829 }
1830
1831 static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
1832 uint8_t value)
1833 {
1834 switch (address) {
1835 case (CIRRUS_MMIO_BLTBGCOLOR + 0):
1836 cirrus_hook_write_gr(s, 0x00, value);
1837 break;
1838 case (CIRRUS_MMIO_BLTBGCOLOR + 1):
1839 cirrus_hook_write_gr(s, 0x10, value);
1840 break;
1841 case (CIRRUS_MMIO_BLTBGCOLOR + 2):
1842 cirrus_hook_write_gr(s, 0x12, value);
1843 break;
1844 case (CIRRUS_MMIO_BLTBGCOLOR + 3):
1845 cirrus_hook_write_gr(s, 0x14, value);
1846 break;
1847 case (CIRRUS_MMIO_BLTFGCOLOR + 0):
1848 cirrus_hook_write_gr(s, 0x01, value);
1849 break;
1850 case (CIRRUS_MMIO_BLTFGCOLOR + 1):
1851 cirrus_hook_write_gr(s, 0x11, value);
1852 break;
1853 case (CIRRUS_MMIO_BLTFGCOLOR + 2):
1854 cirrus_hook_write_gr(s, 0x13, value);
1855 break;
1856 case (CIRRUS_MMIO_BLTFGCOLOR + 3):
1857 cirrus_hook_write_gr(s, 0x15, value);
1858 break;
1859 case (CIRRUS_MMIO_BLTWIDTH + 0):
1860 cirrus_hook_write_gr(s, 0x20, value);
1861 break;
1862 case (CIRRUS_MMIO_BLTWIDTH + 1):
1863 cirrus_hook_write_gr(s, 0x21, value);
1864 break;
1865 case (CIRRUS_MMIO_BLTHEIGHT + 0):
1866 cirrus_hook_write_gr(s, 0x22, value);
1867 break;
1868 case (CIRRUS_MMIO_BLTHEIGHT + 1):
1869 cirrus_hook_write_gr(s, 0x23, value);
1870 break;
1871 case (CIRRUS_MMIO_BLTDESTPITCH + 0):
1872 cirrus_hook_write_gr(s, 0x24, value);
1873 break;
1874 case (CIRRUS_MMIO_BLTDESTPITCH + 1):
1875 cirrus_hook_write_gr(s, 0x25, value);
1876 break;
1877 case (CIRRUS_MMIO_BLTSRCPITCH + 0):
1878 cirrus_hook_write_gr(s, 0x26, value);
1879 break;
1880 case (CIRRUS_MMIO_BLTSRCPITCH + 1):
1881 cirrus_hook_write_gr(s, 0x27, value);
1882 break;
1883 case (CIRRUS_MMIO_BLTDESTADDR + 0):
1884 cirrus_hook_write_gr(s, 0x28, value);
1885 break;
1886 case (CIRRUS_MMIO_BLTDESTADDR + 1):
1887 cirrus_hook_write_gr(s, 0x29, value);
1888 break;
1889 case (CIRRUS_MMIO_BLTDESTADDR + 2):
1890 cirrus_hook_write_gr(s, 0x2a, value);
1891 break;
1892 case (CIRRUS_MMIO_BLTDESTADDR + 3):
1893 /* ignored */
1894 break;
1895 case (CIRRUS_MMIO_BLTSRCADDR + 0):
1896 cirrus_hook_write_gr(s, 0x2c, value);
1897 break;
1898 case (CIRRUS_MMIO_BLTSRCADDR + 1):
1899 cirrus_hook_write_gr(s, 0x2d, value);
1900 break;
1901 case (CIRRUS_MMIO_BLTSRCADDR + 2):
1902 cirrus_hook_write_gr(s, 0x2e, value);
1903 break;
1904 case CIRRUS_MMIO_BLTWRITEMASK:
1905 cirrus_hook_write_gr(s, 0x2f, value);
1906 break;
1907 case CIRRUS_MMIO_BLTMODE:
1908 cirrus_hook_write_gr(s, 0x30, value);
1909 break;
1910 case CIRRUS_MMIO_BLTROP:
1911 cirrus_hook_write_gr(s, 0x32, value);
1912 break;
1913 case CIRRUS_MMIO_BLTMODEEXT:
1914 cirrus_hook_write_gr(s, 0x33, value);
1915 break;
1916 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
1917 cirrus_hook_write_gr(s, 0x34, value);
1918 break;
1919 case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 1):
1920 cirrus_hook_write_gr(s, 0x35, value);
1921 break;
1922 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 0):
1923 cirrus_hook_write_gr(s, 0x38, value);
1924 break;
1925 case (CIRRUS_MMIO_BLTTRANSPARENTCOLORMASK + 1):
1926 cirrus_hook_write_gr(s, 0x39, value);
1927 break;
1928 case CIRRUS_MMIO_BLTSTATUS:
1929 cirrus_hook_write_gr(s, 0x31, value);
1930 break;
1931 default:
1932 #ifdef DEBUG_CIRRUS
1933 printf("cirrus: mmio write - addr 0x%04x val 0x%02x (ignored)\n",
1934 address, value);
1935 #endif
1936 break;
1937 }
1938 }
1939
1940 /***************************************
1941 *
1942 * write mode 4/5
1943 *
1944 * assume TARGET_PAGE_SIZE >= 16
1945 *
1946 ***************************************/
1947
1948 static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
1949 unsigned mode,
1950 unsigned offset,
1951 uint32_t mem_value)
1952 {
1953 int x;
1954 unsigned val = mem_value;
1955 uint8_t *dst;
1956
1957 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1958 for (x = 0; x < 8; x++) {
1959 if (val & 0x80) {
1960 *dst = s->cirrus_shadow_gr1;
1961 } else if (mode == 5) {
1962 *dst = s->cirrus_shadow_gr0;
1963 }
1964 val <<= 1;
1965 dst++;
1966 }
1967 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1968 cpu_physical_memory_set_dirty(s->vram_offset + offset + 7);
1969 }
1970
1971 static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
1972 unsigned mode,
1973 unsigned offset,
1974 uint32_t mem_value)
1975 {
1976 int x;
1977 unsigned val = mem_value;
1978 uint8_t *dst;
1979
1980 dst = s->vram_ptr + (offset &= s->cirrus_addr_mask);
1981 for (x = 0; x < 8; x++) {
1982 if (val & 0x80) {
1983 *dst = s->cirrus_shadow_gr1;
1984 *(dst + 1) = s->gr[0x11];
1985 } else if (mode == 5) {
1986 *dst = s->cirrus_shadow_gr0;
1987 *(dst + 1) = s->gr[0x10];
1988 }
1989 val <<= 1;
1990 dst += 2;
1991 }
1992 cpu_physical_memory_set_dirty(s->vram_offset + offset);
1993 cpu_physical_memory_set_dirty(s->vram_offset + offset + 15);
1994 }
1995
1996 /***************************************
1997 *
1998 * memory access between 0xa0000-0xbffff
1999 *
2000 ***************************************/
2001
2002 static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)
2003 {
2004 CirrusVGAState *s = opaque;
2005 unsigned bank_index;
2006 unsigned bank_offset;
2007 uint32_t val;
2008
2009 if ((s->sr[0x07] & 0x01) == 0) {
2010 return vga_mem_readb(s, addr);
2011 }
2012
2013 addr &= 0x1ffff;
2014
2015 if (addr < 0x10000) {
2016 /* XXX handle bitblt */
2017 /* video memory */
2018 bank_index = addr >> 15;
2019 bank_offset = addr & 0x7fff;
2020 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2021 bank_offset += s->cirrus_bank_base[bank_index];
2022 if ((s->gr[0x0B] & 0x14) == 0x14) {
2023 bank_offset <<= 4;
2024 } else if (s->gr[0x0B] & 0x02) {
2025 bank_offset <<= 3;
2026 }
2027 bank_offset &= s->cirrus_addr_mask;
2028 val = *(s->vram_ptr + bank_offset);
2029 } else
2030 val = 0xff;
2031 } else if (addr >= 0x18000 && addr < 0x18100) {
2032 /* memory-mapped I/O */
2033 val = 0xff;
2034 if ((s->sr[0x17] & 0x44) == 0x04) {
2035 val = cirrus_mmio_blt_read(s, addr & 0xff);
2036 }
2037 } else {
2038 val = 0xff;
2039 #ifdef DEBUG_CIRRUS
2040 printf("cirrus: mem_readb %06x\n", addr);
2041 #endif
2042 }
2043 return val;
2044 }
2045
2046 static uint32_t cirrus_vga_mem_readw(void *opaque, target_phys_addr_t addr)
2047 {
2048 uint32_t v;
2049 #ifdef TARGET_WORDS_BIGENDIAN
2050 v = cirrus_vga_mem_readb(opaque, addr) << 8;
2051 v |= cirrus_vga_mem_readb(opaque, addr + 1);
2052 #else
2053 v = cirrus_vga_mem_readb(opaque, addr);
2054 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2055 #endif
2056 return v;
2057 }
2058
2059 static uint32_t cirrus_vga_mem_readl(void *opaque, target_phys_addr_t addr)
2060 {
2061 uint32_t v;
2062 #ifdef TARGET_WORDS_BIGENDIAN
2063 v = cirrus_vga_mem_readb(opaque, addr) << 24;
2064 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 16;
2065 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 8;
2066 v |= cirrus_vga_mem_readb(opaque, addr + 3);
2067 #else
2068 v = cirrus_vga_mem_readb(opaque, addr);
2069 v |= cirrus_vga_mem_readb(opaque, addr + 1) << 8;
2070 v |= cirrus_vga_mem_readb(opaque, addr + 2) << 16;
2071 v |= cirrus_vga_mem_readb(opaque, addr + 3) << 24;
2072 #endif
2073 return v;
2074 }
2075
2076 static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,
2077 uint32_t mem_value)
2078 {
2079 CirrusVGAState *s = opaque;
2080 unsigned bank_index;
2081 unsigned bank_offset;
2082 unsigned mode;
2083
2084 if ((s->sr[0x07] & 0x01) == 0) {
2085 vga_mem_writeb(s, addr, mem_value);
2086 return;
2087 }
2088
2089 addr &= 0x1ffff;
2090
2091 if (addr < 0x10000) {
2092 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2093 /* bitblt */
2094 *s->cirrus_srcptr++ = (uint8_t) mem_value;
2095 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2096 cirrus_bitblt_cputovideo_next(s);
2097 }
2098 } else {
2099 /* video memory */
2100 bank_index = addr >> 15;
2101 bank_offset = addr & 0x7fff;
2102 if (bank_offset < s->cirrus_bank_limit[bank_index]) {
2103 bank_offset += s->cirrus_bank_base[bank_index];
2104 if ((s->gr[0x0B] & 0x14) == 0x14) {
2105 bank_offset <<= 4;
2106 } else if (s->gr[0x0B] & 0x02) {
2107 bank_offset <<= 3;
2108 }
2109 bank_offset &= s->cirrus_addr_mask;
2110 mode = s->gr[0x05] & 0x7;
2111 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2112 *(s->vram_ptr + bank_offset) = mem_value;
2113 cpu_physical_memory_set_dirty(s->vram_offset +
2114 bank_offset);
2115 } else {
2116 if ((s->gr[0x0B] & 0x14) != 0x14) {
2117 cirrus_mem_writeb_mode4and5_8bpp(s, mode,
2118 bank_offset,
2119 mem_value);
2120 } else {
2121 cirrus_mem_writeb_mode4and5_16bpp(s, mode,
2122 bank_offset,
2123 mem_value);
2124 }
2125 }
2126 }
2127 }
2128 } else if (addr >= 0x18000 && addr < 0x18100) {
2129 /* memory-mapped I/O */
2130 if ((s->sr[0x17] & 0x44) == 0x04) {
2131 cirrus_mmio_blt_write(s, addr & 0xff, mem_value);
2132 }
2133 } else {
2134 #ifdef DEBUG_CIRRUS
2135 printf("cirrus: mem_writeb %06x value %02x\n", addr, mem_value);
2136 #endif
2137 }
2138 }
2139
2140 static void cirrus_vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
2141 {
2142 #ifdef TARGET_WORDS_BIGENDIAN
2143 cirrus_vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
2144 cirrus_vga_mem_writeb(opaque, addr + 1, val & 0xff);
2145 #else
2146 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2147 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2148 #endif
2149 }
2150
2151 static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
2152 {
2153 #ifdef TARGET_WORDS_BIGENDIAN
2154 cirrus_vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
2155 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2156 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2157 cirrus_vga_mem_writeb(opaque, addr + 3, val & 0xff);
2158 #else
2159 cirrus_vga_mem_writeb(opaque, addr, val & 0xff);
2160 cirrus_vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2161 cirrus_vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2162 cirrus_vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2163 #endif
2164 }
2165
2166 static CPUReadMemoryFunc *cirrus_vga_mem_read[3] = {
2167 cirrus_vga_mem_readb,
2168 cirrus_vga_mem_readw,
2169 cirrus_vga_mem_readl,
2170 };
2171
2172 static CPUWriteMemoryFunc *cirrus_vga_mem_write[3] = {
2173 cirrus_vga_mem_writeb,
2174 cirrus_vga_mem_writew,
2175 cirrus_vga_mem_writel,
2176 };
2177
2178 /***************************************
2179 *
2180 * hardware cursor
2181 *
2182 ***************************************/
2183
2184 static inline void invalidate_cursor1(CirrusVGAState *s)
2185 {
2186 if (s->last_hw_cursor_size) {
2187 vga_invalidate_scanlines((VGAState *)s,
2188 s->last_hw_cursor_y + s->last_hw_cursor_y_start,
2189 s->last_hw_cursor_y + s->last_hw_cursor_y_end);
2190 }
2191 }
2192
2193 static inline void cirrus_cursor_compute_yrange(CirrusVGAState *s)
2194 {
2195 const uint8_t *src;
2196 uint32_t content;
2197 int y, y_min, y_max;
2198
2199 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2200 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2201 src += (s->sr[0x13] & 0x3c) * 256;
2202 y_min = 64;
2203 y_max = -1;
2204 for(y = 0; y < 64; y++) {
2205 content = ((uint32_t *)src)[0] |
2206 ((uint32_t *)src)[1] |
2207 ((uint32_t *)src)[2] |
2208 ((uint32_t *)src)[3];
2209 if (content) {
2210 if (y < y_min)
2211 y_min = y;
2212 if (y > y_max)
2213 y_max = y;
2214 }
2215 src += 16;
2216 }
2217 } else {
2218 src += (s->sr[0x13] & 0x3f) * 256;
2219 y_min = 32;
2220 y_max = -1;
2221 for(y = 0; y < 32; y++) {
2222 content = ((uint32_t *)src)[0] |
2223 ((uint32_t *)(src + 128))[0];
2224 if (content) {
2225 if (y < y_min)
2226 y_min = y;
2227 if (y > y_max)
2228 y_max = y;
2229 }
2230 src += 4;
2231 }
2232 }
2233 if (y_min > y_max) {
2234 s->last_hw_cursor_y_start = 0;
2235 s->last_hw_cursor_y_end = 0;
2236 } else {
2237 s->last_hw_cursor_y_start = y_min;
2238 s->last_hw_cursor_y_end = y_max + 1;
2239 }
2240 }
2241
2242 /* NOTE: we do not currently handle the cursor bitmap change, so we
2243 update the cursor only if it moves. */
2244 static void cirrus_cursor_invalidate(VGAState *s1)
2245 {
2246 CirrusVGAState *s = (CirrusVGAState *)s1;
2247 int size;
2248
2249 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW)) {
2250 size = 0;
2251 } else {
2252 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE)
2253 size = 64;
2254 else
2255 size = 32;
2256 }
2257 /* invalidate last cursor and new cursor if any change */
2258 if (s->last_hw_cursor_size != size ||
2259 s->last_hw_cursor_x != s->hw_cursor_x ||
2260 s->last_hw_cursor_y != s->hw_cursor_y) {
2261
2262 invalidate_cursor1(s);
2263
2264 s->last_hw_cursor_size = size;
2265 s->last_hw_cursor_x = s->hw_cursor_x;
2266 s->last_hw_cursor_y = s->hw_cursor_y;
2267 /* compute the real cursor min and max y */
2268 cirrus_cursor_compute_yrange(s);
2269 invalidate_cursor1(s);
2270 }
2271 }
2272
2273 static void cirrus_cursor_draw_line(VGAState *s1, uint8_t *d1, int scr_y)
2274 {
2275 CirrusVGAState *s = (CirrusVGAState *)s1;
2276 int w, h, bpp, x1, x2, poffset;
2277 unsigned int color0, color1;
2278 const uint8_t *palette, *src;
2279 uint32_t content;
2280
2281 if (!(s->sr[0x12] & CIRRUS_CURSOR_SHOW))
2282 return;
2283 /* fast test to see if the cursor intersects with the scan line */
2284 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2285 h = 64;
2286 } else {
2287 h = 32;
2288 }
2289 if (scr_y < s->hw_cursor_y ||
2290 scr_y >= (s->hw_cursor_y + h))
2291 return;
2292
2293 src = s->vram_ptr + s->real_vram_size - 16 * 1024;
2294 if (s->sr[0x12] & CIRRUS_CURSOR_LARGE) {
2295 src += (s->sr[0x13] & 0x3c) * 256;
2296 src += (scr_y - s->hw_cursor_y) * 16;
2297 poffset = 8;
2298 content = ((uint32_t *)src)[0] |
2299 ((uint32_t *)src)[1] |
2300 ((uint32_t *)src)[2] |
2301 ((uint32_t *)src)[3];
2302 } else {
2303 src += (s->sr[0x13] & 0x3f) * 256;
2304 src += (scr_y - s->hw_cursor_y) * 4;
2305 poffset = 128;
2306 content = ((uint32_t *)src)[0] |
2307 ((uint32_t *)(src + 128))[0];
2308 }
2309 /* if nothing to draw, no need to continue */
2310 if (!content)
2311 return;
2312 w = h;
2313
2314 x1 = s->hw_cursor_x;
2315 if (x1 >= s->last_scr_width)
2316 return;
2317 x2 = s->hw_cursor_x + w;
2318 if (x2 > s->last_scr_width)
2319 x2 = s->last_scr_width;
2320 w = x2 - x1;
2321 palette = s->cirrus_hidden_palette;
2322 color0 = s->rgb_to_pixel(c6_to_8(palette[0x0 * 3]),
2323 c6_to_8(palette[0x0 * 3 + 1]),
2324 c6_to_8(palette[0x0 * 3 + 2]));
2325 color1 = s->rgb_to_pixel(c6_to_8(palette[0xf * 3]),
2326 c6_to_8(palette[0xf * 3 + 1]),
2327 c6_to_8(palette[0xf * 3 + 2]));
2328 bpp = ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
2329 d1 += x1 * bpp;
2330 switch(ds_get_bits_per_pixel(s->ds)) {
2331 default:
2332 break;
2333 case 8:
2334 vga_draw_cursor_line_8(d1, src, poffset, w, color0, color1, 0xff);
2335 break;
2336 case 15:
2337 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0x7fff);
2338 break;
2339 case 16:
2340 vga_draw_cursor_line_16(d1, src, poffset, w, color0, color1, 0xffff);
2341 break;
2342 case 32:
2343 vga_draw_cursor_line_32(d1, src, poffset, w, color0, color1, 0xffffff);
2344 break;
2345 }
2346 }
2347
2348 /***************************************
2349 *
2350 * LFB memory access
2351 *
2352 ***************************************/
2353
2354 static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)
2355 {
2356 CirrusVGAState *s = (CirrusVGAState *) opaque;
2357 uint32_t ret;
2358
2359 addr &= s->cirrus_addr_mask;
2360
2361 if (((s->sr[0x17] & 0x44) == 0x44) &&
2362 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2363 /* memory-mapped I/O */
2364 ret = cirrus_mmio_blt_read(s, addr & 0xff);
2365 } else if (0) {
2366 /* XXX handle bitblt */
2367 ret = 0xff;
2368 } else {
2369 /* video memory */
2370 if ((s->gr[0x0B] & 0x14) == 0x14) {
2371 addr <<= 4;
2372 } else if (s->gr[0x0B] & 0x02) {
2373 addr <<= 3;
2374 }
2375 addr &= s->cirrus_addr_mask;
2376 ret = *(s->vram_ptr + addr);
2377 }
2378
2379 return ret;
2380 }
2381
2382 static uint32_t cirrus_linear_readw(void *opaque, target_phys_addr_t addr)
2383 {
2384 uint32_t v;
2385 #ifdef TARGET_WORDS_BIGENDIAN
2386 v = cirrus_linear_readb(opaque, addr) << 8;
2387 v |= cirrus_linear_readb(opaque, addr + 1);
2388 #else
2389 v = cirrus_linear_readb(opaque, addr);
2390 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2391 #endif
2392 return v;
2393 }
2394
2395 static uint32_t cirrus_linear_readl(void *opaque, target_phys_addr_t addr)
2396 {
2397 uint32_t v;
2398 #ifdef TARGET_WORDS_BIGENDIAN
2399 v = cirrus_linear_readb(opaque, addr) << 24;
2400 v |= cirrus_linear_readb(opaque, addr + 1) << 16;
2401 v |= cirrus_linear_readb(opaque, addr + 2) << 8;
2402 v |= cirrus_linear_readb(opaque, addr + 3);
2403 #else
2404 v = cirrus_linear_readb(opaque, addr);
2405 v |= cirrus_linear_readb(opaque, addr + 1) << 8;
2406 v |= cirrus_linear_readb(opaque, addr + 2) << 16;
2407 v |= cirrus_linear_readb(opaque, addr + 3) << 24;
2408 #endif
2409 return v;
2410 }
2411
2412 static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr,
2413 uint32_t val)
2414 {
2415 CirrusVGAState *s = (CirrusVGAState *) opaque;
2416 unsigned mode;
2417
2418 addr &= s->cirrus_addr_mask;
2419
2420 if (((s->sr[0x17] & 0x44) == 0x44) &&
2421 ((addr & s->linear_mmio_mask) == s->linear_mmio_mask)) {
2422 /* memory-mapped I/O */
2423 cirrus_mmio_blt_write(s, addr & 0xff, val);
2424 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2425 /* bitblt */
2426 *s->cirrus_srcptr++ = (uint8_t) val;
2427 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2428 cirrus_bitblt_cputovideo_next(s);
2429 }
2430 } else {
2431 /* video memory */
2432 if ((s->gr[0x0B] & 0x14) == 0x14) {
2433 addr <<= 4;
2434 } else if (s->gr[0x0B] & 0x02) {
2435 addr <<= 3;
2436 }
2437 addr &= s->cirrus_addr_mask;
2438
2439 mode = s->gr[0x05] & 0x7;
2440 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2441 *(s->vram_ptr + addr) = (uint8_t) val;
2442 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2443 } else {
2444 if ((s->gr[0x0B] & 0x14) != 0x14) {
2445 cirrus_mem_writeb_mode4and5_8bpp(s, mode, addr, val);
2446 } else {
2447 cirrus_mem_writeb_mode4and5_16bpp(s, mode, addr, val);
2448 }
2449 }
2450 }
2451 }
2452
2453 static void cirrus_linear_writew(void *opaque, target_phys_addr_t addr,
2454 uint32_t val)
2455 {
2456 #ifdef TARGET_WORDS_BIGENDIAN
2457 cirrus_linear_writeb(opaque, addr, (val >> 8) & 0xff);
2458 cirrus_linear_writeb(opaque, addr + 1, val & 0xff);
2459 #else
2460 cirrus_linear_writeb(opaque, addr, val & 0xff);
2461 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2462 #endif
2463 }
2464
2465 static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr,
2466 uint32_t val)
2467 {
2468 #ifdef TARGET_WORDS_BIGENDIAN
2469 cirrus_linear_writeb(opaque, addr, (val >> 24) & 0xff);
2470 cirrus_linear_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2471 cirrus_linear_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2472 cirrus_linear_writeb(opaque, addr + 3, val & 0xff);
2473 #else
2474 cirrus_linear_writeb(opaque, addr, val & 0xff);
2475 cirrus_linear_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2476 cirrus_linear_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2477 cirrus_linear_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2478 #endif
2479 }
2480
2481
2482 static CPUReadMemoryFunc *cirrus_linear_read[3] = {
2483 cirrus_linear_readb,
2484 cirrus_linear_readw,
2485 cirrus_linear_readl,
2486 };
2487
2488 static CPUWriteMemoryFunc *cirrus_linear_write[3] = {
2489 cirrus_linear_writeb,
2490 cirrus_linear_writew,
2491 cirrus_linear_writel,
2492 };
2493
2494 static void cirrus_linear_mem_writeb(void *opaque, target_phys_addr_t addr,
2495 uint32_t val)
2496 {
2497 CirrusVGAState *s = (CirrusVGAState *) opaque;
2498
2499 addr &= s->cirrus_addr_mask;
2500 *(s->vram_ptr + addr) = val;
2501 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2502 }
2503
2504 static void cirrus_linear_mem_writew(void *opaque, target_phys_addr_t addr,
2505 uint32_t val)
2506 {
2507 CirrusVGAState *s = (CirrusVGAState *) opaque;
2508
2509 addr &= s->cirrus_addr_mask;
2510 cpu_to_le16w((uint16_t *)(s->vram_ptr + addr), val);
2511 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2512 }
2513
2514 static void cirrus_linear_mem_writel(void *opaque, target_phys_addr_t addr,
2515 uint32_t val)
2516 {
2517 CirrusVGAState *s = (CirrusVGAState *) opaque;
2518
2519 addr &= s->cirrus_addr_mask;
2520 cpu_to_le32w((uint32_t *)(s->vram_ptr + addr), val);
2521 cpu_physical_memory_set_dirty(s->vram_offset + addr);
2522 }
2523
2524 /***************************************
2525 *
2526 * system to screen memory access
2527 *
2528 ***************************************/
2529
2530
2531 static uint32_t cirrus_linear_bitblt_readb(void *opaque, target_phys_addr_t addr)
2532 {
2533 uint32_t ret;
2534
2535 /* XXX handle bitblt */
2536 ret = 0xff;
2537 return ret;
2538 }
2539
2540 static uint32_t cirrus_linear_bitblt_readw(void *opaque, target_phys_addr_t addr)
2541 {
2542 uint32_t v;
2543 #ifdef TARGET_WORDS_BIGENDIAN
2544 v = cirrus_linear_bitblt_readb(opaque, addr) << 8;
2545 v |= cirrus_linear_bitblt_readb(opaque, addr + 1);
2546 #else
2547 v = cirrus_linear_bitblt_readb(opaque, addr);
2548 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2549 #endif
2550 return v;
2551 }
2552
2553 static uint32_t cirrus_linear_bitblt_readl(void *opaque, target_phys_addr_t addr)
2554 {
2555 uint32_t v;
2556 #ifdef TARGET_WORDS_BIGENDIAN
2557 v = cirrus_linear_bitblt_readb(opaque, addr) << 24;
2558 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 16;
2559 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 8;
2560 v |= cirrus_linear_bitblt_readb(opaque, addr + 3);
2561 #else
2562 v = cirrus_linear_bitblt_readb(opaque, addr);
2563 v |= cirrus_linear_bitblt_readb(opaque, addr + 1) << 8;
2564 v |= cirrus_linear_bitblt_readb(opaque, addr + 2) << 16;
2565 v |= cirrus_linear_bitblt_readb(opaque, addr + 3) << 24;
2566 #endif
2567 return v;
2568 }
2569
2570 static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr,
2571 uint32_t val)
2572 {
2573 CirrusVGAState *s = (CirrusVGAState *) opaque;
2574
2575 if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2576 /* bitblt */
2577 *s->cirrus_srcptr++ = (uint8_t) val;
2578 if (s->cirrus_srcptr >= s->cirrus_srcptr_end) {
2579 cirrus_bitblt_cputovideo_next(s);
2580 }
2581 }
2582 }
2583
2584 static void cirrus_linear_bitblt_writew(void *opaque, target_phys_addr_t addr,
2585 uint32_t val)
2586 {
2587 #ifdef TARGET_WORDS_BIGENDIAN
2588 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 8) & 0xff);
2589 cirrus_linear_bitblt_writeb(opaque, addr + 1, val & 0xff);
2590 #else
2591 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2592 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2593 #endif
2594 }
2595
2596 static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,
2597 uint32_t val)
2598 {
2599 #ifdef TARGET_WORDS_BIGENDIAN
2600 cirrus_linear_bitblt_writeb(opaque, addr, (val >> 24) & 0xff);
2601 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 16) & 0xff);
2602 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 8) & 0xff);
2603 cirrus_linear_bitblt_writeb(opaque, addr + 3, val & 0xff);
2604 #else
2605 cirrus_linear_bitblt_writeb(opaque, addr, val & 0xff);
2606 cirrus_linear_bitblt_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2607 cirrus_linear_bitblt_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2608 cirrus_linear_bitblt_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2609 #endif
2610 }
2611
2612
2613 static CPUReadMemoryFunc *cirrus_linear_bitblt_read[3] = {
2614 cirrus_linear_bitblt_readb,
2615 cirrus_linear_bitblt_readw,
2616 cirrus_linear_bitblt_readl,
2617 };
2618
2619 static CPUWriteMemoryFunc *cirrus_linear_bitblt_write[3] = {
2620 cirrus_linear_bitblt_writeb,
2621 cirrus_linear_bitblt_writew,
2622 cirrus_linear_bitblt_writel,
2623 };
2624
2625 static void map_linear_vram(CirrusVGAState *s)
2626 {
2627 vga_dirty_log_stop((VGAState *)s);
2628
2629 if (!s->map_addr && s->lfb_addr && s->lfb_end) {
2630 s->map_addr = s->lfb_addr;
2631 s->map_end = s->lfb_end;
2632 cpu_register_physical_memory(s->map_addr, s->map_end - s->map_addr, s->vram_offset);
2633 }
2634
2635 if (!s->map_addr)
2636 return;
2637
2638 s->lfb_vram_mapped = 0;
2639
2640 if (!(s->cirrus_srcptr != s->cirrus_srcptr_end)
2641 && !((s->sr[0x07] & 0x01) == 0)
2642 && !((s->gr[0x0B] & 0x14) == 0x14)
2643 && !(s->gr[0x0B] & 0x02)) {
2644
2645 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x8000,
2646 (s->vram_offset + s->cirrus_bank_base[0]) | IO_MEM_RAM);
2647 cpu_register_physical_memory(isa_mem_base + 0xa8000, 0x8000,
2648 (s->vram_offset + s->cirrus_bank_base[1]) | IO_MEM_RAM);
2649
2650 s->lfb_vram_mapped = 1;
2651 }
2652 else {
2653 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2654 s->vga_io_memory);
2655 }
2656
2657 vga_dirty_log_start((VGAState *)s);
2658 }
2659
2660 static void unmap_linear_vram(CirrusVGAState *s)
2661 {
2662 vga_dirty_log_stop((VGAState *)s);
2663
2664 if (s->map_addr && s->lfb_addr && s->lfb_end)
2665 s->map_addr = s->map_end = 0;
2666
2667 cpu_register_physical_memory(isa_mem_base + 0xa0000, 0x20000,
2668 s->vga_io_memory);
2669
2670 vga_dirty_log_start((VGAState *)s);
2671 }
2672
2673 /* Compute the memory access functions */
2674 static void cirrus_update_memory_access(CirrusVGAState *s)
2675 {
2676 unsigned mode;
2677
2678 if ((s->sr[0x17] & 0x44) == 0x44) {
2679 goto generic_io;
2680 } else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
2681 goto generic_io;
2682 } else {
2683 if ((s->gr[0x0B] & 0x14) == 0x14) {
2684 goto generic_io;
2685 } else if (s->gr[0x0B] & 0x02) {
2686 goto generic_io;
2687 }
2688
2689 mode = s->gr[0x05] & 0x7;
2690 if (mode < 4 || mode > 5 || ((s->gr[0x0B] & 0x4) == 0)) {
2691 map_linear_vram(s);
2692 s->cirrus_linear_write[0] = cirrus_linear_mem_writeb;
2693 s->cirrus_linear_write[1] = cirrus_linear_mem_writew;
2694 s->cirrus_linear_write[2] = cirrus_linear_mem_writel;
2695 } else {
2696 generic_io:
2697 unmap_linear_vram(s);
2698 s->cirrus_linear_write[0] = cirrus_linear_writeb;
2699 s->cirrus_linear_write[1] = cirrus_linear_writew;
2700 s->cirrus_linear_write[2] = cirrus_linear_writel;
2701 }
2702 }
2703 }
2704
2705
2706 /* I/O ports */
2707
2708 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
2709 {
2710 CirrusVGAState *s = opaque;
2711 int val, index;
2712
2713 /* check port range access depending on color/monochrome mode */
2714 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2715 || (addr >= 0x3d0 && addr <= 0x3df
2716 && !(s->msr & MSR_COLOR_EMULATION))) {
2717 val = 0xff;
2718 } else {
2719 switch (addr) {
2720 case 0x3c0:
2721 if (s->ar_flip_flop == 0) {
2722 val = s->ar_index;
2723 } else {
2724 val = 0;
2725 }
2726 break;
2727 case 0x3c1:
2728 index = s->ar_index & 0x1f;
2729 if (index < 21)
2730 val = s->ar[index];
2731 else
2732 val = 0;
2733 break;
2734 case 0x3c2:
2735 val = s->st00;
2736 break;
2737 case 0x3c4:
2738 val = s->sr_index;
2739 break;
2740 case 0x3c5:
2741 if (cirrus_hook_read_sr(s, s->sr_index, &val))
2742 break;
2743 val = s->sr[s->sr_index];
2744 #ifdef DEBUG_VGA_REG
2745 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
2746 #endif
2747 break;
2748 case 0x3c6:
2749 cirrus_read_hidden_dac(s, &val);
2750 break;
2751 case 0x3c7:
2752 val = s->dac_state;
2753 break;
2754 case 0x3c8:
2755 val = s->dac_write_index;
2756 s->cirrus_hidden_dac_lockindex = 0;
2757 break;
2758 case 0x3c9:
2759 if (cirrus_hook_read_palette(s, &val))
2760 break;
2761 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
2762 if (++s->dac_sub_index == 3) {
2763 s->dac_sub_index = 0;
2764 s->dac_read_index++;
2765 }
2766 break;
2767 case 0x3ca:
2768 val = s->fcr;
2769 break;
2770 case 0x3cc:
2771 val = s->msr;
2772 break;
2773 case 0x3ce:
2774 val = s->gr_index;
2775 break;
2776 case 0x3cf:
2777 if (cirrus_hook_read_gr(s, s->gr_index, &val))
2778 break;
2779 val = s->gr[s->gr_index];
2780 #ifdef DEBUG_VGA_REG
2781 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
2782 #endif
2783 break;
2784 case 0x3b4:
2785 case 0x3d4:
2786 val = s->cr_index;
2787 break;
2788 case 0x3b5:
2789 case 0x3d5:
2790 if (cirrus_hook_read_cr(s, s->cr_index, &val))
2791 break;
2792 val = s->cr[s->cr_index];
2793 #ifdef DEBUG_VGA_REG
2794 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
2795 #endif
2796 break;
2797 case 0x3ba:
2798 case 0x3da:
2799 /* just toggle to fool polling */
2800 val = s->st01 = s->retrace((VGAState *) s);
2801 s->ar_flip_flop = 0;
2802 break;
2803 default:
2804 val = 0x00;
2805 break;
2806 }
2807 }
2808 #if defined(DEBUG_VGA)
2809 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
2810 #endif
2811 return val;
2812 }
2813
2814 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
2815 {
2816 CirrusVGAState *s = opaque;
2817 int index;
2818
2819 /* check port range access depending on color/monochrome mode */
2820 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION))
2821 || (addr >= 0x3d0 && addr <= 0x3df
2822 && !(s->msr & MSR_COLOR_EMULATION)))
2823 return;
2824
2825 #ifdef DEBUG_VGA
2826 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
2827 #endif
2828
2829 switch (addr) {
2830 case 0x3c0:
2831 if (s->ar_flip_flop == 0) {
2832 val &= 0x3f;
2833 s->ar_index = val;
2834 } else {
2835 index = s->ar_index & 0x1f;
2836 switch (index) {
2837 case 0x00 ... 0x0f:
2838 s->ar[index] = val & 0x3f;
2839 break;
2840 case 0x10:
2841 s->ar[index] = val & ~0x10;
2842 break;
2843 case 0x11:
2844 s->ar[index] = val;
2845 break;
2846 case 0x12:
2847 s->ar[index] = val & ~0xc0;
2848 break;
2849 case 0x13:
2850 s->ar[index] = val & ~0xf0;
2851 break;
2852 case 0x14:
2853 s->ar[index] = val & ~0xf0;
2854 break;
2855 default:
2856 break;
2857 }
2858 }
2859 s->ar_flip_flop ^= 1;
2860 break;
2861 case 0x3c2:
2862 s->msr = val & ~0x10;
2863 s->update_retrace_info((VGAState *) s);
2864 break;
2865 case 0x3c4:
2866 s->sr_index = val;
2867 break;
2868 case 0x3c5:
2869 if (cirrus_hook_write_sr(s, s->sr_index, val))
2870 break;
2871 #ifdef DEBUG_VGA_REG
2872 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
2873 #endif
2874 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
2875 if (s->sr_index == 1) s->update_retrace_info((VGAState *) s);
2876 break;
2877 case 0x3c6:
2878 cirrus_write_hidden_dac(s, val);
2879 break;
2880 case 0x3c7:
2881 s->dac_read_index = val;
2882 s->dac_sub_index = 0;
2883 s->dac_state = 3;
2884 break;
2885 case 0x3c8:
2886 s->dac_write_index = val;
2887 s->dac_sub_index = 0;
2888 s->dac_state = 0;
2889 break;
2890 case 0x3c9:
2891 if (cirrus_hook_write_palette(s, val))
2892 break;
2893 s->dac_cache[s->dac_sub_index] = val;
2894 if (++s->dac_sub_index == 3) {
2895 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
2896 s->dac_sub_index = 0;
2897 s->dac_write_index++;
2898 }
2899 break;
2900 case 0x3ce:
2901 s->gr_index = val;
2902 break;
2903 case 0x3cf:
2904 if (cirrus_hook_write_gr(s, s->gr_index, val))
2905 break;
2906 #ifdef DEBUG_VGA_REG
2907 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
2908 #endif
2909 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
2910 break;
2911 case 0x3b4:
2912 case 0x3d4:
2913 s->cr_index = val;
2914 break;
2915 case 0x3b5:
2916 case 0x3d5:
2917 if (cirrus_hook_write_cr(s, s->cr_index, val))
2918 break;
2919 #ifdef DEBUG_VGA_REG
2920 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
2921 #endif
2922 /* handle CR0-7 protection */
2923 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
2924 /* can always write bit 4 of CR7 */
2925 if (s->cr_index == 7)
2926 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
2927 return;
2928 }
2929 switch (s->cr_index) {
2930 case 0x01: /* horizontal display end */
2931 case 0x07:
2932 case 0x09:
2933 case 0x0c:
2934 case 0x0d:
2935 case 0x12: /* vertical display end */
2936 s->cr[s->cr_index] = val;
2937 break;
2938
2939 default:
2940 s->cr[s->cr_index] = val;
2941 break;
2942 }
2943
2944 switch(s->cr_index) {
2945 case 0x00:
2946 case 0x04:
2947 case 0x05:
2948 case 0x06:
2949 case 0x07:
2950 case 0x11:
2951 case 0x17:
2952 s->update_retrace_info((VGAState *) s);
2953 break;
2954 }
2955 break;
2956 case 0x3ba:
2957 case 0x3da:
2958 s->fcr = val & 0x10;
2959 break;
2960 }
2961 }
2962
2963 /***************************************
2964 *
2965 * memory-mapped I/O access
2966 *
2967 ***************************************/
2968
2969 static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr)
2970 {
2971 CirrusVGAState *s = (CirrusVGAState *) opaque;
2972
2973 addr &= CIRRUS_PNPMMIO_SIZE - 1;
2974
2975 if (addr >= 0x100) {
2976 return cirrus_mmio_blt_read(s, addr - 0x100);
2977 } else {
2978 return vga_ioport_read(s, addr + 0x3c0);
2979 }
2980 }
2981
2982 static uint32_t cirrus_mmio_readw(void *opaque, target_phys_addr_t addr)
2983 {
2984 uint32_t v;
2985 #ifdef TARGET_WORDS_BIGENDIAN
2986 v = cirrus_mmio_readb(opaque, addr) << 8;
2987 v |= cirrus_mmio_readb(opaque, addr + 1);
2988 #else
2989 v = cirrus_mmio_readb(opaque, addr);
2990 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
2991 #endif
2992 return v;
2993 }
2994
2995 static uint32_t cirrus_mmio_readl(void *opaque, target_phys_addr_t addr)
2996 {
2997 uint32_t v;
2998 #ifdef TARGET_WORDS_BIGENDIAN
2999 v = cirrus_mmio_readb(opaque, addr) << 24;
3000 v |= cirrus_mmio_readb(opaque, addr + 1) << 16;
3001 v |= cirrus_mmio_readb(opaque, addr + 2) << 8;
3002 v |= cirrus_mmio_readb(opaque, addr + 3);
3003 #else
3004 v = cirrus_mmio_readb(opaque, addr);
3005 v |= cirrus_mmio_readb(opaque, addr + 1) << 8;
3006 v |= cirrus_mmio_readb(opaque, addr + 2) << 16;
3007 v |= cirrus_mmio_readb(opaque, addr + 3) << 24;
3008 #endif
3009 return v;
3010 }
3011
3012 static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr,
3013 uint32_t val)
3014 {
3015 CirrusVGAState *s = (CirrusVGAState *) opaque;
3016
3017 addr &= CIRRUS_PNPMMIO_SIZE - 1;
3018
3019 if (addr >= 0x100) {
3020 cirrus_mmio_blt_write(s, addr - 0x100, val);
3021 } else {
3022 vga_ioport_write(s, addr + 0x3c0, val);
3023 }
3024 }
3025
3026 static void cirrus_mmio_writew(void *opaque, target_phys_addr_t addr,
3027 uint32_t val)
3028 {
3029 #ifdef TARGET_WORDS_BIGENDIAN
3030 cirrus_mmio_writeb(opaque, addr, (val >> 8) & 0xff);
3031 cirrus_mmio_writeb(opaque, addr + 1, val & 0xff);
3032 #else
3033 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3034 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3035 #endif
3036 }
3037
3038 static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr,
3039 uint32_t val)
3040 {
3041 #ifdef TARGET_WORDS_BIGENDIAN
3042 cirrus_mmio_writeb(opaque, addr, (val >> 24) & 0xff);
3043 cirrus_mmio_writeb(opaque, addr + 1, (val >> 16) & 0xff);
3044 cirrus_mmio_writeb(opaque, addr + 2, (val >> 8) & 0xff);
3045 cirrus_mmio_writeb(opaque, addr + 3, val & 0xff);
3046 #else
3047 cirrus_mmio_writeb(opaque, addr, val & 0xff);
3048 cirrus_mmio_writeb(opaque, addr + 1, (val >> 8) & 0xff);
3049 cirrus_mmio_writeb(opaque, addr + 2, (val >> 16) & 0xff);
3050 cirrus_mmio_writeb(opaque, addr + 3, (val >> 24) & 0xff);
3051 #endif
3052 }
3053
3054
3055 static CPUReadMemoryFunc *cirrus_mmio_read[3] = {
3056 cirrus_mmio_readb,
3057 cirrus_mmio_readw,
3058 cirrus_mmio_readl,
3059 };
3060
3061 static CPUWriteMemoryFunc *cirrus_mmio_write[3] = {
3062 cirrus_mmio_writeb,
3063 cirrus_mmio_writew,
3064 cirrus_mmio_writel,
3065 };
3066
3067 /* load/save state */
3068
3069 static void cirrus_vga_save(QEMUFile *f, void *opaque)
3070 {
3071 CirrusVGAState *s = opaque;
3072
3073 if (s->pci_dev)
3074 pci_device_save(s->pci_dev, f);
3075
3076 qemu_put_be32s(f, &s->latch);
3077 qemu_put_8s(f, &s->sr_index);
3078 qemu_put_buffer(f, s->sr, 256);
3079 qemu_put_8s(f, &s->gr_index);
3080 qemu_put_8s(f, &s->cirrus_shadow_gr0);
3081 qemu_put_8s(f, &s->cirrus_shadow_gr1);
3082 qemu_put_buffer(f, s->gr + 2, 254);
3083 qemu_put_8s(f, &s->ar_index);
3084 qemu_put_buffer(f, s->ar, 21);
3085 qemu_put_be32(f, s->ar_flip_flop);
3086 qemu_put_8s(f, &s->cr_index);
3087 qemu_put_buffer(f, s->cr, 256);
3088 qemu_put_8s(f, &s->msr);
3089 qemu_put_8s(f, &s->fcr);
3090 qemu_put_8s(f, &s->st00);
3091 qemu_put_8s(f, &s->st01);
3092
3093 qemu_put_8s(f, &s->dac_state);
3094 qemu_put_8s(f, &s->dac_sub_index);
3095 qemu_put_8s(f, &s->dac_read_index);
3096 qemu_put_8s(f, &s->dac_write_index);
3097 qemu_put_buffer(f, s->dac_cache, 3);
3098 qemu_put_buffer(f, s->palette, 768);
3099
3100 qemu_put_be32(f, s->bank_offset);
3101
3102 qemu_put_8s(f, &s->cirrus_hidden_dac_lockindex);
3103 qemu_put_8s(f, &s->cirrus_hidden_dac_data);
3104
3105 qemu_put_be32s(f, &s->hw_cursor_x);
3106 qemu_put_be32s(f, &s->hw_cursor_y);
3107 /* XXX: we do not save the bitblt state - we assume we do not save
3108 the state when the blitter is active */
3109 }
3110
3111 static int cirrus_vga_load(QEMUFile *f, void *opaque, int version_id)
3112 {
3113 CirrusVGAState *s = opaque;
3114 int ret;
3115
3116 if (version_id > 2)
3117 return -EINVAL;
3118
3119 if (s->pci_dev && version_id >= 2) {
3120 ret = pci_device_load(s->pci_dev, f);
3121 if (ret < 0)
3122 return ret;
3123 }
3124
3125 qemu_get_be32s(f, &s->latch);
3126 qemu_get_8s(f, &s->sr_index);
3127 qemu_get_buffer(f, s->sr, 256);
3128 qemu_get_8s(f, &s->gr_index);
3129 qemu_get_8s(f, &s->cirrus_shadow_gr0);
3130 qemu_get_8s(f, &s->cirrus_shadow_gr1);
3131 s->gr[0x00] = s->cirrus_shadow_gr0 & 0x0f;
3132 s->gr[0x01] = s->cirrus_shadow_gr1 & 0x0f;
3133 qemu_get_buffer(f, s->gr + 2, 254);
3134 qemu_get_8s(f, &s->ar_index);
3135 qemu_get_buffer(f, s->ar, 21);
3136 s->ar_flip_flop=qemu_get_be32(f);
3137 qemu_get_8s(f, &s->cr_index);
3138 qemu_get_buffer(f, s->cr, 256);
3139 qemu_get_8s(f, &s->msr);
3140 qemu_get_8s(f, &s->fcr);
3141 qemu_get_8s(f, &s->st00);
3142 qemu_get_8s(f, &s->st01);
3143
3144 qemu_get_8s(f, &s->dac_state);
3145 qemu_get_8s(f, &s->dac_sub_index);
3146 qemu_get_8s(f, &s->dac_read_index);
3147 qemu_get_8s(f, &s->dac_write_index);
3148 qemu_get_buffer(f, s->dac_cache, 3);
3149 qemu_get_buffer(f, s->palette, 768);
3150
3151 s->bank_offset=qemu_get_be32(f);
3152
3153 qemu_get_8s(f, &s->cirrus_hidden_dac_lockindex);
3154 qemu_get_8s(f, &s->cirrus_hidden_dac_data);
3155
3156 qemu_get_be32s(f, &s->hw_cursor_x);
3157 qemu_get_be32s(f, &s->hw_cursor_y);
3158
3159 cirrus_update_memory_access(s);
3160 /* force refresh */
3161 s->graphic_mode = -1;
3162 cirrus_update_bank_ptr(s, 0);
3163 cirrus_update_bank_ptr(s, 1);
3164 return 0;
3165 }
3166
3167 /***************************************
3168 *
3169 * initialize
3170 *
3171 ***************************************/
3172
3173 static void cirrus_reset(void *opaque)
3174 {
3175 CirrusVGAState *s = opaque;
3176
3177 vga_reset(s);
3178 unmap_linear_vram(s);
3179 s->sr[0x06] = 0x0f;
3180 if (s->device_id == CIRRUS_ID_CLGD5446) {
3181 /* 4MB 64 bit memory config, always PCI */
3182 s->sr[0x1F] = 0x2d; // MemClock
3183 s->gr[0x18] = 0x0f; // fastest memory configuration
3184 s->sr[0x0f] = 0x98;
3185 s->sr[0x17] = 0x20;
3186 s->sr[0x15] = 0x04; /* memory size, 3=2MB, 4=4MB */
3187 } else {
3188 s->sr[0x1F] = 0x22; // MemClock
3189 s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
3190 s->sr[0x17] = s->bustype;
3191 s->sr[0x15] = 0x03; /* memory size, 3=2MB, 4=4MB */
3192 }
3193 s->cr[0x27] = s->device_id;
3194
3195 /* Win2K seems to assume that the pattern buffer is at 0xff
3196 initially ! */
3197 memset(s->vram_ptr, 0xff, s->real_vram_size);
3198
3199 s->cirrus_hidden_dac_lockindex = 5;
3200 s->cirrus_hidden_dac_data = 0;
3201 }
3202
3203 static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)
3204 {
3205 int i;
3206 static int inited;
3207
3208 if (!inited) {
3209 inited = 1;
3210 for(i = 0;i < 256; i++)
3211 rop_to_index[i] = CIRRUS_ROP_NOP_INDEX; /* nop rop */
3212 rop_to_index[CIRRUS_ROP_0] = 0;
3213 rop_to_index[CIRRUS_ROP_SRC_AND_DST] = 1;
3214 rop_to_index[CIRRUS_ROP_NOP] = 2;
3215 rop_to_index[CIRRUS_ROP_SRC_AND_NOTDST] = 3;
3216 rop_to_index[CIRRUS_ROP_NOTDST] = 4;
3217 rop_to_index[CIRRUS_ROP_SRC] = 5;
3218 rop_to_index[CIRRUS_ROP_1] = 6;
3219 rop_to_index[CIRRUS_ROP_NOTSRC_AND_DST] = 7;
3220 rop_to_index[CIRRUS_ROP_SRC_XOR_DST] = 8;
3221 rop_to_index[CIRRUS_ROP_SRC_OR_DST] = 9;
3222 rop_to_index[CIRRUS_ROP_NOTSRC_OR_NOTDST] = 10;
3223 rop_to_index[CIRRUS_ROP_SRC_NOTXOR_DST] = 11;
3224 rop_to_index[CIRRUS_ROP_SRC_OR_NOTDST] = 12;
3225 rop_to_index[CIRRUS_ROP_NOTSRC] = 13;
3226 rop_to_index[CIRRUS_ROP_NOTSRC_OR_DST] = 14;
3227 rop_to_index[CIRRUS_ROP_NOTSRC_AND_NOTDST] = 15;
3228 s->device_id = device_id;
3229 if (is_pci)
3230 s->bustype = CIRRUS_BUSTYPE_PCI;
3231 else
3232 s->bustype = CIRRUS_BUSTYPE_ISA;
3233 }
3234
3235 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
3236
3237 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
3238 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
3239 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
3240 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
3241
3242 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
3243
3244 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
3245 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
3246 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
3247 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
3248
3249 s->vga_io_memory = cpu_register_io_memory(0, cirrus_vga_mem_read,
3250 cirrus_vga_mem_write, s);
3251 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
3252 s->vga_io_memory);
3253 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
3254
3255 /* I/O handler for LFB */
3256 s->cirrus_linear_io_addr =
3257 cpu_register_io_memory(0, cirrus_linear_read, cirrus_linear_write, s);
3258 s->cirrus_linear_write = cpu_get_io_memory_write(s->cirrus_linear_io_addr);
3259
3260 /* I/O handler for LFB */
3261 s->cirrus_linear_bitblt_io_addr =
3262 cpu_register_io_memory(0, cirrus_linear_bitblt_read,
3263 cirrus_linear_bitblt_write, s);
3264
3265 /* I/O handler for memory-mapped I/O */
3266 s->cirrus_mmio_io_addr =
3267 cpu_register_io_memory(0, cirrus_mmio_read, cirrus_mmio_write, s);
3268
3269 s->real_vram_size =
3270 (s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
3271
3272 /* XXX: s->vram_size must be a power of two */
3273 s->cirrus_addr_mask = s->real_vram_size - 1;
3274 s->linear_mmio_mask = s->real_vram_size - 256;
3275
3276 s->get_bpp = cirrus_get_bpp;
3277 s->get_offsets = cirrus_get_offsets;
3278 s->get_resolution = cirrus_get_resolution;
3279 s->cursor_invalidate = cirrus_cursor_invalidate;
3280 s->cursor_draw_line = cirrus_cursor_draw_line;
3281
3282 qemu_register_reset(cirrus_reset, s);
3283 cirrus_reset(s);
3284 register_savevm("cirrus_vga", 0, 2, cirrus_vga_save, cirrus_vga_load, s);
3285 }
3286
3287 /***************************************
3288 *
3289 * ISA bus support
3290 *
3291 ***************************************/
3292
3293 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
3294 ram_addr_t vga_ram_offset, int vga_ram_size)
3295 {
3296 CirrusVGAState *s;
3297
3298 s = qemu_mallocz(sizeof(CirrusVGAState));
3299
3300 vga_common_init((VGAState *)s,
3301 vga_ram_base, vga_ram_offset, vga_ram_size);
3302 cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
3303 s->ds = graphic_console_init(s->update, s->invalidate,
3304 s->screen_dump, s->text_update, s);
3305 /* XXX ISA-LFB support */
3306 }
3307
3308 /***************************************
3309 *
3310 * PCI bus support
3311 *
3312 ***************************************/
3313
3314 static void cirrus_pci_lfb_map(PCIDevice *d, int region_num,
3315 uint32_t addr, uint32_t size, int type)
3316 {
3317 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3318
3319 vga_dirty_log_stop((VGAState *)s);
3320
3321 /* XXX: add byte swapping apertures */
3322 cpu_register_physical_memory(addr, s->vram_size,
3323 s->cirrus_linear_io_addr);
3324 cpu_register_physical_memory(addr + 0x1000000, 0x400000,
3325 s->cirrus_linear_bitblt_io_addr);
3326
3327 s->map_addr = s->map_end = 0;
3328 s->lfb_addr = addr & TARGET_PAGE_MASK;
3329 s->lfb_end = ((addr + VGA_RAM_SIZE) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
3330 /* account for overflow */
3331 if (s->lfb_end < addr + VGA_RAM_SIZE)
3332 s->lfb_end = addr + VGA_RAM_SIZE;
3333
3334 vga_dirty_log_start((VGAState *)s);
3335 }
3336
3337 static void cirrus_pci_mmio_map(PCIDevice *d, int region_num,
3338 uint32_t addr, uint32_t size, int type)
3339 {
3340 CirrusVGAState *s = &((PCICirrusVGAState *)d)->cirrus_vga;
3341
3342 cpu_register_physical_memory(addr, CIRRUS_PNPMMIO_SIZE,
3343 s->cirrus_mmio_io_addr);
3344 }
3345
3346 static void pci_cirrus_write_config(PCIDevice *d,
3347 uint32_t address, uint32_t val, int len)
3348 {
3349 PCICirrusVGAState *pvs = container_of(d, PCICirrusVGAState, dev);
3350 CirrusVGAState *s = &pvs->cirrus_vga;
3351
3352 vga_dirty_log_stop((VGAState *)s);
3353
3354 pci_default_write_config(d, address, val, len);
3355 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
3356 s->map_addr = 0;
3357 cirrus_update_memory_access(s);
3358
3359 vga_dirty_log_start((VGAState *)s);
3360 }
3361
3362 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3363 ram_addr_t vga_ram_offset, int vga_ram_size)
3364 {
3365 PCICirrusVGAState *d;
3366 uint8_t *pci_conf;
3367 CirrusVGAState *s;
3368 int device_id;
3369
3370 device_id = CIRRUS_ID_CLGD5446;
3371
3372 /* setup PCI configuration registers */
3373 d = (PCICirrusVGAState *)pci_register_device(bus, "Cirrus VGA",
3374 sizeof(PCICirrusVGAState),
3375 -1, NULL, pci_cirrus_write_config);
3376 pci_conf = d->dev.config;
3377 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3378 pci_config_set_device_id(pci_conf, device_id);
3379 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3380 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3381 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3382
3383 /* setup VGA */
3384 s = &d->cirrus_vga;
3385 vga_common_init((VGAState *)s,
3386 vga_ram_base, vga_ram_offset, vga_ram_size);
3387 cirrus_init_common(s, device_id, 1);
3388
3389 s->ds = graphic_console_init(s->update, s->invalidate,
3390 s->screen_dump, s->text_update, s);
3391
3392 s->pci_dev = (PCIDevice *)d;
3393
3394 /* setup memory space */
3395 /* memory #0 LFB */
3396 /* memory #1 memory-mapped I/O */
3397 /* XXX: s->vram_size must be a power of two */
3398 pci_register_io_region((PCIDevice *)d, 0, 0x2000000,
3399 PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
3400 if (device_id == CIRRUS_ID_CLGD5446) {
3401 pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
3402 PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
3403 }
3404 /* XXX: ROM BIOS */
3405 }