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DisplayAllocator interface (Stefano Stabellini)
[sniper_test.git] / hw / sun4m.c
blob681d9736e0fb4e90508b076ad9373f99a7a5f3f5
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, args...) \
72 do { printf("CPUIRQ: " fmt , ##args); } while (0)
73 #else
74 #define DPRINTF(fmt, args...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 // Control plane, 8-bit and 24-bit planes
87 #define TCX_SIZE (9 * 1024 * 1024)
88
89 #define MAX_CPUS 16
90 #define MAX_PILS 16
91
92 #define ESCC_CLOCK 4915200
93
94 struct sun4m_hwdef {
95 target_phys_addr_t iommu_base, slavio_base;
96 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
97 target_phys_addr_t serial_base, fd_base;
98 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
99 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
100 target_phys_addr_t ecc_base;
101 uint32_t ecc_version;
102 long vram_size, nvram_size;
103 // IRQ numbers are not PIL ones, but master interrupt controller
104 // register bit numbers
105 int esp_irq, le_irq, clock_irq, clock1_irq;
106 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
107 uint8_t nvram_machine_id;
108 uint16_t machine_id;
109 uint32_t iommu_version;
110 uint32_t intbit_to_level[32];
111 uint64_t max_mem;
112 const char * const default_cpu_model;
113 };
114
115 #define MAX_IOUNITS 5
116
117 struct sun4d_hwdef {
118 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
119 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
120 target_phys_addr_t serial_base;
121 target_phys_addr_t espdma_base, esp_base;
122 target_phys_addr_t ledma_base, le_base;
123 target_phys_addr_t tcx_base;
124 target_phys_addr_t sbi_base;
125 unsigned long vram_size, nvram_size;
126 // IRQ numbers are not PIL ones, but SBI register bit numbers
127 int esp_irq, le_irq, clock_irq, clock1_irq;
128 int ser_irq, ms_kb_irq, me_irq;
129 uint8_t nvram_machine_id;
130 uint16_t machine_id;
131 uint32_t iounit_version;
132 uint64_t max_mem;
133 const char * const default_cpu_model;
134 };
135
136 struct sun4c_hwdef {
137 target_phys_addr_t iommu_base, slavio_base;
138 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
139 target_phys_addr_t serial_base, fd_base;
140 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
141 target_phys_addr_t tcx_base, aux1_base;
142 long vram_size, nvram_size;
143 // IRQ numbers are not PIL ones, but master interrupt controller
144 // register bit numbers
145 int esp_irq, le_irq, clock_irq, clock1_irq;
146 int ser_irq, ms_kb_irq, fd_irq, me_irq;
147 uint8_t nvram_machine_id;
148 uint16_t machine_id;
149 uint32_t iommu_version;
150 uint32_t intbit_to_level[32];
151 uint64_t max_mem;
152 const char * const default_cpu_model;
153 };
154
155 int DMA_get_channel_mode (int nchan)
156 {
157 return 0;
158 }
159 int DMA_read_memory (int nchan, void *buf, int pos, int size)
160 {
161 return 0;
162 }
163 int DMA_write_memory (int nchan, void *buf, int pos, int size)
164 {
165 return 0;
166 }
167 void DMA_hold_DREQ (int nchan) {}
168 void DMA_release_DREQ (int nchan) {}
169 void DMA_schedule(int nchan) {}
170 void DMA_init (int high_page_enable) {}
171 void DMA_register_channel (int nchan,
172 DMA_transfer_handler transfer_handler,
173 void *opaque)
174 {
175 }
176
177 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
178 {
179 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
180 return 0;
181 }
182
183 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
184 const char *boot_devices, ram_addr_t RAM_size,
185 uint32_t kernel_size,
186 int width, int height, int depth,
187 int nvram_machine_id, const char *arch)
188 {
189 unsigned int i;
190 uint32_t start, end;
191 uint8_t image[0x1ff0];
192 struct OpenBIOS_nvpart_v1 *part_header;
193
194 memset(image, '\0', sizeof(image));
195
196 start = 0;
197
198 // OpenBIOS nvram variables
199 // Variable partition
200 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
201 part_header->signature = OPENBIOS_PART_SYSTEM;
202 pstrcpy(part_header->name, sizeof(part_header->name), "system");
203
204 end = start + sizeof(struct OpenBIOS_nvpart_v1);
205 for (i = 0; i < nb_prom_envs; i++)
206 end = OpenBIOS_set_var(image, end, prom_envs[i]);
207
208 // End marker
209 image[end++] = '\0';
210
211 end = start + ((end - start + 15) & ~15);
212 OpenBIOS_finish_partition(part_header, end - start);
213
214 // free partition
215 start = end;
216 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
217 part_header->signature = OPENBIOS_PART_FREE;
218 pstrcpy(part_header->name, sizeof(part_header->name), "free");
219
220 end = 0x1fd0;
221 OpenBIOS_finish_partition(part_header, end - start);
222
223 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
224 nvram_machine_id);
225
226 for (i = 0; i < sizeof(image); i++)
227 m48t59_write(nvram, i, image[i]);
228 }
229
230 static void *slavio_intctl;
231
232 void pic_info(Monitor *mon)
233 {
234 if (slavio_intctl)
235 slavio_pic_info(mon, slavio_intctl);
236 }
237
238 void irq_info(Monitor *mon)
239 {
240 if (slavio_intctl)
241 slavio_irq_info(mon, slavio_intctl);
242 }
243
244 void cpu_check_irqs(CPUState *env)
245 {
246 if (env->pil_in && (env->interrupt_index == 0 ||
247 (env->interrupt_index & ~15) == TT_EXTINT)) {
248 unsigned int i;
249
250 for (i = 15; i > 0; i--) {
251 if (env->pil_in & (1 << i)) {
252 int old_interrupt = env->interrupt_index;
253
254 env->interrupt_index = TT_EXTINT | i;
255 if (old_interrupt != env->interrupt_index) {
256 DPRINTF("Set CPU IRQ %d\n", i);
257 cpu_interrupt(env, CPU_INTERRUPT_HARD);
258 }
259 break;
260 }
261 }
262 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
263 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
264 env->interrupt_index = 0;
265 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
266 }
267 }
268
269 static void cpu_set_irq(void *opaque, int irq, int level)
270 {
271 CPUState *env = opaque;
272
273 if (level) {
274 DPRINTF("Raise CPU IRQ %d\n", irq);
275 env->halted = 0;
276 env->pil_in |= 1 << irq;
277 cpu_check_irqs(env);
278 } else {
279 DPRINTF("Lower CPU IRQ %d\n", irq);
280 env->pil_in &= ~(1 << irq);
281 cpu_check_irqs(env);
282 }
283 }
284
285 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
286 {
287 }
288
289 static void *slavio_misc;
290
291 void qemu_system_powerdown(void)
292 {
293 slavio_set_power_fail(slavio_misc, 1);
294 }
295
296 static void main_cpu_reset(void *opaque)
297 {
298 CPUState *env = opaque;
299
300 cpu_reset(env);
301 env->halted = 0;
302 }
303
304 static void secondary_cpu_reset(void *opaque)
305 {
306 CPUState *env = opaque;
307
308 cpu_reset(env);
309 env->halted = 1;
310 }
311
312 static void cpu_halt_signal(void *opaque, int irq, int level)
313 {
314 if (level && cpu_single_env)
315 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
316 }
317
318 static unsigned long sun4m_load_kernel(const char *kernel_filename,
319 const char *initrd_filename,
320 ram_addr_t RAM_size)
321 {
322 int linux_boot;
323 unsigned int i;
324 long initrd_size, kernel_size;
325
326 linux_boot = (kernel_filename != NULL);
327
328 kernel_size = 0;
329 if (linux_boot) {
330 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
331 NULL);
332 if (kernel_size < 0)
333 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR);
335 if (kernel_size < 0)
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
359 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
360 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
361 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
362 break;
363 }
364 }
365 }
366 }
367 return kernel_size;
368 }
369
370 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
371 const char *boot_device,
372 const char *kernel_filename,
373 const char *kernel_cmdline,
374 const char *initrd_filename, const char *cpu_model)
375
376 {
377 CPUState *env, *envs[MAX_CPUS];
378 unsigned int i;
379 void *iommu, *espdma, *ledma, *main_esp, *nvram;
380 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
381 *espdma_irq, *ledma_irq;
382 qemu_irq *esp_reset, *le_reset;
383 qemu_irq *fdc_tc;
384 qemu_irq *cpu_halt;
385 ram_addr_t ram_offset, prom_offset, tcx_offset, idreg_offset;
386 unsigned long kernel_size;
387 int ret;
388 char buf[1024];
389 BlockDriverState *fd[MAX_FD];
390 int drive_index;
391 void *fw_cfg;
392
393 /* init CPUs */
394 if (!cpu_model)
395 cpu_model = hwdef->default_cpu_model;
396
397 for(i = 0; i < smp_cpus; i++) {
398 env = cpu_init(cpu_model);
399 if (!env) {
400 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
401 exit(1);
402 }
403 cpu_sparc_set_id(env, i);
404 envs[i] = env;
405 if (i == 0) {
406 qemu_register_reset(main_cpu_reset, env);
407 } else {
408 qemu_register_reset(secondary_cpu_reset, env);
409 env->halted = 1;
410 }
411 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
412 env->prom_addr = hwdef->slavio_base;
413 }
414
415 for (i = smp_cpus; i < MAX_CPUS; i++)
416 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
417
418
419 /* allocate RAM */
420 if ((uint64_t)RAM_size > hwdef->max_mem) {
421 fprintf(stderr,
422 "qemu: Too much memory for this machine: %d, maximum %d\n",
423 (unsigned int)(RAM_size / (1024 * 1024)),
424 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
425 exit(1);
426 }
427 ram_offset = qemu_ram_alloc(RAM_size);
428 cpu_register_physical_memory(0, RAM_size, ram_offset);
429
430 /* load boot prom */
431 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
432 cpu_register_physical_memory(hwdef->slavio_base,
433 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
434 TARGET_PAGE_MASK,
435 prom_offset | IO_MEM_ROM);
436
437 if (bios_name == NULL)
438 bios_name = PROM_FILENAME;
439 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
440 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
441 if (ret < 0 || ret > PROM_SIZE_MAX)
442 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
443 if (ret < 0 || ret > PROM_SIZE_MAX) {
444 fprintf(stderr, "qemu: could not load prom '%s'\n",
445 buf);
446 exit(1);
447 }
448
449 /* set up devices */
450 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
451 hwdef->intctl_base + 0x10000ULL,
452 &hwdef->intbit_to_level[0],
453 &slavio_irq, &slavio_cpu_irq,
454 cpu_irqs,
455 hwdef->clock_irq);
456
457 if (hwdef->idreg_base) {
458 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
459
460 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
461 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
462 idreg_offset | IO_MEM_ROM);
463 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
464 sizeof(idreg_data));
465 }
466
467 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
468 slavio_irq[hwdef->me_irq]);
469
470 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
471 iommu, &espdma_irq, &esp_reset);
472
473 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
474 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
475 &le_reset);
476
477 if (graphic_depth != 8 && graphic_depth != 24) {
478 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
479 exit (1);
480 }
481 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
482 tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
483 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
484
485 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
486
487 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
488 hwdef->nvram_size, 8);
489
490 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
491 slavio_cpu_irq, smp_cpus);
492
493 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
494 nographic, ESCC_CLOCK, 1);
495 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
496 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
497 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
498 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
499
500 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
501 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
502 hwdef->aux1_base, hwdef->aux2_base,
503 slavio_irq[hwdef->me_irq], cpu_halt[0],
504 &fdc_tc);
505
506 if (hwdef->fd_base) {
507 /* there is zero or one floppy drive */
508 memset(fd, 0, sizeof(fd));
509 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
510 if (drive_index != -1)
511 fd[0] = drives_table[drive_index].bdrv;
512
513 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
514 fdc_tc);
515 }
516
517 if (drive_get_max_bus(IF_SCSI) > 0) {
518 fprintf(stderr, "qemu: too many SCSI bus\n");
519 exit(1);
520 }
521
522 main_esp = esp_init(hwdef->esp_base, 2,
523 espdma_memory_read, espdma_memory_write,
524 espdma, *espdma_irq, esp_reset);
525
526 for (i = 0; i < ESP_MAX_DEVS; i++) {
527 drive_index = drive_get_index(IF_SCSI, 0, i);
528 if (drive_index == -1)
529 continue;
530 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
531 }
532
533 if (hwdef->cs_base)
534 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
535
536 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
537 RAM_size);
538
539 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
540 boot_device, RAM_size, kernel_size, graphic_width,
541 graphic_height, graphic_depth, hwdef->nvram_machine_id,
542 "Sun4m");
543
544 if (hwdef->ecc_base)
545 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
546 hwdef->ecc_version);
547
548 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
549 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
550 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
551 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
552 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
553 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
554 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
555 if (kernel_cmdline) {
556 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
557 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
558 } else {
559 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
560 }
561 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
562 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
563 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
564 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
565 }
566
567 enum {
568 ss2_id = 0,
569 ss5_id = 32,
570 vger_id,
571 lx_id,
572 ss4_id,
573 scls_id,
574 sbook_id,
575 ss10_id = 64,
576 ss20_id,
577 ss600mp_id,
578 ss1000_id = 96,
579 ss2000_id,
580 };
581
582 static const struct sun4m_hwdef sun4m_hwdefs[] = {
583 /* SS-5 */
584 {
585 .iommu_base = 0x10000000,
586 .tcx_base = 0x50000000,
587 .cs_base = 0x6c000000,
588 .slavio_base = 0x70000000,
589 .ms_kb_base = 0x71000000,
590 .serial_base = 0x71100000,
591 .nvram_base = 0x71200000,
592 .fd_base = 0x71400000,
593 .counter_base = 0x71d00000,
594 .intctl_base = 0x71e00000,
595 .idreg_base = 0x78000000,
596 .dma_base = 0x78400000,
597 .esp_base = 0x78800000,
598 .le_base = 0x78c00000,
599 .apc_base = 0x6a000000,
600 .aux1_base = 0x71900000,
601 .aux2_base = 0x71910000,
602 .vram_size = 0x00100000,
603 .nvram_size = 0x2000,
604 .esp_irq = 18,
605 .le_irq = 16,
606 .clock_irq = 7,
607 .clock1_irq = 19,
608 .ms_kb_irq = 14,
609 .ser_irq = 15,
610 .fd_irq = 22,
611 .me_irq = 30,
612 .cs_irq = 5,
613 .nvram_machine_id = 0x80,
614 .machine_id = ss5_id,
615 .iommu_version = 0x05000000,
616 .intbit_to_level = {
617 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
618 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
619 },
620 .max_mem = 0x10000000,
621 .default_cpu_model = "Fujitsu MB86904",
622 },
623 /* SS-10 */
624 {
625 .iommu_base = 0xfe0000000ULL,
626 .tcx_base = 0xe20000000ULL,
627 .slavio_base = 0xff0000000ULL,
628 .ms_kb_base = 0xff1000000ULL,
629 .serial_base = 0xff1100000ULL,
630 .nvram_base = 0xff1200000ULL,
631 .fd_base = 0xff1700000ULL,
632 .counter_base = 0xff1300000ULL,
633 .intctl_base = 0xff1400000ULL,
634 .idreg_base = 0xef0000000ULL,
635 .dma_base = 0xef0400000ULL,
636 .esp_base = 0xef0800000ULL,
637 .le_base = 0xef0c00000ULL,
638 .apc_base = 0xefa000000ULL, // XXX should not exist
639 .aux1_base = 0xff1800000ULL,
640 .aux2_base = 0xff1a01000ULL,
641 .ecc_base = 0xf00000000ULL,
642 .ecc_version = 0x10000000, // version 0, implementation 1
643 .vram_size = 0x00100000,
644 .nvram_size = 0x2000,
645 .esp_irq = 18,
646 .le_irq = 16,
647 .clock_irq = 7,
648 .clock1_irq = 19,
649 .ms_kb_irq = 14,
650 .ser_irq = 15,
651 .fd_irq = 22,
652 .me_irq = 30,
653 .ecc_irq = 28,
654 .nvram_machine_id = 0x72,
655 .machine_id = ss10_id,
656 .iommu_version = 0x03000000,
657 .intbit_to_level = {
658 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
659 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
660 },
661 .max_mem = 0xf00000000ULL,
662 .default_cpu_model = "TI SuperSparc II",
663 },
664 /* SS-600MP */
665 {
666 .iommu_base = 0xfe0000000ULL,
667 .tcx_base = 0xe20000000ULL,
668 .slavio_base = 0xff0000000ULL,
669 .ms_kb_base = 0xff1000000ULL,
670 .serial_base = 0xff1100000ULL,
671 .nvram_base = 0xff1200000ULL,
672 .counter_base = 0xff1300000ULL,
673 .intctl_base = 0xff1400000ULL,
674 .dma_base = 0xef0081000ULL,
675 .esp_base = 0xef0080000ULL,
676 .le_base = 0xef0060000ULL,
677 .apc_base = 0xefa000000ULL, // XXX should not exist
678 .aux1_base = 0xff1800000ULL,
679 .aux2_base = 0xff1a01000ULL, // XXX should not exist
680 .ecc_base = 0xf00000000ULL,
681 .ecc_version = 0x00000000, // version 0, implementation 0
682 .vram_size = 0x00100000,
683 .nvram_size = 0x2000,
684 .esp_irq = 18,
685 .le_irq = 16,
686 .clock_irq = 7,
687 .clock1_irq = 19,
688 .ms_kb_irq = 14,
689 .ser_irq = 15,
690 .fd_irq = 22,
691 .me_irq = 30,
692 .ecc_irq = 28,
693 .nvram_machine_id = 0x71,
694 .machine_id = ss600mp_id,
695 .iommu_version = 0x01000000,
696 .intbit_to_level = {
697 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
698 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
699 },
700 .max_mem = 0xf00000000ULL,
701 .default_cpu_model = "TI SuperSparc II",
702 },
703 /* SS-20 */
704 {
705 .iommu_base = 0xfe0000000ULL,
706 .tcx_base = 0xe20000000ULL,
707 .slavio_base = 0xff0000000ULL,
708 .ms_kb_base = 0xff1000000ULL,
709 .serial_base = 0xff1100000ULL,
710 .nvram_base = 0xff1200000ULL,
711 .fd_base = 0xff1700000ULL,
712 .counter_base = 0xff1300000ULL,
713 .intctl_base = 0xff1400000ULL,
714 .idreg_base = 0xef0000000ULL,
715 .dma_base = 0xef0400000ULL,
716 .esp_base = 0xef0800000ULL,
717 .le_base = 0xef0c00000ULL,
718 .apc_base = 0xefa000000ULL, // XXX should not exist
719 .aux1_base = 0xff1800000ULL,
720 .aux2_base = 0xff1a01000ULL,
721 .ecc_base = 0xf00000000ULL,
722 .ecc_version = 0x20000000, // version 0, implementation 2
723 .vram_size = 0x00100000,
724 .nvram_size = 0x2000,
725 .esp_irq = 18,
726 .le_irq = 16,
727 .clock_irq = 7,
728 .clock1_irq = 19,
729 .ms_kb_irq = 14,
730 .ser_irq = 15,
731 .fd_irq = 22,
732 .me_irq = 30,
733 .ecc_irq = 28,
734 .nvram_machine_id = 0x72,
735 .machine_id = ss20_id,
736 .iommu_version = 0x13000000,
737 .intbit_to_level = {
738 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
739 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
740 },
741 .max_mem = 0xf00000000ULL,
742 .default_cpu_model = "TI SuperSparc II",
743 },
744 /* Voyager */
745 {
746 .iommu_base = 0x10000000,
747 .tcx_base = 0x50000000,
748 .slavio_base = 0x70000000,
749 .ms_kb_base = 0x71000000,
750 .serial_base = 0x71100000,
751 .nvram_base = 0x71200000,
752 .fd_base = 0x71400000,
753 .counter_base = 0x71d00000,
754 .intctl_base = 0x71e00000,
755 .idreg_base = 0x78000000,
756 .dma_base = 0x78400000,
757 .esp_base = 0x78800000,
758 .le_base = 0x78c00000,
759 .apc_base = 0x71300000, // pmc
760 .aux1_base = 0x71900000,
761 .aux2_base = 0x71910000,
762 .vram_size = 0x00100000,
763 .nvram_size = 0x2000,
764 .esp_irq = 18,
765 .le_irq = 16,
766 .clock_irq = 7,
767 .clock1_irq = 19,
768 .ms_kb_irq = 14,
769 .ser_irq = 15,
770 .fd_irq = 22,
771 .me_irq = 30,
772 .nvram_machine_id = 0x80,
773 .machine_id = vger_id,
774 .iommu_version = 0x05000000,
775 .intbit_to_level = {
776 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
777 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
778 },
779 .max_mem = 0x10000000,
780 .default_cpu_model = "Fujitsu MB86904",
781 },
782 /* LX */
783 {
784 .iommu_base = 0x10000000,
785 .tcx_base = 0x50000000,
786 .slavio_base = 0x70000000,
787 .ms_kb_base = 0x71000000,
788 .serial_base = 0x71100000,
789 .nvram_base = 0x71200000,
790 .fd_base = 0x71400000,
791 .counter_base = 0x71d00000,
792 .intctl_base = 0x71e00000,
793 .idreg_base = 0x78000000,
794 .dma_base = 0x78400000,
795 .esp_base = 0x78800000,
796 .le_base = 0x78c00000,
797 .aux1_base = 0x71900000,
798 .aux2_base = 0x71910000,
799 .vram_size = 0x00100000,
800 .nvram_size = 0x2000,
801 .esp_irq = 18,
802 .le_irq = 16,
803 .clock_irq = 7,
804 .clock1_irq = 19,
805 .ms_kb_irq = 14,
806 .ser_irq = 15,
807 .fd_irq = 22,
808 .me_irq = 30,
809 .nvram_machine_id = 0x80,
810 .machine_id = lx_id,
811 .iommu_version = 0x04000000,
812 .intbit_to_level = {
813 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
814 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
815 },
816 .max_mem = 0x10000000,
817 .default_cpu_model = "TI MicroSparc I",
818 },
819 /* SS-4 */
820 {
821 .iommu_base = 0x10000000,
822 .tcx_base = 0x50000000,
823 .cs_base = 0x6c000000,
824 .slavio_base = 0x70000000,
825 .ms_kb_base = 0x71000000,
826 .serial_base = 0x71100000,
827 .nvram_base = 0x71200000,
828 .fd_base = 0x71400000,
829 .counter_base = 0x71d00000,
830 .intctl_base = 0x71e00000,
831 .idreg_base = 0x78000000,
832 .dma_base = 0x78400000,
833 .esp_base = 0x78800000,
834 .le_base = 0x78c00000,
835 .apc_base = 0x6a000000,
836 .aux1_base = 0x71900000,
837 .aux2_base = 0x71910000,
838 .vram_size = 0x00100000,
839 .nvram_size = 0x2000,
840 .esp_irq = 18,
841 .le_irq = 16,
842 .clock_irq = 7,
843 .clock1_irq = 19,
844 .ms_kb_irq = 14,
845 .ser_irq = 15,
846 .fd_irq = 22,
847 .me_irq = 30,
848 .cs_irq = 5,
849 .nvram_machine_id = 0x80,
850 .machine_id = ss4_id,
851 .iommu_version = 0x05000000,
852 .intbit_to_level = {
853 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
854 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
855 },
856 .max_mem = 0x10000000,
857 .default_cpu_model = "Fujitsu MB86904",
858 },
859 /* SPARCClassic */
860 {
861 .iommu_base = 0x10000000,
862 .tcx_base = 0x50000000,
863 .slavio_base = 0x70000000,
864 .ms_kb_base = 0x71000000,
865 .serial_base = 0x71100000,
866 .nvram_base = 0x71200000,
867 .fd_base = 0x71400000,
868 .counter_base = 0x71d00000,
869 .intctl_base = 0x71e00000,
870 .idreg_base = 0x78000000,
871 .dma_base = 0x78400000,
872 .esp_base = 0x78800000,
873 .le_base = 0x78c00000,
874 .apc_base = 0x6a000000,
875 .aux1_base = 0x71900000,
876 .aux2_base = 0x71910000,
877 .vram_size = 0x00100000,
878 .nvram_size = 0x2000,
879 .esp_irq = 18,
880 .le_irq = 16,
881 .clock_irq = 7,
882 .clock1_irq = 19,
883 .ms_kb_irq = 14,
884 .ser_irq = 15,
885 .fd_irq = 22,
886 .me_irq = 30,
887 .nvram_machine_id = 0x80,
888 .machine_id = scls_id,
889 .iommu_version = 0x05000000,
890 .intbit_to_level = {
891 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
892 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
893 },
894 .max_mem = 0x10000000,
895 .default_cpu_model = "TI MicroSparc I",
896 },
897 /* SPARCbook */
898 {
899 .iommu_base = 0x10000000,
900 .tcx_base = 0x50000000, // XXX
901 .slavio_base = 0x70000000,
902 .ms_kb_base = 0x71000000,
903 .serial_base = 0x71100000,
904 .nvram_base = 0x71200000,
905 .fd_base = 0x71400000,
906 .counter_base = 0x71d00000,
907 .intctl_base = 0x71e00000,
908 .idreg_base = 0x78000000,
909 .dma_base = 0x78400000,
910 .esp_base = 0x78800000,
911 .le_base = 0x78c00000,
912 .apc_base = 0x6a000000,
913 .aux1_base = 0x71900000,
914 .aux2_base = 0x71910000,
915 .vram_size = 0x00100000,
916 .nvram_size = 0x2000,
917 .esp_irq = 18,
918 .le_irq = 16,
919 .clock_irq = 7,
920 .clock1_irq = 19,
921 .ms_kb_irq = 14,
922 .ser_irq = 15,
923 .fd_irq = 22,
924 .me_irq = 30,
925 .nvram_machine_id = 0x80,
926 .machine_id = sbook_id,
927 .iommu_version = 0x05000000,
928 .intbit_to_level = {
929 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
930 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
931 },
932 .max_mem = 0x10000000,
933 .default_cpu_model = "TI MicroSparc I",
934 },
935 };
936
937 /* SPARCstation 5 hardware initialisation */
938 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
939 const char *boot_device,
940 const char *kernel_filename, const char *kernel_cmdline,
941 const char *initrd_filename, const char *cpu_model)
942 {
943 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
944 kernel_cmdline, initrd_filename, cpu_model);
945 }
946
947 /* SPARCstation 10 hardware initialisation */
948 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
949 const char *boot_device,
950 const char *kernel_filename, const char *kernel_cmdline,
951 const char *initrd_filename, const char *cpu_model)
952 {
953 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
954 kernel_cmdline, initrd_filename, cpu_model);
955 }
956
957 /* SPARCserver 600MP hardware initialisation */
958 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
959 const char *boot_device,
960 const char *kernel_filename,
961 const char *kernel_cmdline,
962 const char *initrd_filename, const char *cpu_model)
963 {
964 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
965 kernel_cmdline, initrd_filename, cpu_model);
966 }
967
968 /* SPARCstation 20 hardware initialisation */
969 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
970 const char *boot_device,
971 const char *kernel_filename, const char *kernel_cmdline,
972 const char *initrd_filename, const char *cpu_model)
973 {
974 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
975 kernel_cmdline, initrd_filename, cpu_model);
976 }
977
978 /* SPARCstation Voyager hardware initialisation */
979 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
980 const char *boot_device,
981 const char *kernel_filename, const char *kernel_cmdline,
982 const char *initrd_filename, const char *cpu_model)
983 {
984 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
985 kernel_cmdline, initrd_filename, cpu_model);
986 }
987
988 /* SPARCstation LX hardware initialisation */
989 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
990 const char *boot_device,
991 const char *kernel_filename, const char *kernel_cmdline,
992 const char *initrd_filename, const char *cpu_model)
993 {
994 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
995 kernel_cmdline, initrd_filename, cpu_model);
996 }
997
998 /* SPARCstation 4 hardware initialisation */
999 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1000 const char *boot_device,
1001 const char *kernel_filename, const char *kernel_cmdline,
1002 const char *initrd_filename, const char *cpu_model)
1003 {
1004 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1005 kernel_cmdline, initrd_filename, cpu_model);
1006 }
1007
1008 /* SPARCClassic hardware initialisation */
1009 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1010 const char *boot_device,
1011 const char *kernel_filename, const char *kernel_cmdline,
1012 const char *initrd_filename, const char *cpu_model)
1013 {
1014 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1015 kernel_cmdline, initrd_filename, cpu_model);
1016 }
1017
1018 /* SPARCbook hardware initialisation */
1019 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1020 const char *boot_device,
1021 const char *kernel_filename, const char *kernel_cmdline,
1022 const char *initrd_filename, const char *cpu_model)
1023 {
1024 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1025 kernel_cmdline, initrd_filename, cpu_model);
1026 }
1027
1028 QEMUMachine ss5_machine = {
1029 .name = "SS-5",
1030 .desc = "Sun4m platform, SPARCstation 5",
1031 .init = ss5_init,
1032 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1033 .nodisk_ok = 1,
1034 .use_scsi = 1,
1035 };
1036
1037 QEMUMachine ss10_machine = {
1038 .name = "SS-10",
1039 .desc = "Sun4m platform, SPARCstation 10",
1040 .init = ss10_init,
1041 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1042 .nodisk_ok = 1,
1043 .use_scsi = 1,
1044 .max_cpus = 4,
1045 };
1046
1047 QEMUMachine ss600mp_machine = {
1048 .name = "SS-600MP",
1049 .desc = "Sun4m platform, SPARCserver 600MP",
1050 .init = ss600mp_init,
1051 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1052 .nodisk_ok = 1,
1053 .use_scsi = 1,
1054 .max_cpus = 4,
1055 };
1056
1057 QEMUMachine ss20_machine = {
1058 .name = "SS-20",
1059 .desc = "Sun4m platform, SPARCstation 20",
1060 .init = ss20_init,
1061 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1062 .nodisk_ok = 1,
1063 .use_scsi = 1,
1064 .max_cpus = 4,
1065 };
1066
1067 QEMUMachine voyager_machine = {
1068 .name = "Voyager",
1069 .desc = "Sun4m platform, SPARCstation Voyager",
1070 .init = vger_init,
1071 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1072 .nodisk_ok = 1,
1073 .use_scsi = 1,
1074 };
1075
1076 QEMUMachine ss_lx_machine = {
1077 .name = "LX",
1078 .desc = "Sun4m platform, SPARCstation LX",
1079 .init = ss_lx_init,
1080 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1081 .nodisk_ok = 1,
1082 .use_scsi = 1,
1083 };
1084
1085 QEMUMachine ss4_machine = {
1086 .name = "SS-4",
1087 .desc = "Sun4m platform, SPARCstation 4",
1088 .init = ss4_init,
1089 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1090 .nodisk_ok = 1,
1091 .use_scsi = 1,
1092 };
1093
1094 QEMUMachine scls_machine = {
1095 .name = "SPARCClassic",
1096 .desc = "Sun4m platform, SPARCClassic",
1097 .init = scls_init,
1098 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1099 .nodisk_ok = 1,
1100 .use_scsi = 1,
1101 };
1102
1103 QEMUMachine sbook_machine = {
1104 .name = "SPARCbook",
1105 .desc = "Sun4m platform, SPARCbook",
1106 .init = sbook_init,
1107 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1108 .nodisk_ok = 1,
1109 .use_scsi = 1,
1110 };
1111
1112 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1113 /* SS-1000 */
1114 {
1115 .iounit_bases = {
1116 0xfe0200000ULL,
1117 0xfe1200000ULL,
1118 0xfe2200000ULL,
1119 0xfe3200000ULL,
1120 -1,
1121 },
1122 .tcx_base = 0x820000000ULL,
1123 .slavio_base = 0xf00000000ULL,
1124 .ms_kb_base = 0xf00240000ULL,
1125 .serial_base = 0xf00200000ULL,
1126 .nvram_base = 0xf00280000ULL,
1127 .counter_base = 0xf00300000ULL,
1128 .espdma_base = 0x800081000ULL,
1129 .esp_base = 0x800080000ULL,
1130 .ledma_base = 0x800040000ULL,
1131 .le_base = 0x800060000ULL,
1132 .sbi_base = 0xf02800000ULL,
1133 .vram_size = 0x00100000,
1134 .nvram_size = 0x2000,
1135 .esp_irq = 3,
1136 .le_irq = 4,
1137 .clock_irq = 14,
1138 .clock1_irq = 10,
1139 .ms_kb_irq = 12,
1140 .ser_irq = 12,
1141 .nvram_machine_id = 0x80,
1142 .machine_id = ss1000_id,
1143 .iounit_version = 0x03000000,
1144 .max_mem = 0xf00000000ULL,
1145 .default_cpu_model = "TI SuperSparc II",
1146 },
1147 /* SS-2000 */
1148 {
1149 .iounit_bases = {
1150 0xfe0200000ULL,
1151 0xfe1200000ULL,
1152 0xfe2200000ULL,
1153 0xfe3200000ULL,
1154 0xfe4200000ULL,
1155 },
1156 .tcx_base = 0x820000000ULL,
1157 .slavio_base = 0xf00000000ULL,
1158 .ms_kb_base = 0xf00240000ULL,
1159 .serial_base = 0xf00200000ULL,
1160 .nvram_base = 0xf00280000ULL,
1161 .counter_base = 0xf00300000ULL,
1162 .espdma_base = 0x800081000ULL,
1163 .esp_base = 0x800080000ULL,
1164 .ledma_base = 0x800040000ULL,
1165 .le_base = 0x800060000ULL,
1166 .sbi_base = 0xf02800000ULL,
1167 .vram_size = 0x00100000,
1168 .nvram_size = 0x2000,
1169 .esp_irq = 3,
1170 .le_irq = 4,
1171 .clock_irq = 14,
1172 .clock1_irq = 10,
1173 .ms_kb_irq = 12,
1174 .ser_irq = 12,
1175 .nvram_machine_id = 0x80,
1176 .machine_id = ss2000_id,
1177 .iounit_version = 0x03000000,
1178 .max_mem = 0xf00000000ULL,
1179 .default_cpu_model = "TI SuperSparc II",
1180 },
1181 };
1182
1183 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1184 const char *boot_device,
1185 const char *kernel_filename,
1186 const char *kernel_cmdline,
1187 const char *initrd_filename, const char *cpu_model)
1188 {
1189 CPUState *env, *envs[MAX_CPUS];
1190 unsigned int i;
1191 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1192 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1193 *espdma_irq, *ledma_irq;
1194 qemu_irq *esp_reset, *le_reset;
1195 ram_addr_t ram_offset, prom_offset, tcx_offset;
1196 unsigned long kernel_size;
1197 int ret;
1198 char buf[1024];
1199 int drive_index;
1200 void *fw_cfg;
1201
1202 /* init CPUs */
1203 if (!cpu_model)
1204 cpu_model = hwdef->default_cpu_model;
1205
1206 for (i = 0; i < smp_cpus; i++) {
1207 env = cpu_init(cpu_model);
1208 if (!env) {
1209 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1210 exit(1);
1211 }
1212 cpu_sparc_set_id(env, i);
1213 envs[i] = env;
1214 if (i == 0) {
1215 qemu_register_reset(main_cpu_reset, env);
1216 } else {
1217 qemu_register_reset(secondary_cpu_reset, env);
1218 env->halted = 1;
1219 }
1220 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1221 env->prom_addr = hwdef->slavio_base;
1222 }
1223
1224 for (i = smp_cpus; i < MAX_CPUS; i++)
1225 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1226
1227 /* allocate RAM */
1228 if ((uint64_t)RAM_size > hwdef->max_mem) {
1229 fprintf(stderr,
1230 "qemu: Too much memory for this machine: %d, maximum %d\n",
1231 (unsigned int)(RAM_size / (1024 * 1024)),
1232 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1233 exit(1);
1234 }
1235 ram_offset = qemu_ram_alloc(RAM_size);
1236 cpu_register_physical_memory(0, RAM_size, ram_offset);
1237
1238 /* load boot prom */
1239 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1240 cpu_register_physical_memory(hwdef->slavio_base,
1241 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1242 TARGET_PAGE_MASK,
1243 prom_offset | IO_MEM_ROM);
1244
1245 if (bios_name == NULL)
1246 bios_name = PROM_FILENAME;
1247 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1248 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1249 if (ret < 0 || ret > PROM_SIZE_MAX)
1250 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1251 if (ret < 0 || ret > PROM_SIZE_MAX) {
1252 fprintf(stderr, "qemu: could not load prom '%s'\n",
1253 buf);
1254 exit(1);
1255 }
1256
1257 /* set up devices */
1258 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1259
1260 for (i = 0; i < MAX_IOUNITS; i++)
1261 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1262 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1263 hwdef->iounit_version,
1264 sbi_irq[hwdef->me_irq]);
1265
1266 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1267 iounits[0], &espdma_irq, &esp_reset);
1268
1269 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1270 iounits[0], &ledma_irq, &le_reset);
1271
1272 if (graphic_depth != 8 && graphic_depth != 24) {
1273 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1274 exit (1);
1275 }
1276 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1277 tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1278 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1279
1280 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1281
1282 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1283 hwdef->nvram_size, 8);
1284
1285 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1286 sbi_cpu_irq, smp_cpus);
1287
1288 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1289 nographic, ESCC_CLOCK, 1);
1290 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1291 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1292 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1293 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1294
1295 if (drive_get_max_bus(IF_SCSI) > 0) {
1296 fprintf(stderr, "qemu: too many SCSI bus\n");
1297 exit(1);
1298 }
1299
1300 main_esp = esp_init(hwdef->esp_base, 2,
1301 espdma_memory_read, espdma_memory_write,
1302 espdma, *espdma_irq, esp_reset);
1303
1304 for (i = 0; i < ESP_MAX_DEVS; i++) {
1305 drive_index = drive_get_index(IF_SCSI, 0, i);
1306 if (drive_index == -1)
1307 continue;
1308 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1309 }
1310
1311 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1312 RAM_size);
1313
1314 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1315 boot_device, RAM_size, kernel_size, graphic_width,
1316 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1317 "Sun4d");
1318
1319 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1320 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1321 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1322 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1323 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1324 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1326 if (kernel_cmdline) {
1327 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1328 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1329 } else {
1330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1331 }
1332 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1333 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1334 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1335 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1336 }
1337
1338 /* SPARCserver 1000 hardware initialisation */
1339 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1340 const char *boot_device,
1341 const char *kernel_filename, const char *kernel_cmdline,
1342 const char *initrd_filename, const char *cpu_model)
1343 {
1344 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1345 kernel_cmdline, initrd_filename, cpu_model);
1346 }
1347
1348 /* SPARCcenter 2000 hardware initialisation */
1349 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1350 const char *boot_device,
1351 const char *kernel_filename, const char *kernel_cmdline,
1352 const char *initrd_filename, const char *cpu_model)
1353 {
1354 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1355 kernel_cmdline, initrd_filename, cpu_model);
1356 }
1357
1358 QEMUMachine ss1000_machine = {
1359 .name = "SS-1000",
1360 .desc = "Sun4d platform, SPARCserver 1000",
1361 .init = ss1000_init,
1362 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1363 .nodisk_ok = 1,
1364 .use_scsi = 1,
1365 .max_cpus = 8,
1366 };
1367
1368 QEMUMachine ss2000_machine = {
1369 .name = "SS-2000",
1370 .desc = "Sun4d platform, SPARCcenter 2000",
1371 .init = ss2000_init,
1372 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1373 .nodisk_ok = 1,
1374 .use_scsi = 1,
1375 .max_cpus = 20,
1376 };
1377
1378 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1379 /* SS-2 */
1380 {
1381 .iommu_base = 0xf8000000,
1382 .tcx_base = 0xfe000000,
1383 .slavio_base = 0xf6000000,
1384 .intctl_base = 0xf5000000,
1385 .counter_base = 0xf3000000,
1386 .ms_kb_base = 0xf0000000,
1387 .serial_base = 0xf1000000,
1388 .nvram_base = 0xf2000000,
1389 .fd_base = 0xf7200000,
1390 .dma_base = 0xf8400000,
1391 .esp_base = 0xf8800000,
1392 .le_base = 0xf8c00000,
1393 .aux1_base = 0xf7400003,
1394 .vram_size = 0x00100000,
1395 .nvram_size = 0x800,
1396 .esp_irq = 2,
1397 .le_irq = 3,
1398 .clock_irq = 5,
1399 .clock1_irq = 7,
1400 .ms_kb_irq = 1,
1401 .ser_irq = 1,
1402 .fd_irq = 1,
1403 .me_irq = 1,
1404 .nvram_machine_id = 0x55,
1405 .machine_id = ss2_id,
1406 .max_mem = 0x10000000,
1407 .default_cpu_model = "Cypress CY7C601",
1408 },
1409 };
1410
1411 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1412 const char *boot_device,
1413 const char *kernel_filename,
1414 const char *kernel_cmdline,
1415 const char *initrd_filename, const char *cpu_model)
1416 {
1417 CPUState *env;
1418 unsigned int i;
1419 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1420 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1421 qemu_irq *esp_reset, *le_reset;
1422 qemu_irq *fdc_tc;
1423 ram_addr_t ram_offset, prom_offset, tcx_offset;
1424 unsigned long kernel_size;
1425 int ret;
1426 char buf[1024];
1427 BlockDriverState *fd[MAX_FD];
1428 int drive_index;
1429 void *fw_cfg;
1430
1431 /* init CPU */
1432 if (!cpu_model)
1433 cpu_model = hwdef->default_cpu_model;
1434
1435 env = cpu_init(cpu_model);
1436 if (!env) {
1437 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1438 exit(1);
1439 }
1440
1441 cpu_sparc_set_id(env, 0);
1442
1443 qemu_register_reset(main_cpu_reset, env);
1444 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1445 env->prom_addr = hwdef->slavio_base;
1446
1447 /* allocate RAM */
1448 if ((uint64_t)RAM_size > hwdef->max_mem) {
1449 fprintf(stderr,
1450 "qemu: Too much memory for this machine: %d, maximum %d\n",
1451 (unsigned int)(RAM_size / (1024 * 1024)),
1452 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1453 exit(1);
1454 }
1455 ram_offset = qemu_ram_alloc(RAM_size);
1456 cpu_register_physical_memory(0, RAM_size, ram_offset);
1457
1458 /* load boot prom */
1459 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1460 cpu_register_physical_memory(hwdef->slavio_base,
1461 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1462 TARGET_PAGE_MASK,
1463 prom_offset | IO_MEM_ROM);
1464
1465 if (bios_name == NULL)
1466 bios_name = PROM_FILENAME;
1467 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1468 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1469 if (ret < 0 || ret > PROM_SIZE_MAX)
1470 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1471 if (ret < 0 || ret > PROM_SIZE_MAX) {
1472 fprintf(stderr, "qemu: could not load prom '%s'\n",
1473 buf);
1474 exit(1);
1475 }
1476
1477 /* set up devices */
1478 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1479 &slavio_irq, cpu_irqs);
1480
1481 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1482 slavio_irq[hwdef->me_irq]);
1483
1484 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1485 iommu, &espdma_irq, &esp_reset);
1486
1487 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1488 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1489 &le_reset);
1490
1491 if (graphic_depth != 8 && graphic_depth != 24) {
1492 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1493 exit (1);
1494 }
1495 tcx_offset = qemu_ram_alloc(hwdef->vram_size);
1496 tcx_init(hwdef->tcx_base, phys_ram_base + tcx_offset, tcx_offset,
1497 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1498
1499 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1500
1501 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1502 hwdef->nvram_size, 2);
1503
1504 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1505 nographic, ESCC_CLOCK, 1);
1506 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1507 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1508 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1509 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1510 ESCC_CLOCK, 1);
1511
1512 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1513 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1514
1515 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1516 /* there is zero or one floppy drive */
1517 memset(fd, 0, sizeof(fd));
1518 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1519 if (drive_index != -1)
1520 fd[0] = drives_table[drive_index].bdrv;
1521
1522 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1523 fdc_tc);
1524 }
1525
1526 if (drive_get_max_bus(IF_SCSI) > 0) {
1527 fprintf(stderr, "qemu: too many SCSI bus\n");
1528 exit(1);
1529 }
1530
1531 main_esp = esp_init(hwdef->esp_base, 2,
1532 espdma_memory_read, espdma_memory_write,
1533 espdma, *espdma_irq, esp_reset);
1534
1535 for (i = 0; i < ESP_MAX_DEVS; i++) {
1536 drive_index = drive_get_index(IF_SCSI, 0, i);
1537 if (drive_index == -1)
1538 continue;
1539 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1540 }
1541
1542 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1543 RAM_size);
1544
1545 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1546 boot_device, RAM_size, kernel_size, graphic_width,
1547 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1548 "Sun4c");
1549
1550 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1551 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1552 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1553 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1554 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1555 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1556 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1557 if (kernel_cmdline) {
1558 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1559 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1560 } else {
1561 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1562 }
1563 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1564 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1565 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1566 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1567 }
1568
1569 /* SPARCstation 2 hardware initialisation */
1570 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1571 const char *boot_device,
1572 const char *kernel_filename, const char *kernel_cmdline,
1573 const char *initrd_filename, const char *cpu_model)
1574 {
1575 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1576 kernel_cmdline, initrd_filename, cpu_model);
1577 }
1578
1579 QEMUMachine ss2_machine = {
1580 .name = "SS-2",
1581 .desc = "Sun4c platform, SPARCstation 2",
1582 .init = ss2_init,
1583 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1584 .nodisk_ok = 1,
1585 .use_scsi = 1,
1586 };