linux: shared memory interface - link with librt
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1 class:: Trig1
2 summary:: Timed trigger.
3 related:: Classes/Trig
4 categories::  UGens>Triggers
7 Description::
9 When a nonpositive to positive transition occurs at the input, Trig1
10 outputs 1 for the specified duration, otherwise outputs 0.
13 classmethods::
15 method::ar, kr
17 argument::in
19 Trigger. Trigger can be any signal. A trigger happens when the
20 signal changes from non-positive to positive.
23 argument::dur
25 Duration of the trigger output.
28 Examples::
30 code::
32 { Trig1.ar(Dust.ar(1), 0.2) * FSinOsc.ar(800, 0.5) }.play
35 To create a fixed duration gate
38 SynthDef("trig1",{ arg dur=0.125;
39         var gate;
40         gate = Trig1.kr(1.0,dur);
41         OffsetOut.ar(0,
42                 SinOsc.ar(800, 0.3)
43                 * EnvGen.kr(
44                         Env([0,0.1,0.1,0],[0.01,1.0,0.01],[-4,4],2),
45                         gate,
46                         doneAction: 2)
47         )
48 }).send(s);
50 Routine({
51         1.0.wait;
52         100.do({
53                 s.sendBundle(0.05,["s_new", "trig1" ,-1,0,0,0,rrand(0.02,0.25)]);
54                 0.25.wait
55         })
56 }).play(SystemClock)
60 This should sound like a continous sine wave, although it is actually a series of 0.25 second synths.
62 SynthDef("trig1",{
63         var gate;
64         gate = Trig1.kr(1.0,0.25);
65         OffsetOut.ar(0,
66                 SinOsc.ar(800, 0.3)
67                 * EnvGen.kr(
68                         Env([0,0.1,0.1,0],[0.01,1.0,0.01],[-4,4],2),
69                         gate,
70                         doneAction: 2)
71         )
72 }).send(s);
74 Routine({
75         1.0.wait;
76         100.do({
77                 s.sendBundle(0.05,["s_new", "trig1" ,-1]);
78                 0.25.wait
79         })
80 }).play(SystemClock)