com32/include/cpuid.h

   1 /* ----------------------------------------------------------------------- *
   2  *
   3  *   Copyright 2006 Erwan Velu - All Rights Reserved
   4  *
   5  *   This program is free software; you can redistribute it and/or modify
   6  *   it under the terms of the GNU General Public License as published by
   7  *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8  *   Boston MA 02111-1307, USA; either version 2 of the License, or
   9  *   (at your option) any later version; incorporated herein by reference.
  10  *
  11  * ----------------------------------------------------------------------- */
  12
  13 #ifndef CPUID_H
  14 #define CPUID_H
  15
  16 #include "stdbool.h"
  17 #include "cpufeature.h"
  18 #define u32 unsigned int
  19 #define __u32 u32
  20 #define __u16 unsigned short
  21 #define __u8  unsigned char
  22 #define PAGE_SIZE 4096
  23
  24 #define CPU_MODEL_SIZE  48
  25 #define CPU_VENDOR_SIZE 48
  26
  27 typedef struct {
  28         __u32 l;
  29         __u32 h;
  30 } __u64;
  31
  32 typedef struct {
  33         bool fpu; /* Onboard FPU */
  34         bool vme; /* Virtual Mode Extensions */
  35         bool de;  /* Debugging Extensions */
  36         bool pse; /* Page Size Extensions */
  37         bool tsc; /* Time Stamp Counter */
  38         bool msr; /* Model-Specific Registers, RDMSR, WRMSR */
  39         bool pae; /* Physical Address Extensions */
  40         bool mce; /* Machine Check Architecture */
  41         bool cx8; /* CMPXCHG8 instruction */
  42         bool apic;/* Onboard APIC */
  43         bool sep; /* SYSENTER/SYSEXIT */
  44         bool mtrr;/* Memory Type Range Registers */
  45         bool pge; /* Page Global Enable */
  46         bool mca; /* Machine Check Architecture */
  47         bool cmov;/* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
  48         bool pat; /* Page Attribute Table */
  49         bool pse_36; /* 36-bit PSEs */
  50         bool psn; /* Processor serial number */
  51         bool clflsh; /* Supports the CLFLUSH instruction */
  52         bool dts; /* Debug Trace Store */
  53         bool acpi;/* ACPI via MSR */
  54         bool mmx; /* Multimedia Extensions */
  55         bool fxsr;/* FXSAVE and FXRSTOR instructions (fast save and restore */
  56                   /* of FPU context), and CR4.OSFXSR available */
  57         bool sse; /* Streaming SIMD Extensions */
  58         bool sse2;/* Streaming SIMD Extensions 2*/
  59         bool ss;  /* CPU self snoop */
  60         bool htt; /* Hyper-Threading */
  61         bool acc; /* Automatic clock control */
  62         bool syscall; /* SYSCALL/SYSRET */
  63         bool mp;  /* MP Capable. */
  64         bool nx;  /* Execute Disable */
  65         bool mmxext;  /* AMD MMX extensions */
  66         bool lm;  /* Long Mode (x86-64) */
  67         bool nowext;/* AMD 3DNow! extensions */
  68         bool now;   /* 3DNow! */
  69         bool smp;  /* A smp configuration has been found*/
  70 }  __attribute__((__packed__)) s_cpu_flags;
  71
  72 typedef struct {
  73 char vendor[CPU_VENDOR_SIZE];
  74 __u8 vendor_id;
  75 __u8 family;
  76 char model[CPU_MODEL_SIZE];
  77 __u8 model_id;
  78 __u8 stepping;
  79 s_cpu_flags flags;
  80 } s_cpu;
  81
  82 /**********************************************************************************/
  83 /**********************************************************************************/
  84 /* From this point this is some internal stuff mainly taken from the linux kernel */
  85 /**********************************************************************************/
  86 /**********************************************************************************/
  87
  88 /*
  89  * EFLAGS bits
  90  */
  91 #define X86_EFLAGS_CF   0x00000001 /* Carry Flag */
  92 #define X86_EFLAGS_PF   0x00000004 /* Parity Flag */
  93 #define X86_EFLAGS_AF   0x00000010 /* Auxillary carry Flag */
  94 #define X86_EFLAGS_ZF   0x00000040 /* Zero Flag */
  95 #define X86_EFLAGS_SF   0x00000080 /* Sign Flag */
  96 #define X86_EFLAGS_TF   0x00000100 /* Trap Flag */
  97 #define X86_EFLAGS_IF   0x00000200 /* Interrupt Flag */
  98 #define X86_EFLAGS_DF   0x00000400 /* Direction Flag */
  99 #define X86_EFLAGS_OF   0x00000800 /* Overflow Flag */
 100 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
 101 #define X86_EFLAGS_NT   0x00004000 /* Nested Task */
 102 #define X86_EFLAGS_RF   0x00010000 /* Resume Flag */
 103 #define X86_EFLAGS_VM   0x00020000 /* Virtual Mode */
 104 #define X86_EFLAGS_AC   0x00040000 /* Alignment Check */
 105 #define X86_EFLAGS_VIF  0x00080000 /* Virtual Interrupt Flag */
 106 #define X86_EFLAGS_VIP  0x00100000 /* Virtual Interrupt Pending */
 107 #define X86_EFLAGS_ID   0x00200000 /* CPUID detection flag */
 108
 109 #define X86_VENDOR_INTEL 0
 110 #define X86_VENDOR_CYRIX 1
 111 #define X86_VENDOR_AMD 2
 112 #define X86_VENDOR_UMC 3
 113 #define X86_VENDOR_NEXGEN 4
 114 #define X86_VENDOR_CENTAUR 5
 115 #define X86_VENDOR_RISE 6
 116 #define X86_VENDOR_TRANSMETA 7
 117 #define X86_VENDOR_NSC 8
 118 #define X86_VENDOR_NUM 9
 119 #define X86_VENDOR_UNKNOWN 0xff
 120
 121 static inline int test_bit(int nr, const volatile unsigned long *addr)
 122 {
 123         return ((1UL << (nr & 31)) & (addr[nr >> 5])) != 0;
 124 }
 125
 126 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 127
 128 /*
 129  *  CPU type and hardware bug flags. Kept separately for each CPU.
 130  *  Members of this structure are referenced in head.S, so think twice
 131  *  before touching them. [mj]
 132  */
 133
 134 struct cpuinfo_x86 {
 135         __u8    x86;            /* CPU family */
 136         __u8    x86_vendor;     /* CPU vendor */
 137         __u8    x86_model;
 138         __u8    x86_mask;
 139         char    wp_works_ok;    /* It doesn't on 386's */
 140         char    hlt_works_ok;   /* Problems on some 486Dx4's and old 386's */
 141         char    hard_math;
 142         char    rfu;
 143         int     cpuid_level;    /* Maximum supported CPUID level, -1=no CPUID */
 144         unsigned long   x86_capability[NCAPINTS];
 145         char    x86_vendor_id[16];
 146         char    x86_model_id[64];
 147         int     x86_cache_size;  /* in KB - valid for CPUS which support this
 148                                     call  */
 149         int     x86_cache_alignment;    /* In bytes */
 150         char    fdiv_bug;
 151         char    f00f_bug;
 152         char    coma_bug;
 153         char    pad0;
 154         int     x86_power;
 155         unsigned long loops_per_jiffy;
 156 #ifdef CONFIG_SMP
 157         cpumask_t llc_shared_map;       /* cpus sharing the last level cache */
 158 #endif
 159         unsigned char x86_max_cores;    /* cpuid returned max cores value */
 160         unsigned char booted_cores;     /* number of cores as seen by OS */
 161         unsigned char apicid;
 162 } __attribute__((__packed__));
 163 #endif
 164
 165 struct cpu_model_info {
 166         int vendor;
 167         int family;
 168         char *model_names[16];
 169 };
 170
 171 /* attempt to consolidate cpu attributes */
 172 struct cpu_dev {
 173         char    * c_vendor;
 174
 175         /* some have two possibilities for cpuid string */
 176         char    * c_ident[2];
 177
 178         struct          cpu_model_info c_models[4];
 179
 180         void            (*c_init)(struct cpuinfo_x86 * c);
 181         void            (*c_identify)(struct cpuinfo_x86 * c);
 182         unsigned int    (*c_size_cache)(struct cpuinfo_x86 * c, unsigned int size);
 183 };
 184
 185 /*
 186  * Generic CPUID function
 187  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
 188  * resulting in stale register contents being returned.
 189  */
 190 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
 191 {
 192         __asm__("cpuid"
 193                 : "=a" (*eax),
 194                   "=b" (*ebx),
 195                   "=c" (*ecx),
 196                   "=d" (*edx)
 197                 : "0" (op), "c"(0));
 198 }
 199
 200 /*
 201  * Structure definitions for SMP machines following the
 202  * Intel Multiprocessing Specification 1.1 and 1.4.
 203  */
 204
 205 /*
 206  * This tag identifies where the SMP configuration
 207  * information is.
 208  */
 209
 210 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
 211
 212 struct intel_mp_floating
 213 {
 214         char mpf_signature[4];          /* "_MP_"                       */
 215         unsigned long mpf_physptr;      /* Configuration table address  */
 216         unsigned char mpf_length;       /* Our length (paragraphs)      */
 217         unsigned char mpf_specification;/* Specification version        */
 218         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
 219         unsigned char mpf_feature1;     /* Standard or configuration ?  */
 220         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
 221         unsigned char mpf_feature3;     /* Unused (0)                   */
 222         unsigned char mpf_feature4;     /* Unused (0)                   */
 223         unsigned char mpf_feature5;     /* Unused (0)                   */
 224 };
 225
 226
 227 extern void get_cpu_vendor(struct cpuinfo_x86 *c);
 228 extern void detect_cpu(s_cpu *cpu);