Updated PCI IDs to latest snapshot.
[tangerine.git] / arch / common / boot / grub / netboot / sis900.h
blob44feafbade2024270f79fb1d26f373b3ecab76c1
1 /* -*- Mode:C; c-basic-offset:4; -*- */
3 /* Definitions for SiS ethernet controllers including 7014/7016 and 900
4 * References:
5 * SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
6 * preliminary Rev. 1.0 Jan. 14, 1998
7 * SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
8 * preliminary Rev. 1.0 Nov. 10, 1998
9 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
10 * preliminary Rev. 1.0 Jan. 18, 1998
11 * http://www.sis.com.tw/support/databook.htm
14 /* MAC operationl registers of SiS 7016 and SiS 900 ethernet controller */
15 /* The I/O extent, SiS 900 needs 256 bytes of io address */
16 #define SIS900_TOTAL_SIZE 0x100
18 /* Symbolic offsets to registers. */
19 enum sis900_registers {
20 cr=0x0, /* Command Register */
21 cfg=0x4, /* Configuration Register */
22 mear=0x8, /* EEPROM Access Register */
23 ptscr=0xc, /* PCI Test Control Register */
24 isr=0x10, /* Interrupt Status Register */
25 imr=0x14, /* Interrupt Mask Register */
26 ier=0x18, /* Interrupt Enable Register */
27 epar=0x18, /* Enhanced PHY Access Register */
28 txdp=0x20, /* Transmit Descriptor Pointer Register */
29 txcfg=0x24, /* Transmit Configuration Register */
30 rxdp=0x30, /* Receive Descriptor Pointer Register */
31 rxcfg=0x34, /* Receive Configuration Register */
32 flctrl=0x38, /* Flow Control Register */
33 rxlen=0x3c, /* Receive Packet Length Register */
34 rfcr=0x48, /* Receive Filter Control Register */
35 rfdr=0x4C, /* Receive Filter Data Register */
36 pmctrl=0xB0, /* Power Management Control Register */
37 pmer=0xB4 /* Power Management Wake-up Event Register */
40 /* Symbolic names for bits in various registers */
41 enum sis900_command_register_bits {
42 RESET = 0x00000100,
43 SWI = 0x00000080,
44 RxRESET = 0x00000020,
45 TxRESET = 0x00000010,
46 RxDIS = 0x00000008,
47 RxENA = 0x00000004,
48 TxDIS = 0x00000002,
49 TxENA = 0x00000001
52 enum sis900_configuration_register_bits {
53 DESCRFMT = 0x00000100, /* 7016 specific */
54 REQALG = 0x00000080,
55 SB = 0x00000040,
56 POW = 0x00000020,
57 EXD = 0x00000010,
58 PESEL = 0x00000008,
59 LPM = 0x00000004,
60 BEM = 0x00000001
63 enum sis900_eeprom_access_reigster_bits {
64 MDC = 0x00000040,
65 MDDIR = 0x00000020,
66 MDIO = 0x00000010, /* 7016 specific */
67 EECS = 0x00000008,
68 EECLK = 0x00000004,
69 EEDO = 0x00000002,
70 EEDI = 0x00000001
73 enum sis900_interrupt_register_bits {
74 WKEVT = 0x10000000,
75 TxPAUSEEND = 0x08000000,
76 TxPAUSE = 0x04000000,
77 TxRCMP = 0x02000000,
78 RxRCMP = 0x01000000,
79 DPERR = 0x00800000,
80 SSERR = 0x00400000,
81 RMABT = 0x00200000,
82 RTABT = 0x00100000,
83 RxSOVR = 0x00010000,
84 HIBERR = 0x00008000,
85 SWINT = 0x00001000,
86 MIBINT = 0x00000800,
87 TxURN = 0x00000400,
88 TxIDLE = 0x00000200,
89 TxERR = 0x00000100,
90 TxDESC = 0x00000080,
91 TxOK = 0x00000040,
92 RxORN = 0x00000020,
93 RxIDLE = 0x00000010,
94 RxEARLY = 0x00000008,
95 RxERR = 0x00000004,
96 RxDESC = 0x00000002,
97 RxOK = 0x00000001
100 enum sis900_interrupt_enable_reigster_bits {
101 IE = 0x00000001
104 /* maximum dma burst fro transmission and receive*/
105 #define MAX_DMA_RANGE 7 /* actually 0 means MAXIMUM !! */
106 #define TxMXDMA_shift 20
107 #define RxMXDMA_shift 20
108 #define TX_DMA_BURST 0
109 #define RX_DMA_BURST 0
111 /* transmit FIFO threshholds */
112 #define TX_FILL_THRESH 16 /* 1/4 FIFO size */
113 #define TxFILLT_shift 8
114 #define TxDRNT_shift 0
115 #define TxDRNT_100 48 /* 3/4 FIFO size */
116 #define TxDRNT_10 16 /* 1/2 FIFO size */
118 enum sis900_transmit_config_register_bits {
119 TxCSI = 0x80000000,
120 TxHBI = 0x40000000,
121 TxMLB = 0x20000000,
122 TxATP = 0x10000000,
123 TxIFG = 0x0C000000,
124 TxFILLT = 0x00003F00,
125 TxDRNT = 0x0000003F
128 /* recevie FIFO thresholds */
129 #define RxDRNT_shift 1
130 #define RxDRNT_100 16 /* 1/2 FIFO size */
131 #define RxDRNT_10 24 /* 3/4 FIFO size */
133 enum sis900_reveive_config_register_bits {
134 RxAEP = 0x80000000,
135 RxARP = 0x40000000,
136 RxATX = 0x10000000,
137 RxAJAB = 0x08000000,
138 RxDRNT = 0x0000007F
141 #define RFAA_shift 28
142 #define RFADDR_shift 16
144 enum sis900_receive_filter_control_register_bits {
145 RFEN = 0x80000000,
146 RFAAB = 0x40000000,
147 RFAAM = 0x20000000,
148 RFAAP = 0x10000000,
149 RFPromiscuous = (RFAAB|RFAAM|RFAAP)
152 enum sis900_reveive_filter_data_mask {
153 RFDAT = 0x0000FFFF
156 /* EEPROM Addresses */
157 enum sis900_eeprom_address {
158 EEPROMSignature = 0x00,
159 EEPROMVendorID = 0x02,
160 EEPROMDeviceID = 0x03,
161 EEPROMMACAddr = 0x08,
162 EEPROMChecksum = 0x0b
165 /* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
166 enum sis900_eeprom_command {
167 EEread = 0x0180,
168 EEwrite = 0x0140,
169 EEerase = 0x01C0,
170 EEwriteEnable = 0x0130,
171 EEwriteDisable = 0x0100,
172 EEeraseAll = 0x0120,
173 EEwriteAll = 0x0110,
174 EEaddrMask = 0x013F,
177 /* Manamgement Data I/O (mdio) frame */
178 #define MIIread 0x6000
179 #define MIIwrite 0x5002
180 #define MIIpmdShift 7
181 #define MIIregShift 2
182 #define MIIcmdLen 16
183 #define MIIcmdShift 16
185 /* Buffer Descriptor Status*/
186 enum sis900_buffer_status {
187 OWN = 0x80000000,
188 MORE = 0x40000000,
189 INTR = 0x20000000,
190 SUPCRC = 0x10000000,
191 INCCRC = 0x10000000,
192 OK = 0x08000000,
193 DSIZE = 0x00000FFF
196 /* Status for TX Buffers */
197 enum sis900_tx_buffer_status {
198 ABORT = 0x04000000,
199 UNDERRUN = 0x02000000,
200 NOCARRIER = 0x01000000,
201 DEFERD = 0x00800000,
202 EXCDEFER = 0x00400000,
203 OWCOLL = 0x00200000,
204 EXCCOLL = 0x00100000,
205 COLCNT = 0x000F0000
208 enum sis900_rx_bufer_status {
209 OVERRUN = 0x02000000,
210 DEST = 0x00800000,
211 BCAST = 0x01800000,
212 MCAST = 0x01000000,
213 UNIMATCH = 0x00800000,
214 TOOLONG = 0x00400000,
215 RUNT = 0x00200000,
216 RXISERR = 0x00100000,
217 CRCERR = 0x00080000,
218 FAERR = 0x00040000,
219 LOOPBK = 0x00020000,
220 RXCOL = 0x00010000
223 /* MII register offsets */
224 enum mii_registers {
225 MII_CONTROL = 0x0000,
226 MII_STATUS = 0x0001,
227 MII_PHY_ID0 = 0x0002,
228 MII_PHY_ID1 = 0x0003,
229 MII_ANADV = 0x0004,
230 MII_ANLPAR = 0x0005,
231 MII_ANEXT = 0x0006
234 /* mii registers specific to SiS 900 */
235 enum sis_mii_registers {
236 MII_CONFIG1 = 0x0010,
237 MII_CONFIG2 = 0x0011,
238 MII_STSOUT = 0x0012,
239 MII_MASK = 0x0013
242 /* mii registers specific to AMD 79C901 */
243 enum amd_mii_registers {
244 MII_STATUS_SUMMARY = 0x0018
247 /* mii registers specific to ICS 1893 */
248 enum ics_mii_registers {
249 MII_EXTCTRL = 0x0010, MII_QPDSTS = 0x0011, MII_10BTOP = 0x0012,
250 MII_EXTCTRL2 = 0x0013
255 /* MII Control register bit definitions. */
256 enum mii_control_register_bits {
257 MII_CNTL_FDX = 0x0100,
258 MII_CNTL_RST_AUTO = 0x0200,
259 MII_CNTL_ISOLATE = 0x0400,
260 MII_CNTL_PWRDWN = 0x0800,
261 MII_CNTL_AUTO = 0x1000,
262 MII_CNTL_SPEED = 0x2000,
263 MII_CNTL_LPBK = 0x4000,
264 MII_CNTL_RESET = 0x8000
267 /* MII Status register bit */
268 enum mii_status_register_bits {
269 MII_STAT_EXT = 0x0001,
270 MII_STAT_JAB = 0x0002,
271 MII_STAT_LINK = 0x0004,
272 MII_STAT_CAN_AUTO = 0x0008,
273 MII_STAT_FAULT = 0x0010,
274 MII_STAT_AUTO_DONE = 0x0020,
275 MII_STAT_CAN_T = 0x0800,
276 MII_STAT_CAN_T_FDX = 0x1000,
277 MII_STAT_CAN_TX = 0x2000,
278 MII_STAT_CAN_TX_FDX = 0x4000,
279 MII_STAT_CAN_T4 = 0x8000
282 #define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
283 #define MII_ID1_MODEL 0x03F0 /* model number */
284 #define MII_ID1_REV 0x000F /* model number */
286 /* MII NWAY Register Bits ...
287 valid for the ANAR (Auto-Negotiation Advertisement) and
288 ANLPAR (Auto-Negotiation Link Partner) registers */
289 enum mii_nway_register_bits {
290 MII_NWAY_NODE_SEL = 0x001f,
291 MII_NWAY_CSMA_CD = 0x0001,
292 MII_NWAY_T = 0x0020,
293 MII_NWAY_T_FDX = 0x0040,
294 MII_NWAY_TX = 0x0080,
295 MII_NWAY_TX_FDX = 0x0100,
296 MII_NWAY_T4 = 0x0200,
297 MII_NWAY_PAUSE = 0x0400,
298 MII_NWAY_RF = 0x2000,
299 MII_NWAY_ACK = 0x4000,
300 MII_NWAY_NP = 0x8000
303 enum mii_stsout_register_bits {
304 MII_STSOUT_LINK_FAIL = 0x4000,
305 MII_STSOUT_SPD = 0x0080,
306 MII_STSOUT_DPLX = 0x0040
309 enum mii_stsics_register_bits {
310 MII_STSICS_SPD = 0x8000, MII_STSICS_DPLX = 0x4000,
311 MII_STSICS_LINKSTS = 0x0001
314 enum mii_stssum_register_bits {
315 MII_STSSUM_LINK = 0x0008,
316 MII_STSSUM_DPLX = 0x0004,
317 MII_STSSUM_AUTO = 0x0002,
318 MII_STSSUM_SPD = 0x0001
321 enum sis900_revision_id {
322 SIS630A_900_REV = 0x80, SIS630E_900_REV = 0x81,
323 SIS630S_900_REV = 0x82, SIS630EA1_900_REV = 0x83
326 enum sis630_revision_id {
327 SIS630A0 = 0x00, SIS630A1 = 0x01,
328 SIS630B0 = 0x10, SIS630B1 = 0x11
331 #define FDX_CAPABLE_DUPLEX_UNKNOWN 0
332 #define FDX_CAPABLE_HALF_SELECTED 1
333 #define FDX_CAPABLE_FULL_SELECTED 2
335 #define HW_SPEED_UNCONFIG 0
336 #define HW_SPEED_HOME 1
337 #define HW_SPEED_10_MBPS 10
338 #define HW_SPEED_100_MBPS 100
339 #define HW_SPEED_DEFAULT (HW_SPEED_100_MBPS)
341 #define CRC_SIZE 4
342 #define MAC_HEADER_SIZE 14
344 #define TX_BUF_SIZE 1536
345 #define RX_BUF_SIZE 1536
347 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
349 typedef unsigned char u8;
350 typedef signed char s8;
351 typedef unsigned short u16;
352 typedef signed short s16;
353 typedef unsigned int u32;
354 typedef signed int s32;
356 /* Time in ticks before concluding the transmitter is hung. */
357 #define TX_TIMEOUT (4*TICKS_PER_SEC)
359 typedef struct _BufferDesc {
360 u32 link;
361 volatile u32 cmdsts;
362 u32 bufptr;
363 } BufferDesc;