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only bring in as many sdl things as are strictly necessary
[tangerine.git] / arch / common / hidd.radeon / radeon_driver.c
blob727e838c4cfab49376af443e6d3345fb8951a30b
1 /*
2 Copyright © 2004, The AROS Development Team. All rights reserved.
3 $Id$
4 */
5
6 #include "ati.h"
7 #include "radeon.h"
8 #include "radeon_reg.h"
9 #include "radeon_bios.h"
10 #include "radeon_accel.h"
11 #include "radeon_macros.h"
12
13 #include "bitmap.h"
14
15 #include <math.h>
16
17 #define DEBUG 0
18 #include <aros/debug.h>
19
20 #include <proto/oop.h>
21 #include <hidd/i2c.h>
22
23 #define MAX(a,b) ((a) > (b) ? (a) : (b))
24
25 static void usleep(struct ati_staticdata *sd, ULONG usec)
26 {
27 D(bug("[ATI] usleep(%p, %d)\n", sd, usec));
28 sd->mp.mp_SigTask = FindTask(NULL);
29 sd->tr.tr_node.io_Command = TR_ADDREQUEST;
30 sd->tr.tr_time.tv_secs = usec / 1000000;
31 sd->tr.tr_time.tv_micro = usec % 1000000;
32
33 DoIO((struct IORequest *)&sd->tr);
34
35 sd->mp.mp_SigTask = NULL;
36 }
37
38 /* Compute n/d with rounding */
39 static int RADEONDiv(int n, int d)
40 {
41 return (n + (d / 2)) / d;
42 }
43
44 /* This function is required to workaround a hardware bug in some (all?)
45 * revisions of the R300. This workaround should be called after every
46 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
47 * may not be correct.
48 */
49 void R300CGWorkaround(struct ati_staticdata *sd)
50 {
51 ULONG save, tmp;
52
53 save = INREG(RADEON_CLOCK_CNTL_INDEX);
54 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
55 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
56 tmp = INREG(RADEON_CLOCK_CNTL_DATA);
57 OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
58 }
59
60 void RADEONPllErrataAfterIndex(struct ati_staticdata *sd)
61 {
62 if (!(sd->Card.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS))
63 return;
64
65 /* This workaround is necessary on rv200 and RS200 or PLL
66 * reads may return garbage (among others...)
67 */
68 (void)INREG(RADEON_CLOCK_CNTL_DATA);
69 (void)INREG(RADEON_CRTC_GEN_CNTL);
70 }
71
72 void RADEONPllErrataAfterData(struct ati_staticdata *sd)
73 {
74 /* This workarounds is necessary on RV100, RS100 and RS200 chips
75 * or the chip could hang on a subsequent access
76 */
77 if (sd->Card.ChipErrata & CHIP_ERRATA_PLL_DELAY) {
78 /* we can't deal with posted writes here ... */
79 usleep(sd, 5000);
80 }
81
82 /* This function is required to workaround a hardware bug in some (all?)
83 * revisions of the R300. This workaround should be called after every
84 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
85 * may not be correct.
86 */
87 if (sd->Card.ChipErrata & CHIP_ERRATA_R300_CG) {
88 ULONG save, tmp;
89
90 save = INREG(RADEON_CLOCK_CNTL_INDEX);
91 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
92 OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp);
93 tmp = INREG(RADEON_CLOCK_CNTL_DATA);
94 OUTREG(RADEON_CLOCK_CNTL_INDEX, save);
95 }
96 }
97
98 /* Read PLL information */
99 unsigned RADEONINPLL(struct ati_staticdata *sd, int addr)
100 {
101 ULONG data;
102
103 OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
104 RADEONPllErrataAfterIndex(sd);
105 data = INREG(RADEON_CLOCK_CNTL_DATA);
106 RADEONPllErrataAfterData(sd);
107
108 return data;
109 }
110
111 /* Blank screen */
112 static void RADEONBlank(struct ati_staticdata *sd)
113 {
114 if (!sd->Card.IsSecondary) {
115 switch(sd->Card.MonType1) {
116 case MT_LCD:
117 case MT_CRT:
118 case MT_DFP:
119 OUTREGP(RADEON_CRTC_EXT_CNTL,
120 RADEON_CRTC_DISPLAY_DIS,
121 ~(RADEON_CRTC_DISPLAY_DIS));
122 break;
123
124 case MT_NONE:
125 default:
126 break;
127 }
128 } else {
129 OUTREGP(RADEON_CRTC2_GEN_CNTL,
130 RADEON_CRTC2_DISP_DIS,
131 ~(RADEON_CRTC2_DISP_DIS));
132 }
133 }
134
135 /* Unblank screen */
136 static void RADEONUnblank(struct ati_staticdata *sd)
137 {
138 if (!sd->Card.IsSecondary) {
139 switch (sd->Card.MonType1) {
140 case MT_LCD:
141 case MT_CRT:
142 case MT_DFP:
143 OUTREGP(RADEON_CRTC_EXT_CNTL,
144 RADEON_CRTC_CRT_ON,
145 ~(RADEON_CRTC_DISPLAY_DIS));
146 break;
147
148 case MT_NONE:
149 default:
150 break;
151 }
152 } else {
153 switch (sd->Card.MonType1) {
154 case MT_LCD:
155 case MT_DFP:
156 case MT_CRT:
157 OUTREGP(RADEON_CRTC2_GEN_CNTL,
158 0,
159 ~(RADEON_CRTC2_DISP_DIS));
160 break;
161
162 case MT_NONE:
163 default:
164 break;
165 }
166 }
167 }
168
169 //static void RADEONPLLWaitForReadUpdateComplete(struct ati_staticdata *sd)
170 //{
171 // int i = 0;
172 //
173 // /* FIXME: Certain revisions of R300 can't recover here. Not sure of
174 // the cause yet, but this workaround will mask the problem for now.
175 // Other chips usually will pass at the very first test, so the
176 // workaround shouldn't have any effect on them. */
177 // for (i = 0;
178 // (i < 100000 &&
179 // RADEONINPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
180 // i++);
181 //}
182 //
183 //static void RADEONPLLWriteUpdate(struct ati_staticdata *sd)
184 //{
185 // while (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
186 //
187 // OUTPLLP(sd, RADEON_PPLL_REF_DIV,
188 // RADEON_PPLL_ATOMIC_UPDATE_W,
189 // ~(RADEON_PPLL_ATOMIC_UPDATE_W));
190 //}
191
192 /* Calculate display buffer watermark to prevent buffer underflow */
193 static void RADEONInitDispBandwidth(struct ati_staticdata *sd, struct CardState *mode)
194 {
195 ULONG temp, data, mem_trcd, mem_trp, mem_tras, mem_trbs=0;
196 float mem_tcas;
197 int k1, c;
198 ULONG MemTrcdExtMemCntl[4] = {1, 2, 3, 4};
199 ULONG MemTrpExtMemCntl[4] = {1, 2, 3, 4};
200 ULONG MemTrasExtMemCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
201
202 ULONG MemTrcdMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
203 ULONG MemTrpMemTimingCntl[8] = {1, 2, 3, 4, 5, 6, 7, 8};
204 ULONG MemTrasMemTimingCntl[16] = {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19};
205
206 float MemTcas[8] = {0, 1, 2, 3, 0, 1.5, 2.5, 0};
207 float MemTcas2[8] = {0, 1, 2, 3, 4, 5, 6, 7};
208 float MemTrbs[8] = {1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5};
209
210 float mem_bw, peak_disp_bw;
211 float min_mem_eff = 0.8;
212 float sclk_eff, sclk_delay;
213 float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
214 float disp_latency, disp_latency_overhead, disp_drain_rate, disp_drain_rate2;
215 float pix_clk, pix_clk2; /* in MHz */
216 int cur_size = 16; /* in octawords */
217 int critical_point;
218 int stop_req, max_stop_req;
219
220 /* R420 family not supported yet */
221 if (sd->Card.Type == R420) return;
222
223 /*
224 * Determine if there is enough bandwidth for current display mode
225 */
226 mem_bw = sd->Card.mclk * (sd->Card.RamWidth / 8) * (sd->Card.IsDDR ? 2 : 1);
227
228 pix_clk = mode->pixelc/1000.0;
229 pix_clk2 = 0;
230
231 peak_disp_bw = (pix_clk * mode->bpp);
232
233 D(bug("[ATI] mem_bw=%d peak_disp_bw=%d mode->bpp=%d mode->pixelc=%d mode->HDisplay=%d\n", (ULONG)mem_bw, (ULONG)peak_disp_bw,
234 mode->bpp, mode->pixelc, mode->HDisplay));
235
236 if (peak_disp_bw >= mem_bw * min_mem_eff) {
237 D(bug("[ATI] You may not have enough display bandwidth for current mode\n"
238 "[ATI] If you have flickering problem, try to lower resolution, refresh rate, or color depth\n"));
239 }
240
241 /* CRTC1
242 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
243 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
244 */
245 stop_req = mode->HDisplay * mode->bpp / 16;
246
247 /* setup Max GRPH_STOP_REQ default value */
248 if (IS_RV100_VARIANT)
249 max_stop_req = 0x5c;
250 else
251 max_stop_req = 0x7c;
252 if (stop_req > max_stop_req)
253 stop_req = max_stop_req;
254
255 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
256 temp = INREG(RADEON_MEM_TIMING_CNTL);
257 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
258 mem_trcd = MemTrcdExtMemCntl[(temp & 0x0c) >> 2];
259 mem_trp = MemTrpExtMemCntl[ (temp & 0x03) >> 0];
260 mem_tras = MemTrasExtMemCntl[(temp & 0x70) >> 4];
261 } else { /* RV200 and later */
262 mem_trcd = MemTrcdMemTimingCntl[(temp & 0x07) >> 0];
263 mem_trp = MemTrpMemTimingCntl[ (temp & 0x700) >> 8];
264 mem_tras = MemTrasMemTimingCntl[(temp & 0xf000) >> 12];
265 }
266
267 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
268 temp = INREG(RADEON_MEM_SDRAM_MODE_REG);
269 data = (temp & (7<<20)) >> 20;
270 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
271 mem_tcas = MemTcas [data];
272 } else {
273 mem_tcas = MemTcas2 [data];
274 }
275
276 if (IS_R300_VARIANT) {
277
278 /* on the R300, Tcas is included in Trbs.
279 */
280 temp = INREG(RADEON_MEM_CNTL);
281 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
282 if (data == 2) {
283 if (R300_MEM_USE_CD_CH_ONLY & temp) {
284 temp = INREG(R300_MC_IND_INDEX);
285 temp &= ~R300_MC_IND_ADDR_MASK;
286 temp |= R300_MC_READ_CNTL_CD_mcind;
287 OUTREG(R300_MC_IND_INDEX, temp);
288 temp = INREG(R300_MC_IND_DATA);
289 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
290 } else {
291 temp = INREG(R300_MC_READ_CNTL_AB);
292 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
293 }
294 } else {
295 temp = INREG(R300_MC_READ_CNTL_AB);
296 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
297 }
298
299 mem_trbs = MemTrbs[data];
300 mem_tcas += mem_trbs;
301 }
302
303 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) { /* RV100, M6, IGPs */
304 /* DDR64 SCLK_EFF = SCLK for analysis */
305 sclk_eff = sd->Card.sclk;
306 } else {
307 sclk_eff = sd->Card.sclk;
308 }
309
310 /* Find the memory controller latency for the display client.
311 */
312 if (IS_R300_VARIANT) {
313 /*not enough for R350 ???*/
314 /*
315 if (!mode2) sclk_delay = 150;
316 else {
317 if (info->RamWidth == 256) sclk_delay = 87;
318 else sclk_delay = 97;
319 }
320 */
321 sclk_delay = 250;
322 } else {
323 if ((sd->Card.Type == RV100) || sd->Card.IsIGP) {
324 if (sd->Card.IsDDR) sclk_delay = 41;
325 else sclk_delay = 33;
326 } else {
327 if (sd->Card.RamWidth == 128) sclk_delay = 57;
328 else sclk_delay = 41;
329 }
330 }
331
332 mc_latency_sclk = sclk_delay / sclk_eff;
333
334 if (sd->Card.IsDDR) {
335 if (sd->Card.RamWidth == 32) {
336 k1 = 40;
337 c = 3;
338 } else {
339 k1 = 20;
340 c = 1;
341 }
342 } else {
343 k1 = 40;
344 c = 3;
345 }
346 mc_latency_mclk = ((2.0*mem_trcd + mem_tcas*c + 4.0*mem_tras + 4.0*mem_trp + k1) /
347 sd->Card.mclk) + (4.0 / sclk_eff);
348
349 /*
350 HW cursor time assuming worst case of full size colour cursor.
351 */
352 cur_latency_mclk = (mem_trp + MAX(mem_tras, (mem_trcd + 2*(cur_size - (sd->Card.IsDDR+1))))) / sd->Card.mclk;
353 cur_latency_sclk = cur_size / sclk_eff;
354
355 /*
356 Find the total latency for the display data.
357 */
358 disp_latency_overhead = 8.0 / sd->Card.sclk;
359 mc_latency_mclk = mc_latency_mclk + disp_latency_overhead + cur_latency_mclk;
360 mc_latency_sclk = mc_latency_sclk + disp_latency_overhead + cur_latency_sclk;
361 disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
362
363 /*
364 Find the drain rate of the display buffer.
365 */
366 disp_drain_rate = pix_clk / (16.0/mode->bpp);
367 disp_drain_rate2 = 0;
368
369 /*
370 Find the critical point of the display buffer.
371 */
372 critical_point= (ULONG)(disp_drain_rate * disp_latency + 0.5);
373
374 /* ???? */
375 /*
376 temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
377 if (critical_point < temp) critical_point = temp;
378 */
379
380 /*
381 The critical point should never be above max_stop_req-4. Setting
382 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
383 */
384 if (max_stop_req - critical_point < 4) critical_point = 0;
385
386 temp = sd->poweron_state->grph_buffer_cntl;
387 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
388 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
389 temp &= ~(RADEON_GRPH_START_REQ_MASK);
390 if ((sd->Card.Type == R350) &&
391 (stop_req > 0x15)) {
392 stop_req -= 0x10;
393 }
394 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
395
396 temp |= RADEON_GRPH_BUFFER_SIZE;
397 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
398 RADEON_GRPH_CRITICAL_AT_SOF |
399 RADEON_GRPH_STOP_CNTL);
400 /*
401 Write the result into the register.
402 */
403 OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
404 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
405
406 D(bug("[ATI] GRPH_BUFFER_CNTL from %x to %x\n",
407 sd->poweron_state->grph_buffer_cntl, INREG(RADEON_GRPH_BUFFER_CNTL)));
408
409 }
410
411 /*
412 * Powering done DAC, needed for DPMS problem with ViewSonic P817 (or its variant).
413 *
414 * Note for current DAC mapping when calling this function:
415 * For most of cards:
416 * single CRT: Driver doesn't change the existing CRTC->DAC mapping,
417 * CRTC1 could be driving either DAC or both DACs.
418 * CRT+CRT: CRTC1->TV DAC, CRTC2->Primary DAC
419 * DFP/LCD+CRT: CRTC2->TV DAC, CRTC2->Primary DAC.
420 * Some boards have two DACs reversed or don't even have a primary DAC,
421 * this is reflected in pRADEONEnt->ReversedDAC. And radeon 7200 doesn't
422 * have a second DAC.
423 * It's kind of messy, we'll need to redo DAC mapping part some day.
424 */
425 static void RADEONDacPowerSet(struct ati_staticdata *sd, BOOL IsOn, BOOL IsPrimaryDAC)
426 {
427 if (IsPrimaryDAC) {
428 ULONG dac_cntl;
429 ULONG dac_macro_cntl = 0;
430 dac_cntl = INREG(RADEON_DAC_CNTL);
431 if ((!sd->Card.IsMobility) || (sd->Card.Type == RV350))
432 dac_macro_cntl = INREG(RADEON_DAC_MACRO_CNTL);
433 if (IsOn) {
434 dac_cntl &= ~RADEON_DAC_PDWN;
435 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
436 RADEON_DAC_PDWN_G |
437 RADEON_DAC_PDWN_B);
438 } else {
439 dac_cntl |= RADEON_DAC_PDWN;
440 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
441 RADEON_DAC_PDWN_G |
442 RADEON_DAC_PDWN_B);
443 }
444 OUTREG(RADEON_DAC_CNTL, dac_cntl);
445 if ((!sd->Card.IsMobility) || (sd->Card.Type == RV350))
446 OUTREG(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
447 } else {
448 if (sd->Card.Type != R200) {
449 ULONG tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
450 if (IsOn) {
451 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
452 RADEON_TV_DAC_GDACPD |
453 RADEON_TV_DAC_BDACPD |
454 RADEON_TV_DAC_BGSLEEP);
455 } else {
456 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
457 RADEON_TV_DAC_GDACPD |
458 RADEON_TV_DAC_BDACPD |
459 RADEON_TV_DAC_BGSLEEP);
460 }
461 OUTREG(RADEON_TV_DAC_CNTL, tv_dac_cntl);
462 } else {
463 ULONG fp2_gen_cntl = INREG(RADEON_FP2_GEN_CNTL);
464 if (IsOn) {
465 fp2_gen_cntl |= RADEON_FP2_DVO_EN;
466 } else {
467 fp2_gen_cntl &= ~RADEON_FP2_DVO_EN;
468 }
469 OUTREG(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
470 }
471 }
472 }
473
474 /* Define common registers for requested video mode */
475 static void RADEONInitCommonRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *info)
476 {
477 save->ovr_clr = 0;
478 save->ovr_wid_left_right = 0;
479 save->ovr_wid_top_bottom = 0;
480 save->ov0_scale_cntl = 0;
481 save->subpic_cntl = 0;
482 save->viph_control = 0;
483 save->i2c_cntl_1 = 0;
484 save->rbbm_soft_reset = 0;
485 save->cap0_trig_cntl = 0;
486 save->cap1_trig_cntl = 0;
487 save->bus_cntl = sd->Card.BusCntl;
488 /*
489 * If bursts are enabled, turn on discards
490 * Radeon doesn't have write bursts
491 */
492 if (save->bus_cntl & (RADEON_BUS_READ_BURST))
493 save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
494 }
495
496 /* Define CRTC registers for requested video mode */
497 static BOOL RADEONInitCrtcRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
498 {
499 int format;
500 int hsync_start;
501 int hsync_wid;
502 int vsync_wid;
503
504 switch (mode->bpp) {
505 case 15: format = 3; mode->bpp = 16; break; /* 555 */
506 case 16: format = 4; break; /* 565 */
507 case 24: format = 5; mode->bpp = 32; break; /* RGB */
508 case 32: format = 6; break; /* xRGB */
509 default:
510 return FALSE;
511 }
512
513 if (mode->bpp == 16)
514 save->bpp = 2;
515 else
516 save->bpp = 4;
517
518 if ((sd->Card.MonType1 == MT_DFP) ||
519 (sd->Card.MonType1 == MT_LCD))
520 {
521 if (mode->Flags & RADEON_USE_RMX)
522 {
523 mode->HTotal = mode->HDisplay + sd->Card.HBlank;
524 mode->HSyncStart = mode->HDisplay + sd->Card.HOverPlus;
525 mode->HSyncEnd = mode->HSyncStart + sd->Card.HSyncWidth;
526
527 mode->VTotal = mode->VDisplay + sd->Card.VBlank;
528 mode->VSyncStart = mode->VDisplay + sd->Card.VOverPlus;
529 mode->VSyncEnd = mode->VSyncStart + sd->Card.VSyncWidth;
530
531 mode->pixelc = sd->Card.DotClock;
532 mode->Flags = sd->Card.Flags | RADEON_USE_RMX;
533 }
534 }
535
536 save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
537 | RADEON_CRTC_EN
538 | RADEON_CRTC_ARGB_EN
539 | (format << 8)
540 | ((mode->height < 400)
541 ? RADEON_CRTC_DBL_SCAN_EN
542 : 0));
543
544 if ((sd->Card.MonType1 == MT_DFP) ||
545 (sd->Card.MonType1 == MT_LCD)) {
546 save->crtc_ext_cntl = RADEON_VGA_ATI_LINEAR | RADEON_XCRT_CNT_EN;
547 save->crtc_gen_cntl &= ~(RADEON_CRTC_DBL_SCAN_EN |
548 RADEON_CRTC_CSYNC_EN |
549 RADEON_CRTC_INTERLACE_EN);
550 } else {
551 save->crtc_ext_cntl = (RADEON_VGA_ATI_LINEAR |
552 RADEON_XCRT_CNT_EN |
553 RADEON_CRTC_CRT_ON);
554 }
555
556 save->dac_cntl = (RADEON_DAC_MASK_ALL
557 | RADEON_DAC_VGA_ADR_EN
558 | RADEON_DAC_8BIT_EN);
559
560 save->crtc_h_total_disp = ((((mode->HTotal / 8) - 1) & 0x3ff)
561 | ((((mode->HDisplay / 8) - 1) & 0x1ff) << 16));
562
563 hsync_wid = (mode->HSyncEnd - mode->HSyncStart) / 8;
564 if (!hsync_wid) hsync_wid = 1;
565 hsync_start = mode->HSyncStart - 8;
566
567 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
568 | ((hsync_wid & 0x3f) << 16));
569
570 /* This works for double scan mode. */
571 save->crtc_v_total_disp = (((mode->VTotal - 1) & 0xffff)
572 | ((mode->VDisplay - 1) << 16));
573
574 vsync_wid = mode->VSyncEnd - mode->VSyncStart;
575 if (!vsync_wid) vsync_wid = 1;
576
577 save->crtc_v_sync_strt_wid = (((mode->VSyncStart - 1) & 0xfff)
578 | ((vsync_wid & 0x1f) << 16));
579
580 save->crtc_offset = mode->base;
581 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
582
583 save->crtc_pitch = (((mode->width * mode->bpp) +
584 ((mode->bpp * 8) -1)) /
585 (mode->bpp * 8));
586
587 D(bug("[RADEON] crtc_pitch = %08x\n", save->crtc_pitch));
588
589 save->crtc_pitch |= save->crtc_pitch << 16;
590
591 save->crtc_more_cntl = 0;
592 if ((sd->Card.Type == RS100) ||
593 (sd->Card.Type == RS200)) {
594 /* This is to workaround the asic bug for RMX, some versions
595 of BIOS dosen't have this register initialized correctly.
596 */
597 save->crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
598 }
599
600 save->surface_cntl = 0;
601 save->disp_merge_cntl = sd->poweron_state->disp_merge_cntl;
602 save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
603
604 #if AROS_BIG_ENDIAN
605 /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
606 switch (mode->bpp) {
607 case 16:
608 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
609 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
610 break;
611
612 case 32:
613 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
614 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
615 break;
616 }
617 #endif
618
619 return TRUE;
620 }
621
622 /* Define CRTC registers for requested video mode */
623 static BOOL RADEONInitCrtc2Registers(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
624 {
625 int format;
626 int hsync_start;
627 int hsync_wid;
628 int vsync_wid;
629
630 switch (mode->bpp) {
631 case 15: format = 3; mode->bpp = 16; break; /* 555 */
632 case 16: format = 4; break; /* 565 */
633 case 24: format = 5; mode->bpp = 32; break; /* RGB */
634 case 32: format = 6; break; /* xRGB */
635 default:
636 return FALSE;
637 }
638
639 if (mode->bpp == 16)
640 save->bpp = 2;
641 else
642 save->bpp = 4;
643
644 save->crtc2_gen_cntl = (RADEON_CRTC2_EN
645 | RADEON_CRTC2_CRT2_ON
646 | RADEON_CRTC_ARGB_EN
647 | (format << 8)
648 | ((mode->height < 400)
649 ? RADEON_CRTC2_DBL_SCAN_EN
650 : 0));
651
652 /* Turn CRT on in case the first head is a DFP */
653 save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
654 save->dac2_cntl = sd->poweron_state->dac2_cntl;
655 /* always let TVDAC drive CRT2, we don't support tvout yet */
656 save->dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
657 save->disp_output_cntl = sd->poweron_state->disp_output_cntl;
658 if (sd->Card.Type == R200 || IS_R300_VARIANT) {
659 save->disp_output_cntl &= ~(RADEON_DISP_DAC_SOURCE_MASK |
660 RADEON_DISP_DAC2_SOURCE_MASK);
661 if (sd->Card.MonType2 != MT_CRT) {
662 save->disp_output_cntl |= (RADEON_DISP_DAC_SOURCE_CRTC2 |
663 RADEON_DISP_DAC2_SOURCE_CRTC2);
664 } else {
665 if (sd->Card.ReversedDAC) {
666 save->disp_output_cntl |= RADEON_DISP_DAC2_SOURCE_CRTC2;
667 } else {
668 save->disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
669 }
670 }
671 } else {
672 save->disp_hw_debug = sd->poweron_state->disp_hw_debug;
673 /* Turn on 2nd CRT */
674 if (sd->Card.MonType2 != MT_CRT) {
675 /* This is for some sample boards with the VGA port
676 connected to the TVDAC, but BIOS doesn't reflect this.
677 Here we configure both DACs to use CRTC2.
678 Not sure if this happens in any retail board.
679 */
680 save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
681 save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
682 } else {
683 if (sd->Card.ReversedDAC) {
684 save->disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
685 save->dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
686 } else {
687 save->disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
688 save->dac2_cntl |= RADEON_DAC2_DAC_CLK_SEL;
689 }
690 }
691 }
692
693 save->crtc2_h_total_disp =
694 ((((mode->HTotal / 8) - 1) & 0x3ff)
695 | ((((mode->HDisplay / 8) - 1) & 0x1ff) << 16));
696
697 hsync_wid = (mode->HSyncEnd - mode->HSyncStart) / 8;
698 if (!hsync_wid) hsync_wid = 1;
699 hsync_start = mode->HSyncStart - 8;
700
701 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
702 | ((hsync_wid & 0x3f) << 16));
703
704 /* This works for double scan mode. */
705 save->crtc2_v_total_disp = (((mode->VTotal - 1) & 0xffff)
706 | ((mode->VDisplay - 1) << 16));
707
708 vsync_wid = mode->VSyncEnd - mode->VSyncStart;
709 if (!vsync_wid) vsync_wid = 1;
710
711 save->crtc2_v_sync_strt_wid = (((mode->VSyncStart - 1) & 0xfff)
712 | ((vsync_wid & 0x1f) << 16));
713
714 save->crtc2_offset = mode->base;
715 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
716 /* this should be right */
717 save->crtc2_pitch = (((mode->width * mode->bpp) +
718 ((mode->bpp * 8) -1)) /
719 (mode->bpp * 8));
720 save->crtc2_pitch |= save->crtc2_pitch << 16;
721
722 save->disp2_merge_cntl = sd->poweron_state->disp2_merge_cntl;
723 save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
724
725 if (sd->Card.MonType2 == MT_DFP && sd->Card.IsSecondary) {
726 save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8));
727 save->fp2_h_sync_strt_wid = save->crtc2_h_sync_strt_wid;
728 save->fp2_v_sync_strt_wid = save->crtc2_v_sync_strt_wid;
729 save->fp2_gen_cntl = sd->poweron_state->fp2_gen_cntl | RADEON_FP2_ON;
730
731 if (sd->Card.Type == R200 || IS_R300_VARIANT) {
732 save->fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
733 RADEON_FP2_DVO_RATE_SEL_SDR);
734
735 save->fp2_gen_cntl |= (R200_FP2_SOURCE_SEL_CRTC2 |
736 RADEON_FP2_DVO_EN);
737 } else {
738 save->fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_MASK;
739 save->fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
740 }
741
742 save->fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format */
743 }
744
745 save->surface_cntl = 0;
746
747 #if AROS_BIG_ENDIAN
748 /* Alhought we current onlu use aperture 0, also setting aperture 1 should not harm -ReneR */
749 switch (mode->bpp) {
750 case 16:
751 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
752 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_16BPP;
753 break;
754
755 case 32:
756 save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
757 save->surface_cntl |= RADEON_NONSURF_AP1_SWP_32BPP;
758 break;
759 }
760 #endif
761
762 return TRUE;
763 }
764
765 /* Define CRTC registers for requested video mode */
766 static void RADEONInitFPRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
767 {
768 int xres = mode->HDisplay;
769 int yres = mode->VDisplay;
770 float Hratio, Vratio;
771
772 /* If the FP registers have been initialized before for a panel,
773 * but the primary port is a CRT, we need to reinitialize
774 * FP registers in order for CRT to work properly
775 */
776
777 if ((sd->Card.MonType1 != MT_DFP) && (sd->Card.MonType1 != MT_LCD)) {
778 save->fp_crtc_h_total_disp = sd->poweron_state->fp_crtc_h_total_disp;
779 save->fp_crtc_v_total_disp = sd->poweron_state->fp_crtc_v_total_disp;
780 save->fp_gen_cntl = 0;
781 save->fp_h_sync_strt_wid = sd->poweron_state->fp_h_sync_strt_wid;
782 save->fp_horz_stretch = 0;
783 save->fp_v_sync_strt_wid = sd->poweron_state->fp_v_sync_strt_wid;
784 save->fp_vert_stretch = 0;
785 save->lvds_gen_cntl = sd->poweron_state->lvds_gen_cntl;
786 save->lvds_pll_cntl = sd->poweron_state->lvds_pll_cntl;
787 save->tmds_pll_cntl = sd->poweron_state->tmds_pll_cntl;
788 save->tmds_transmitter_cntl= sd->poweron_state->tmds_transmitter_cntl;
789
790 save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23));
791 save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
792 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
793
794 return;
795 }
796
797 if (sd->Card.PanelXRes == 0 || sd->Card.PanelYRes == 0) {
798 Hratio = 1.0;
799 Vratio = 1.0;
800 } else {
801 if (xres > sd->Card.PanelXRes) xres = sd->Card.PanelXRes;
802 if (yres > sd->Card.PanelYRes) yres = sd->Card.PanelYRes;
803
804 Hratio = (float)xres/(float)sd->Card.PanelXRes;
805 Vratio = (float)yres/(float)sd->Card.PanelYRes;
806 }
807
808 if (Hratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
809 save->fp_horz_stretch = sd->poweron_state->fp_horz_stretch;
810 save->fp_horz_stretch &= ~(RADEON_HORZ_STRETCH_BLEND |
811 RADEON_HORZ_STRETCH_ENABLE);
812 save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
813 RADEON_HORZ_PANEL_SIZE);
814 save->fp_horz_stretch |= ((xres/8-1)<<16);
815 } else {
816 save->fp_horz_stretch =
817 ((((unsigned long)(Hratio * RADEON_HORZ_STRETCH_RATIO_MAX +
818 0.5)) & RADEON_HORZ_STRETCH_RATIO_MASK)) |
819 (sd->poweron_state->fp_horz_stretch & (RADEON_HORZ_PANEL_SIZE |
820 RADEON_HORZ_FP_LOOP_STRETCH |
821 RADEON_HORZ_AUTO_RATIO_INC));
822 save->fp_horz_stretch |= (RADEON_HORZ_STRETCH_BLEND |
823 RADEON_HORZ_STRETCH_ENABLE);
824
825 save->fp_horz_stretch &= ~(RADEON_HORZ_AUTO_RATIO |
826 RADEON_HORZ_PANEL_SIZE);
827 save->fp_horz_stretch |= ((sd->Card.PanelXRes / 8 - 1) << 16);
828 }
829
830 if (Vratio == 1.0 || !(mode->Flags & RADEON_USE_RMX)) {
831 save->fp_vert_stretch = sd->poweron_state->fp_vert_stretch;
832 save->fp_vert_stretch &= ~(RADEON_VERT_STRETCH_ENABLE|
833 RADEON_VERT_STRETCH_BLEND);
834 save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
835 RADEON_VERT_PANEL_SIZE);
836 save->fp_vert_stretch |= ((yres-1) << 12);
837 } else {
838 save->fp_vert_stretch =
839 (((((unsigned long)(Vratio * RADEON_VERT_STRETCH_RATIO_MAX +
840 0.5)) & RADEON_VERT_STRETCH_RATIO_MASK)) |
841 (sd->poweron_state->fp_vert_stretch & (RADEON_VERT_PANEL_SIZE |
842 RADEON_VERT_STRETCH_RESERVED)));
843 save->fp_vert_stretch |= (RADEON_VERT_STRETCH_ENABLE |
844 RADEON_VERT_STRETCH_BLEND);
845
846 save->fp_vert_stretch &= ~(RADEON_VERT_AUTO_RATIO_EN |
847 RADEON_VERT_PANEL_SIZE);
848 save->fp_vert_stretch |= ((sd->Card.PanelYRes-1) << 12);
849 }
850
851 save->fp_gen_cntl = (sd->poweron_state->fp_gen_cntl & (ULONG)
852 ~(RADEON_FP_SEL_CRTC2 |
853 RADEON_FP_RMX_HVSYNC_CONTROL_EN |
854 RADEON_FP_DFP_SYNC_SEL |
855 RADEON_FP_CRT_SYNC_SEL |
856 RADEON_FP_CRTC_LOCK_8DOT |
857 RADEON_FP_USE_SHADOW_EN |
858 RADEON_FP_CRTC_USE_SHADOW_VEND |
859 RADEON_FP_CRT_SYNC_ALT));
860 save->fp_gen_cntl |= (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
861 RADEON_FP_CRTC_DONT_SHADOW_HEND );
862
863 save->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
864
865 if (IS_R300_VARIANT || (sd->Card.Type == R200)) {
866 save->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
867 if (sd->Card.Flags & RADEON_USE_RMX)
868 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
869 else
870 save->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
871 } else
872 save->fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
873
874 save->lvds_gen_cntl = sd->poweron_state->lvds_gen_cntl;
875 save->lvds_pll_cntl = sd->poweron_state->lvds_pll_cntl;
876
877 save->tmds_pll_cntl = sd->poweron_state->tmds_pll_cntl;
878 save->tmds_transmitter_cntl= sd->poweron_state->tmds_transmitter_cntl;
879
880 if (sd->Card.MonType1 == MT_LCD) {
881
882 save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON);
883 save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
884
885 } else if (sd->Card.MonType1 == MT_DFP) {
886 int i;
887 ULONG tmp = sd->poweron_state->tmds_pll_cntl & 0xfffff;
888 for (i=0; i<4; i++) {
889 if (sd->Card.tmds_pll[i].freq == 0) break;
890 if (save->dot_clock_freq < sd->Card.tmds_pll[i].freq) {
891 tmp = sd->Card.tmds_pll[i].value ;
892 break;
893 }
894 }
895 if (IS_R300_VARIANT || (sd->Card.Type == RV280)) {
896 if (tmp & 0xfff00000)
897 save->tmds_pll_cntl = tmp;
898 else
899 save->tmds_pll_cntl = (sd->poweron_state->tmds_pll_cntl & 0xfff00000) | tmp;
900 } else save->tmds_pll_cntl = tmp;
901
902 D(bug("[ATI] TMDS_PLL from %x to %x\n",
903 sd->poweron_state->tmds_pll_cntl,
904 save->tmds_pll_cntl));
905
906 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
907
908 if (IS_R300_VARIANT || (sd->Card.Type == R200)) // || !sd->Card.HasCRTC2)
909 save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
910 else /* weird, RV chips got this bit reversed? */
911 save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
912
913 save->fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
914 }
915
916 if (sd->Card.IsMobility) {
917 /* To work correctly with laptop hotkeys.
918 * Since there is no machnism for accessing ACPI evnets
919 * and the driver currently doesn't know how to validate
920 * a mode dynamically, we have to tell BIOS don't do
921 * display switching after X has started.
922 * If LCD is on, lid close/open should still work
923 * with below settings
924 */
925 if (sd->Card.MonType1 == MT_LCD) {
926 if (sd->Card.MonType2 == MT_CRT)
927 save->bios_5_scratch = 0x0201;
928 else if (sd->Card.MonType2 == MT_DFP)
929 save->bios_5_scratch = 0x0801;
930 else
931 save->bios_5_scratch = sd->poweron_state->bios_5_scratch;
932 } else {
933 if (sd->Card.MonType2 == MT_CRT)
934 save->bios_5_scratch = 0x0200;
935 else if (sd->Card.MonType2 == MT_DFP)
936 save->bios_5_scratch = 0x0800;
937 else
938 save->bios_5_scratch = 0x0;
939 }
940 save->bios_4_scratch = 0x4;
941 save->bios_6_scratch = sd->poweron_state->bios_6_scratch | 0x40000000;
942 }
943
944 save->fp_crtc_h_total_disp = save->crtc_h_total_disp;
945 save->fp_crtc_v_total_disp = save->crtc_v_total_disp;
946 save->fp_h_sync_strt_wid = save->crtc_h_sync_strt_wid;
947 save->fp_v_sync_strt_wid = save->crtc_v_sync_strt_wid;
948 }
949
950 static void RADEONInitPLLRegisters(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
951 {
952 double freq = mode->pixelc/10.0;
953
954 struct {
955 int divider;
956 int bitvalue;
957 } *post_div, post_divs[] = {
958 /* From RAGE 128 VR/RAGE 128 GL Register
959 * Reference Manual (Technical Reference
960 * Manual P/N RRG-G04100-C Rev. 0.04), page
961 * 3-17 (PLL_DIV_[3:0]).
962 */
963 { 1, 0 }, /* VCLK_SRC */
964 { 2, 1 }, /* VCLK_SRC/2 */
965 { 4, 2 }, /* VCLK_SRC/4 */
966 { 8, 3 }, /* VCLK_SRC/8 */
967 { 3, 4 }, /* VCLK_SRC/3 */
968 { 16, 5 }, /* VCLK_SRC/16 */
969 { 6, 6 }, /* VCLK_SRC/6 */
970 { 12, 7 }, /* VCLK_SRC/12 */
971 { 0, 0 }
972 };
973
974 if (freq > sd->Card.pll.max_pll_freq) freq = sd->Card.pll.max_pll_freq;
975 if (freq * 12 < sd->Card.pll.min_pll_freq) freq = sd->Card.pll.min_pll_freq / 12;
976
977 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
978 save->pll_output_freq = post_div->divider * freq;
979
980 if (save->pll_output_freq >= sd->Card.pll.min_pll_freq
981 && save->pll_output_freq <= sd->Card.pll.max_pll_freq) break;
982 }
983
984 if (!post_div->divider) {
985 save->pll_output_freq = freq;
986 post_div = &post_divs[0];
987 }
988
989 save->dot_clock_freq = freq;
990 save->feedback_div = RADEONDiv(sd->Card.pll.reference_div
991 * save->pll_output_freq,
992 sd->Card.pll.reference_freq);
993 save->post_div = post_div->divider;
994
995 D(bug("[ATI] dc=%d, of=%d, fd=%d, pd=%d\n",
996 save->dot_clock_freq,
997 save->pll_output_freq,
998 save->feedback_div,
999 save->post_div));
1000
1001 save->ppll_ref_div = sd->Card.pll.reference_div;
1002 save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16));
1003 save->htotal_cntl = 0;
1004 }
1005
1006 /* Define PLL2 registers for requested video mode */
1007 static void RADEONInitPLL2Registers(struct ati_staticdata *sd, struct CardState *save, RADEONModeInfo *mode)
1008 {
1009 double freq = mode->pixelc/10.0;
1010
1011 struct {
1012 int divider;
1013 int bitvalue;
1014 } *post_div, post_divs[] = {
1015 /* From RAGE 128 VR/RAGE 128 GL Register
1016 * Reference Manual (Technical Reference
1017 * Manual P/N RRG-G04100-C Rev. 0.04), page
1018 * 3-17 (PLL_DIV_[3:0]).
1019 */
1020 { 1, 0 }, /* VCLK_SRC */
1021 { 2, 1 }, /* VCLK_SRC/2 */
1022 { 4, 2 }, /* VCLK_SRC/4 */
1023 { 8, 3 }, /* VCLK_SRC/8 */
1024 { 3, 4 }, /* VCLK_SRC/3 */
1025 { 6, 6 }, /* VCLK_SRC/6 */
1026 { 12, 7 }, /* VCLK_SRC/12 */
1027 { 0, 0 }
1028 };
1029
1030 if (freq > sd->Card.pll.max_pll_freq) freq = sd->Card.pll.max_pll_freq;
1031 if (freq * 12 < sd->Card.pll.min_pll_freq) freq = sd->Card.pll.min_pll_freq / 12;
1032
1033 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1034 save->pll_output_freq_2 = post_div->divider * freq;
1035 if (save->pll_output_freq_2 >= sd->Card.pll.min_pll_freq
1036 && save->pll_output_freq_2 <= sd->Card.pll.max_pll_freq) break;
1037 }
1038
1039 if (!post_div->divider) {
1040 save->pll_output_freq_2 = freq;
1041 post_div = &post_divs[0];
1042 }
1043
1044 save->dot_clock_freq_2 = freq;
1045 save->feedback_div_2 = RADEONDiv(sd->Card.pll.reference_div
1046 * save->pll_output_freq_2,
1047 sd->Card.pll.reference_freq);
1048 save->post_div_2 = post_div->divider;
1049
1050 D(bug("[ATI] dc=%d, of=%d, fd=%d, pd=%d\n",
1051 save->dot_clock_freq_2,
1052 save->pll_output_freq_2,
1053 save->feedback_div_2,
1054 save->post_div_2));
1055
1056 save->p2pll_ref_div = sd->Card.pll.reference_div;
1057 save->p2pll_div_0 = (save->feedback_div_2 |
1058 (post_div->bitvalue << 16));
1059 save->htotal_cntl2 = 0;
1060 }
1061
1062 static void RADEONGetVRamType(struct ati_staticdata *sd)
1063 {
1064 ULONG tmp;
1065
1066 if (sd->Card.IsIGP || (sd->Card.Type >= R300) ||
1067 (INREG(RADEON_MEM_SDRAM_MODE_REG) & (1<<30)))
1068 sd->Card.IsDDR = TRUE;
1069 else
1070 sd->Card.IsDDR = FALSE;
1071
1072 tmp = INREG(RADEON_MEM_CNTL);
1073 if (IS_R300_VARIANT) {
1074 tmp &= R300_MEM_NUM_CHANNELS_MASK;
1075 switch (tmp) {
1076 case 0: sd->Card.RamWidth = 64; break;
1077 case 1: sd->Card.RamWidth = 128; break;
1078 case 2: sd->Card.RamWidth = 256; break;
1079 default: sd->Card.RamWidth = 128; break;
1080 }
1081 } else if ((sd->Card.Type == RV100) ||
1082 (sd->Card.Type == RS100) ||
1083 (sd->Card.Type == RS200)){
1084 if (tmp & RV100_HALF_MODE) sd->Card.RamWidth = 32;
1085 else sd->Card.RamWidth = 64;
1086 } else {
1087 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) sd->Card.RamWidth = 128;
1088 else sd->Card.RamWidth = 64;
1089 }
1090
1091 /* This may not be correct, as some cards can have half of channel disabled
1092 * ToDo: identify these cases
1093 */
1094 }
1095
1096 struct RADEONInt10Save {
1097 ULONG MEM_CNTL;
1098 ULONG MEMSIZE;
1099 ULONG MPP_TB_CONFIG;
1100 };
1101
1102 static void RADEONPreInt10Save(struct ati_staticdata *sd, void **pPtr)
1103 {
1104 ULONG CardTmp;
1105 static struct RADEONInt10Save SaveStruct = { 0, 0, 0 };
1106
1107 /* Save the values and zap MEM_CNTL */
1108 SaveStruct.MEM_CNTL = INREG(RADEON_MEM_CNTL);
1109 SaveStruct.MEMSIZE = INREG(RADEON_CONFIG_MEMSIZE);
1110 SaveStruct.MPP_TB_CONFIG = INREG(RADEON_MPP_TB_CONFIG);
1111
1112 /*
1113 * Zap MEM_CNTL and set MPP_TB_CONFIG<31:24> to 4
1114 */
1115 OUTREG(RADEON_MEM_CNTL, 0);
1116 CardTmp = SaveStruct.MPP_TB_CONFIG & 0x00ffffffu;
1117 CardTmp |= 0x04 << 24;
1118 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
1119
1120 *pPtr = (void *)&SaveStruct;
1121 }
1122
1123 static void RADEONPostInt10Check(struct ati_staticdata *sd, void *ptr)
1124 {
1125 struct RADEONInt10Save *pSave = ptr;
1126 ULONG CardTmp;
1127
1128 /* If we don't have a valid (non-zero) saved MEM_CNTL, get out now */
1129 if (!pSave || !pSave->MEM_CNTL)
1130 return;
1131
1132 /*
1133 * If either MEM_CNTL is currently zero or inconistent (configured for
1134 * two channels with the two channels configured differently), restore
1135 * the saved registers.
1136 */
1137 CardTmp = INREG(RADEON_MEM_CNTL);
1138 if (!CardTmp ||
1139 ((CardTmp & 1) &&
1140 (((CardTmp >> 8) & 0xff) != ((CardTmp >> 24) & 0xff)))) {
1141 /* Restore the saved registers */
1142 D(bug("[ATI] Restoring MEM_CNTL (%08lx), setting to %08lx\n",
1143 (unsigned long)CardTmp, (unsigned long)pSave->MEM_CNTL));
1144 OUTREG(RADEON_MEM_CNTL, pSave->MEM_CNTL);
1145
1146 CardTmp = INREG(RADEON_CONFIG_MEMSIZE);
1147 if (CardTmp != pSave->MEMSIZE) {
1148 D(bug("[ATI] Restoring CONFIG_MEMSIZE (%08lx), setting to %08lx\n",
1149 (unsigned long)CardTmp, (unsigned long)pSave->MEMSIZE));
1150 OUTREG(RADEON_CONFIG_MEMSIZE, pSave->MEMSIZE);
1151 }
1152 }
1153
1154 CardTmp = INREG(RADEON_MPP_TB_CONFIG);
1155 if ((CardTmp & 0xff000000u) != (pSave->MPP_TB_CONFIG & 0xff000000u)) {
1156 D(bug("[ATI] Restoring MPP_TB_CONFIG<31:24> (%02lx), setting to %02lx\n",
1157 (unsigned long)CardTmp >> 24,
1158 (unsigned long)pSave->MPP_TB_CONFIG >> 24));
1159 CardTmp &= 0x00ffffffu;
1160 CardTmp |= (pSave->MPP_TB_CONFIG & 0xff000000u);
1161 OUTREG(RADEON_MPP_TB_CONFIG, CardTmp);
1162 }
1163 }
1164
1165 static void RADEONGetPanelInfo(struct ati_staticdata *sd)
1166 {
1167 }
1168
1169 static void RADEONGetClockInfo(struct ati_staticdata *sd)
1170 {
1171 RADEONPLLRec *pll = &sd->Card.pll;
1172 double min_dotclock;
1173
1174 if (RADEONGetClockInfoFromBIOS(sd)) {
1175 if (pll->reference_div < 2) {
1176 /* retrive it from register setting for fitting into current PLL algorithm.
1177 We'll probably need a new routine to calculate the best ref_div from BIOS
1178 provided min_input_pll and max_input_pll
1179 */
1180 ULONG tmp;
1181 tmp = RADEONINPLL(sd, RADEON_PPLL_REF_DIV);
1182 if (IS_R300_VARIANT ||
1183 (sd->Card.Type == RS300)) {
1184 pll->reference_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
1185 } else {
1186 pll->reference_div = tmp & RADEON_PPLL_REF_DIV_MASK;
1187 }
1188
1189 if (pll->reference_div < 2) pll->reference_div = 12;
1190 }
1191
1192 } else {
1193 D(bug("[ATI] Video BIOS not detected, using default clock settings!\n"));
1194
1195 if (sd->Card.IsIGP)
1196 pll->reference_freq = 1432;
1197 else
1198 pll->reference_freq = 2700;
1199
1200 pll->reference_div = 12;
1201 pll->min_pll_freq = 12500;
1202 pll->max_pll_freq = 35000;
1203 pll->xclk = 10300;
1204
1205 sd->Card.sclk = 200.00;
1206 sd->Card.mclk = 200.00;
1207 }
1208
1209 D(bug("[ATI] PLL parameters: rf=%d rd=%d min=%ld max=%ld; xclk=%d\n",
1210 pll->reference_freq,
1211 pll->reference_div,
1212 pll->min_pll_freq, pll->max_pll_freq, pll->xclk));
1213 }
1214
1215 BOOL HIDD_I2C_ProbeAddress(OOP_Object *obj, UWORD address);
1216
1217 #undef HiddI2CDeviceAttrBase
1218 #undef HiddI2CAttrBase
1219 #define HiddI2CDeviceAttrBase (sd->i2cDeviceAttrBase)
1220 #define HiddI2CAttrBase (sd->i2cAttrBase)
1221
1222 RADEONMonitorType RADEONDisplayDDCConnected(struct ati_staticdata *sd, RADEONDDCType type, RADEONConnector *port)
1223 {
1224 OOP_Object *i2c;
1225 RADEONMonitorType montyp = MT_NONE;
1226
1227 D(bug("[ATI] Probing monitor type\n"));
1228
1229 switch (type)
1230 {
1231 case DDC_MONID:
1232 sd->Card.DDCReg = RADEON_GPIO_MONID;
1233 break;
1234
1235 case DDC_DVI:
1236 sd->Card.DDCReg = RADEON_GPIO_DVI_DDC;
1237 break;
1238
1239 case DDC_VGA:
1240 sd->Card.DDCReg = RADEON_GPIO_VGA_DDC;
1241 break;
1242
1243 case DDC_CRT2:
1244 sd->Card.DDCReg = RADEON_GPIO_CRT2_DDC;
1245 break;
1246
1247 default:
1248 return MT_NONE;
1249 }
1250
1251 i2c = OOP_NewObject(sd->AtiI2C, NULL, NULL);
1252
1253 if (HIDD_I2C_ProbeAddress(i2c, 0xa0))
1254 {
1255 char edid[128];
1256 char wb[2] = {0, 0};
1257
1258 struct TagItem attrs[] = {
1259 { aHidd_I2CDevice_Driver, (IPTR)i2c },
1260 { aHidd_I2CDevice_Address, 0xa0 },
1261 { aHidd_I2CDevice_Name, (IPTR)"Display" },
1262 { TAG_DONE, 0UL }
1263 };
1264
1265 D(bug("[ATI] I2C device found\n"));
1266
1267 OOP_Object *obj = OOP_NewObject(NULL, CLID_Hidd_I2CDevice, attrs);
1268
1269 if (obj)
1270 {
1271 D(bug("[ATI] I2C Device @ %p\n", obj));
1272
1273 struct pHidd_I2CDevice_WriteRead msg;
1274
1275 msg.mID = OOP_GetMethodID((STRPTR)IID_Hidd_I2CDevice, moHidd_I2CDevice_WriteRead);
1276 msg.readBuffer = &edid[0];
1277 msg.readLength = 128;
1278 msg.writeBuffer = &wb[0];
1279 msg.writeLength = 1;
1280
1281 OOP_DoMethod(obj, &msg.mID);
1282
1283 int i;
1284
1285 D(bug("[ATI] DDC1 Dump:\n[ATI] "));
1286 for (i=0; i < 128; i++)
1287 {
1288 D(bug("%02x ", edid[i]));
1289
1290 if (i % 20 == 19)
1291 D(bug("\n[ATI] "));
1292 }
1293 D(bug("\n"));
1294
1295 OOP_DisposeObject(obj);
1296
1297 if (edid[0x14] & 0x80) {
1298 /* Note some laptops have a DVI output that uses internal TMDS,
1299 * when its DVI is enabled by hotkey, LVDS panel is not used.
1300 * In this case, the laptop is configured as DVI+VGA as a normal
1301 * desktop card.
1302 * Also for laptop, when X starts with lid closed (no DVI connection)
1303 * both LDVS and TMDS are disable, we still need to treat it as a LVDS panel.
1304 */
1305 if (port->TMDSType == TMDS_EXT) montyp = MT_DFP;
1306 else {
1307 if ((INREG(RADEON_FP_GEN_CNTL) & (1<<7)) || !sd->Card.IsMobility)
1308 montyp = MT_DFP;
1309 else
1310 montyp = MT_LCD;
1311 }
1312 } else montyp = MT_CRT;
1313 }
1314 }
1315
1316 OOP_DisposeObject(i2c);
1317
1318 return montyp;
1319 }
1320
1321 static BOOL RADEONQueryConnectedMonitors(struct ati_staticdata *sd)
1322 {
1323 const char *s;
1324 BOOL ignore_edid = TRUE;
1325 int i = 0, second = 0, max_mt;
1326
1327 const char *MonTypeName[7] =
1328 {
1329 "AUTO",
1330 "NONE",
1331 "CRT",
1332 "LVDS",
1333 "TMDS",
1334 "CTV",
1335 "STV"
1336 };
1337
1338 const RADEONMonitorType MonTypeID[7] =
1339 {
1340 MT_UNKNOWN, /* this is just a dummy value for AUTO DETECTION */
1341 MT_NONE, /* NONE -> NONE */
1342 MT_CRT, /* CRT -> CRT */
1343 MT_LCD, /* Laptop LCDs are driven via LVDS port */
1344 MT_DFP, /* DFPs are driven via TMDS */
1345 MT_CTV, /* CTV -> CTV */
1346 MT_STV, /* STV -> STV */
1347 };
1348
1349 const char *TMDSTypeName[3] =
1350 {
1351 "NONE",
1352 "Internal",
1353 "External"
1354 };
1355
1356 const char *DDCTypeName[5] =
1357 {
1358 "NONE",
1359 "MONID",
1360 "DVI_DDC",
1361 "VGA_DDC",
1362 "CRT2_DDC"
1363 };
1364
1365 const char *DACTypeName[3] =
1366 {
1367 "Unknown",
1368 "Primary",
1369 "TVDAC/ExtDAC",
1370 };
1371
1372 const char *ConnectorTypeName[8] =
1373 {
1374 "None",
1375 "Proprietary",
1376 "VGA",
1377 "DVI-I",
1378 "DVI-D",
1379 "CTV",
1380 "STV",
1381 "Unsupported"
1382 };
1383
1384 const char *ConnectorTypeNameATOM[10] =
1385 {
1386 "None",
1387 "VGA",
1388 "DVI-I",
1389 "DVI-D",
1390 "DVI-A",
1391 "STV",
1392 "CTV",
1393 "LVDS",
1394 "Digital",
1395 "Unsupported"
1396 };
1397
1398 max_mt = 5;
1399
1400 /*
1401 if(info->IsSecondary) {
1402 info->DisplayType = (RADEONMonitorType)pRADEONEnt->MonType2;
1403 if(info->DisplayType == MT_NONE) return FALSE;
1404 return TRUE;
1405 }
1406 */
1407
1408 /* We first get the information about all connectors from BIOS.
1409 * This is how the card is phyiscally wired up.
1410 * The information should be correct even on a OEM card.
1411 * If not, we may have problem -- need to use MonitorLayout option.
1412 */
1413 for (i = 0; i < 2; i++) {
1414 sd->Card.PortInfo[i].MonType = MT_UNKNOWN;
1415 // sd->Card.PortInfo[i].MonInfo = NULL;
1416 sd->Card.PortInfo[i].DDCType = DDC_NONE_DETECTED;
1417 sd->Card.PortInfo[i].DACType = DAC_UNKNOWN;
1418 sd->Card.PortInfo[i].TMDSType = TMDS_UNKNOWN;
1419 sd->Card.PortInfo[i].ConnectorType = CONNECTOR_NONE;
1420 }
1421
1422 if (!RADEONGetConnectorInfoFromBIOS(sd)) {
1423 /* Below is the most common setting, but may not be true */
1424 sd->Card.PortInfo[0].MonType = MT_UNKNOWN;
1425 // sd->Card.PortInfo[0].MonInfo = NULL;
1426 sd->Card.PortInfo[0].DDCType = DDC_DVI;
1427 sd->Card.PortInfo[0].DACType = DAC_TVDAC;
1428 sd->Card.PortInfo[0].TMDSType = TMDS_INT;
1429 sd->Card.PortInfo[0].ConnectorType = CONNECTOR_DVI_D;
1430
1431 sd->Card.PortInfo[1].MonType = MT_UNKNOWN;
1432 // sd->Card.PortInfo[1].MonInfo = NULL;
1433 sd->Card.PortInfo[1].DDCType = DDC_VGA;
1434 sd->Card.PortInfo[1].DACType = DAC_PRIMARY;
1435 sd->Card.PortInfo[1].TMDSType = TMDS_EXT;
1436 sd->Card.PortInfo[1].ConnectorType = CONNECTOR_CRT;
1437 }
1438
1439 /* always make TMDS_INT port first*/
1440 if (sd->Card.PortInfo[1].TMDSType == TMDS_INT) {
1441 RADEONConnector connector;
1442 connector = sd->Card.PortInfo[0];
1443 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1444 sd->Card.PortInfo[1] = connector;
1445 } else if ((sd->Card.PortInfo[0].TMDSType != TMDS_INT &&
1446 sd->Card.PortInfo[1].TMDSType != TMDS_INT)) {
1447 /* no TMDS_INT port, make primary DAC port first */
1448 if (sd->Card.PortInfo[1].DACType == DAC_PRIMARY) {
1449 RADEONConnector connector;
1450 connector = sd->Card.PortInfo[0];
1451 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1452 sd->Card.PortInfo[1] = connector;
1453 }
1454 }
1455
1456 if (sd->Card.HasSingleDAC) {
1457 /* For RS300/RS350/RS400 chips, there is no primary DAC. Force VGA port to use TVDAC*/
1458 if (sd->Card.PortInfo[0].ConnectorType == CONNECTOR_CRT) {
1459 sd->Card.PortInfo[0].DACType = DAC_TVDAC;
1460 sd->Card.PortInfo[1].DACType = DAC_PRIMARY;
1461 } else {
1462 sd->Card.PortInfo[1].DACType = DAC_TVDAC;
1463 sd->Card.PortInfo[0].DACType = DAC_PRIMARY;
1464 }
1465 } else if (!sd->Card.HasCRTC2) {
1466 sd->Card.PortInfo[0].DACType = DAC_PRIMARY;
1467 }
1468
1469 if(((!sd->Card.HasCRTC2) || sd->Card.IsDellServer)) {
1470 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN) {
1471 if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[0])));
1472 else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[0])));
1473 else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[0])));
1474 else
1475 sd->Card.PortInfo[0].MonType = MT_CRT;
1476 }
1477
1478 sd->Card.MonType1 = sd->Card.PortInfo[0].MonType;
1479 // pRADEONEnt->MonInfo1 = sd->Card.PortInfo[0]. .MonInfo;
1480 sd->Card.MonType2 = MT_NONE;
1481 // pRADEONEnt->MonInfo2 = NULL;
1482
1483 D(bug("[ATI] Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1484 MonTypeName[sd->Card.PortInfo[0].MonType+1],
1485 sd->Card.IsAtomBios ?
1486 ConnectorTypeNameATOM[sd->Card.PortInfo[0].ConnectorType]:
1487 ConnectorTypeName[sd->Card.PortInfo[0].ConnectorType],
1488 DACTypeName[sd->Card.PortInfo[0].DACType+1],
1489 TMDSTypeName[sd->Card.PortInfo[0].TMDSType+1],
1490 DDCTypeName[sd->Card.PortInfo[0].DDCType]));
1491
1492 return TRUE;
1493 }
1494
1495 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN || sd->Card.PortInfo[1].MonType == MT_UNKNOWN) {
1496
1497 /* Primary Head (DVI or Laptop Int. panel)*/
1498 /* A ddc capable display connected on DVI port */
1499 if (sd->Card.PortInfo[0].MonType == MT_UNKNOWN) {
1500 if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, sd->Card.PortInfo[0].DDCType, &sd->Card.PortInfo[0])));
1501 else
1502 // if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[0])));
1503 // else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[0])));
1504 // else if((sd->Card.PortInfo[0].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[0])));
1505 // else
1506 if (sd->Card.IsMobility &&
1507 (INREG(RADEON_BIOS_4_SCRATCH) & 4)) {
1508 /* non-DDC laptop panel connected on primary */
1509 sd->Card.PortInfo[0].MonType = MT_LCD;
1510 } else {
1511 /* CRT on DVI, TODO: not reliable, make it always return false for now*/
1512 // sd->Card.PortInfo[0].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[0].DACType));
1513 }
1514 }
1515
1516 /* Secondary Head (mostly VGA, can be DVI on some OEM boards)*/
1517 if (sd->Card.PortInfo[1].MonType == MT_UNKNOWN) {
1518 if((sd->Card.PortInfo[1].MonType =
1519 RADEONDisplayDDCConnected(sd, sd->Card.PortInfo[1].DDCType, &sd->Card.PortInfo[1])));
1520 else
1521 // if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_DVI, &sd->Card.PortInfo[1])));
1522 // else if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_VGA, &sd->Card.PortInfo[1])));
1523 // else if((sd->Card.PortInfo[1].MonType = RADEONDisplayDDCConnected(sd, DDC_CRT2, &sd->Card.PortInfo[1])));
1524 // else
1525 if (sd->Card.IsMobility &&
1526 (INREG(RADEON_FP2_GEN_CNTL) & RADEON_FP2_ON)) {
1527 /* non-DDC TMDS panel connected through DVO */
1528 sd->Card.PortInfo[1].MonType = MT_DFP;
1529 }
1530 //else
1531 // sd->Card.PortInfo[1].MonType = RADEONCrtIsPhysicallyConnected(pScrn, !(pRADEONEnt->PortInfo[1].DACType));
1532
1533 }
1534 }
1535
1536 sd->Card.MonType1 = sd->Card.PortInfo[0].MonType;
1537 sd->Card.MonType2 = sd->Card.PortInfo[1].MonType;
1538 if (sd->Card.PortInfo[0].MonType == MT_NONE) {
1539 if (sd->Card.PortInfo[1].MonType == MT_NONE) {
1540 sd->Card.MonType1 = MT_CRT;
1541 } else {
1542 RADEONConnector tmp;
1543 sd->Card.MonType1 = sd->Card.PortInfo[1].MonType;
1544 tmp = sd->Card.PortInfo[0];
1545 sd->Card.PortInfo[0] = sd->Card.PortInfo[1];
1546 sd->Card.PortInfo[1] = tmp;
1547 }
1548 sd->Card.MonType2 = MT_NONE;
1549 }
1550 sd->Card.ReversedDAC = FALSE;
1551 sd->Card.OverlayOnCRTC2 = FALSE;
1552
1553 if (sd->Card.MonType2 != MT_NONE) {
1554
1555 if (sd->Card.PortInfo[1].DACType == DAC_TVDAC) {
1556 D(bug("[ATI] Reversed DAC decteced\n"));
1557 sd->Card.ReversedDAC = TRUE;
1558 }
1559 } else {
1560 sd->Card.HasSecondary = FALSE;
1561 }
1562 D(bug("[ATI] Primary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1563 MonTypeName[sd->Card.PortInfo[0].MonType+1],
1564 sd->Card.IsAtomBios ?
1565 ConnectorTypeNameATOM[sd->Card.PortInfo[0].ConnectorType]:
1566 ConnectorTypeName[sd->Card.PortInfo[0].ConnectorType],
1567 DACTypeName[sd->Card.PortInfo[0].DACType+1],
1568 TMDSTypeName[sd->Card.PortInfo[0].TMDSType+1],
1569 DDCTypeName[sd->Card.PortInfo[0].DDCType]));
1570
1571 D(bug("[ATI] Secondary:\n Monitor -- %s\n Connector -- %s\n DAC Type -- %s\n TMDS Type -- %s\n DDC Type -- %s\n",
1572 MonTypeName[sd->Card.PortInfo[1].MonType+1],
1573 sd->Card.IsAtomBios ?
1574 ConnectorTypeNameATOM[sd->Card.PortInfo[1].ConnectorType]:
1575 ConnectorTypeName[sd->Card.PortInfo[1].ConnectorType],
1576 DACTypeName[sd->Card.PortInfo[1].DACType+1],
1577 TMDSTypeName[sd->Card.PortInfo[1].TMDSType+1],
1578 DDCTypeName[sd->Card.PortInfo[1].DDCType]));
1579
1580 return TRUE;
1581 }
1582
1583
1584
1585
1586 /*
1587 * Accesible functions
1588 */
1589
1590 void InitMode(struct ati_staticdata *sd, struct CardState *save,
1591 ULONG width, ULONG height, UBYTE bpp, ULONG pixelc, IPTR base,
1592 ULONG HDisplay, ULONG VDisplay,
1593 ULONG HSyncStart, ULONG HSyncEnd, ULONG HTotal,
1594 ULONG VSyncStart, ULONG VSyncEnd, ULONG VTotal)
1595 {
1596 RADEONModeInfo info = {
1597 width, height, bpp, pixelc, base,
1598 HDisplay, VDisplay, HSyncStart, HSyncEnd, HTotal,
1599 VSyncStart, VSyncEnd, VTotal };
1600
1601 RADEONInitCommonRegisters(sd, save, &info);
1602
1603 if (sd->Card.IsSecondary)
1604 {
1605 RADEONInitCrtc2Registers(sd, save, &info);
1606 RADEONInitPLL2Registers(sd, save, &info);
1607 }
1608 else
1609 {
1610 RADEONInitCrtcRegisters(sd, save, &info);
1611 RADEONInitPLLRegisters(sd, save, &info);
1612 }
1613 RADEONInitFPRegisters(sd, save, &info);
1614
1615 save->pixelc = info.pixelc;
1616 save->HDisplay = info.HDisplay;
1617 }
1618
1619 void ShowHideCursor(struct ati_staticdata *sd, BOOL visible)
1620 {
1621 D(bug("[ATI] ShowHideCursor: %s\n", visible ? "show":"hide"));
1622
1623 if (visible)
1624 {
1625 if (sd->Card.IsSecondary)
1626 OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_CUR_EN, ~RADEON_CRTC2_CUR_EN);
1627 else
1628 OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_CUR_EN, ~RADEON_CRTC_CUR_EN);
1629 }
1630 else
1631 {
1632 if (sd->Card.IsSecondary)
1633 OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_CUR_EN);
1634 else
1635 OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_CUR_EN);
1636 }
1637 }
1638
1639 void SaveState(struct ati_staticdata *sd, struct CardState *save)
1640 {
1641 save->dp_datatype = INREG(RADEON_DP_DATATYPE);
1642 save->rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
1643 save->clock_cntl_index = INREG(RADEON_CLOCK_CNTL_INDEX);
1644 if (sd->Card.R300CGWorkaround) R300CGWorkaround(sd);
1645
1646 // Common registers
1647 save->ovr_clr = INREG(RADEON_OVR_CLR);
1648 save->ovr_wid_left_right = INREG(RADEON_OVR_WID_LEFT_RIGHT);
1649 save->ovr_wid_top_bottom = INREG(RADEON_OVR_WID_TOP_BOTTOM);
1650 save->ov0_scale_cntl = INREG(RADEON_OV0_SCALE_CNTL);
1651 save->subpic_cntl = INREG(RADEON_SUBPIC_CNTL);
1652 save->viph_control = INREG(RADEON_VIPH_CONTROL);
1653 save->i2c_cntl_1 = INREG(RADEON_I2C_CNTL_1);
1654 save->gen_int_cntl = INREG(RADEON_GEN_INT_CNTL);
1655 save->cap0_trig_cntl = INREG(RADEON_CAP0_TRIG_CNTL);
1656 save->cap1_trig_cntl = INREG(RADEON_CAP1_TRIG_CNTL);
1657 save->bus_cntl = INREG(RADEON_BUS_CNTL);
1658 save->surface_cntl = INREG(RADEON_SURFACE_CNTL);
1659 save->grph_buffer_cntl = INREG(RADEON_GRPH_BUFFER_CNTL);
1660 save->grph2_buffer_cntl = INREG(RADEON_GRPH2_BUFFER_CNTL);
1661
1662 if (!sd->Card.IsSecondary)
1663 {
1664 // PLL
1665 save->ppll_ref_div = RADEONINPLL(sd, RADEON_PPLL_REF_DIV);
1666 save->ppll_div_3 = RADEONINPLL(sd, RADEON_PPLL_DIV_3);
1667 save->htotal_cntl = RADEONINPLL(sd, RADEON_HTOTAL_CNTL);
1668
1669 // CRTC
1670 save->crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL);
1671 save->crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL);
1672 save->dac_cntl = INREG(RADEON_DAC_CNTL);
1673 save->crtc_h_total_disp = INREG(RADEON_CRTC_H_TOTAL_DISP);
1674 save->crtc_h_sync_strt_wid = INREG(RADEON_CRTC_H_SYNC_STRT_WID);
1675 save->crtc_v_total_disp = INREG(RADEON_CRTC_V_TOTAL_DISP);
1676 save->crtc_v_sync_strt_wid = INREG(RADEON_CRTC_V_SYNC_STRT_WID);
1677 save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
1678 save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
1679 save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
1680 save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
1681 save->crtc_more_cntl = INREG(RADEON_CRTC_MORE_CNTL);
1682
1683 if (sd->Card.IsDellServer) {
1684 save->tv_dac_cntl = INREG(RADEON_TV_DAC_CNTL);
1685 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
1686 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
1687 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
1688 }
1689
1690 // Flat panel
1691 save->fp_crtc_h_total_disp = INREG(RADEON_FP_CRTC_H_TOTAL_DISP);
1692 save->fp_crtc_v_total_disp = INREG(RADEON_FP_CRTC_V_TOTAL_DISP);
1693 save->fp_gen_cntl = INREG(RADEON_FP_GEN_CNTL);
1694 save->fp_h_sync_strt_wid = INREG(RADEON_FP_H_SYNC_STRT_WID);
1695 save->fp_horz_stretch = INREG(RADEON_FP_HORZ_STRETCH);
1696 save->fp_v_sync_strt_wid = INREG(RADEON_FP_V_SYNC_STRT_WID);
1697 save->fp_vert_stretch = INREG(RADEON_FP_VERT_STRETCH);
1698 save->lvds_gen_cntl = INREG(RADEON_LVDS_GEN_CNTL);
1699 save->lvds_pll_cntl = INREG(RADEON_LVDS_PLL_CNTL);
1700 save->tmds_pll_cntl = INREG(RADEON_TMDS_PLL_CNTL);
1701 save->tmds_transmitter_cntl= INREG(RADEON_TMDS_TRANSMITTER_CNTL);
1702 save->bios_4_scratch = INREG(RADEON_BIOS_4_SCRATCH);
1703 save->bios_5_scratch = INREG(RADEON_BIOS_5_SCRATCH);
1704 save->bios_6_scratch = INREG(RADEON_BIOS_6_SCRATCH);
1705
1706 if (sd->Card.Type == RV280) {
1707 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
1708 save->tmds_pll_cntl ^= (1 << 22);
1709 }
1710 }
1711 else
1712 {
1713 // CRTC2
1714 save->dac2_cntl = INREG(RADEON_DAC_CNTL2);
1715 save->disp_output_cntl = INREG(RADEON_DISP_OUTPUT_CNTL);
1716 save->disp_hw_debug = INREG (RADEON_DISP_HW_DEBUG);
1717
1718 save->crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL);
1719 save->crtc2_h_total_disp = INREG(RADEON_CRTC2_H_TOTAL_DISP);
1720 save->crtc2_h_sync_strt_wid = INREG(RADEON_CRTC2_H_SYNC_STRT_WID);
1721 save->crtc2_v_total_disp = INREG(RADEON_CRTC2_V_TOTAL_DISP);
1722 save->crtc2_v_sync_strt_wid = INREG(RADEON_CRTC2_V_SYNC_STRT_WID);
1723 save->crtc2_offset = INREG(RADEON_CRTC2_OFFSET);
1724 save->crtc2_offset_cntl = INREG(RADEON_CRTC2_OFFSET_CNTL);
1725 save->crtc2_pitch = INREG(RADEON_CRTC2_PITCH);
1726
1727 save->fp2_h_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
1728 save->fp2_v_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
1729 save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL);
1730 save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
1731
1732 // PLL2
1733 save->p2pll_ref_div = RADEONINPLL(sd, RADEON_P2PLL_REF_DIV);
1734 save->p2pll_div_0 = RADEONINPLL(sd, RADEON_P2PLL_DIV_0);
1735 save->htotal_cntl2 = RADEONINPLL(sd, RADEON_HTOTAL2_CNTL);
1736 }
1737 }
1738
1739 /* Write common registers */
1740 static void RADEONRestoreCommonRegisters(struct ati_staticdata *sd, struct CardState *restore)
1741 {
1742 OUTREG(RADEON_OVR_CLR, restore->ovr_clr);
1743 OUTREG(RADEON_OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
1744 OUTREG(RADEON_OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
1745 OUTREG(RADEON_OV0_SCALE_CNTL, restore->ov0_scale_cntl);
1746 OUTREG(RADEON_SUBPIC_CNTL, restore->subpic_cntl);
1747 OUTREG(RADEON_VIPH_CONTROL, restore->viph_control);
1748 OUTREG(RADEON_I2C_CNTL_1, restore->i2c_cntl_1);
1749 OUTREG(RADEON_GEN_INT_CNTL, restore->gen_int_cntl);
1750 OUTREG(RADEON_CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
1751 OUTREG(RADEON_CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
1752 OUTREG(RADEON_BUS_CNTL, restore->bus_cntl);
1753 OUTREG(RADEON_SURFACE_CNTL, restore->surface_cntl);
1754 }
1755
1756 static void RADEONRestoreCrtcRegisters(struct ati_staticdata *sd, struct CardState *restore)
1757 {
1758 /* We prevent the CRTC from hitting the memory controller until
1759 * fully programmed
1760 */
1761 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl |
1762 RADEON_CRTC_DISP_REQ_EN_B);
1763
1764 OUTREGP(RADEON_CRTC_EXT_CNTL,
1765 restore->crtc_ext_cntl,
1766 RADEON_CRTC_VSYNC_DIS |
1767 RADEON_CRTC_HSYNC_DIS |
1768 RADEON_CRTC_DISPLAY_DIS);
1769
1770 OUTREGP(RADEON_DAC_CNTL,
1771 restore->dac_cntl,
1772 RADEON_DAC_RANGE_CNTL |
1773 RADEON_DAC_BLANKING);
1774
1775 OUTREG(RADEON_CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
1776 OUTREG(RADEON_CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
1777 OUTREG(RADEON_CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
1778 OUTREG(RADEON_CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
1779 OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
1780 OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
1781 OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
1782 OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
1783 OUTREG(RADEON_CRTC_MORE_CNTL, restore->crtc_more_cntl);
1784
1785 if (sd->Card.IsDellServer) {
1786 OUTREG(RADEON_TV_DAC_CNTL, restore->tv_dac_cntl);
1787 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
1788 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
1789 OUTREG(RADEON_CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);
1790 }
1791
1792 OUTREG(RADEON_CRTC_GEN_CNTL, restore->crtc_gen_cntl);
1793
1794 }
1795
1796 static void RADEONRestoreCrtc2Registers(struct ati_staticdata *sd, struct CardState *restore)
1797 {
1798 ULONG crtc2_gen_cntl;
1799
1800 crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL) &
1801 (RADEON_CRTC2_VSYNC_DIS |
1802 RADEON_CRTC2_HSYNC_DIS |
1803 RADEON_CRTC2_DISP_DIS);
1804 crtc2_gen_cntl |= restore->crtc2_gen_cntl;
1805
1806 /* We prevent the CRTC from hitting the memory controller until
1807 * fully programmed
1808 */
1809 OUTREG(RADEON_CRTC2_GEN_CNTL,
1810 crtc2_gen_cntl | RADEON_CRTC2_DISP_REQ_EN_B);
1811
1812 OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
1813
1814 OUTREG(RADEON_TV_DAC_CNTL, 0x00280203);
1815 if ((sd->Card.Type == R200) ||
1816 IS_R300_VARIANT) {
1817 OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
1818 } else {
1819 OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
1820 }
1821
1822 OUTREG(RADEON_CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
1823 OUTREG(RADEON_CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
1824 OUTREG(RADEON_CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
1825 OUTREG(RADEON_CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
1826 OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
1827 OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
1828 OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
1829 OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
1830
1831 if ((sd->Card.MonType2 == MT_DFP && sd->Card.IsSecondary))
1832 {
1833 OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid);
1834 OUTREG(RADEON_FP_V2_SYNC_STRT_WID, restore->fp2_v_sync_strt_wid);
1835 OUTREG(RADEON_FP2_GEN_CNTL, restore->fp2_gen_cntl);
1836 }
1837
1838 OUTREG(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1839 }
1840
1841 static void RADEONRestoreFPRegisters(struct ati_staticdata *sd, struct CardState *restore)
1842 {
1843 unsigned long tmp;
1844
1845 OUTREG(RADEON_FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
1846 OUTREG(RADEON_FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
1847 OUTREG(RADEON_FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
1848 OUTREG(RADEON_FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
1849 OUTREG(RADEON_TMDS_PLL_CNTL, restore->tmds_pll_cntl);
1850 OUTREG(RADEON_TMDS_TRANSMITTER_CNTL,restore->tmds_transmitter_cntl);
1851 OUTREG(RADEON_FP_HORZ_STRETCH, restore->fp_horz_stretch);
1852 OUTREG(RADEON_FP_VERT_STRETCH, restore->fp_vert_stretch);
1853 OUTREG(RADEON_FP_GEN_CNTL, restore->fp_gen_cntl);
1854
1855 /* old AIW Radeon has some BIOS initialization problem
1856 * with display buffer underflow, only occurs to DFP
1857 */
1858 if (!sd->Card.HasCRTC2)
1859 OUTREG(RADEON_GRPH_BUFFER_CNTL,
1860 INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
1861
1862 if (sd->Card.IsMobility) {
1863 OUTREG(RADEON_BIOS_4_SCRATCH, restore->bios_4_scratch);
1864 OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
1865 OUTREG(RADEON_BIOS_6_SCRATCH, restore->bios_6_scratch);
1866 }
1867
1868 if (sd->Card.MonType1 != MT_DFP) {
1869 unsigned long tmpPixclksCntl = INPLL(sd, RADEON_PIXCLKS_CNTL);
1870
1871 if (sd->Card.IsMobility || sd->Card.IsIGP) {
1872 /* Asic bug, when turning off LVDS_ON, we have to make sure
1873 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1874 */
1875 if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
1876 OUTPLLP(sd, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
1877 }
1878 }
1879
1880 tmp = INREG(RADEON_LVDS_GEN_CNTL);
1881 if ((tmp & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) ==
1882 (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON))) {
1883 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1884 } else {
1885 if (restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) {
1886 usleep(sd, sd->Card.PanelPwrDly * 1000);
1887 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1888 } else {
1889 OUTREG(RADEON_LVDS_GEN_CNTL,
1890 restore->lvds_gen_cntl | RADEON_LVDS_BLON);
1891 usleep(sd, sd->Card.PanelPwrDly * 1000);
1892 OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
1893 }
1894 }
1895
1896 if (sd->Card.IsMobility || sd->Card.IsIGP) {
1897 if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
1898 OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
1899 }
1900 }
1901 }
1902 }
1903
1904 static void RADEONPLLWaitForReadUpdateComplete(struct ati_staticdata *sd)
1905 {
1906 int i = 0;
1907
1908 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1909 the cause yet, but this workaround will mask the problem for now.
1910 Other chips usually will pass at the very first test, so the
1911 workaround shouldn't have any effect on them. */
1912 for (i = 0;
1913 (i < 10000 &&
1914 INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
1915 i++);
1916 }
1917
1918 static void RADEONPLLWriteUpdate(struct ati_staticdata *sd)
1919 {
1920 while (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
1921
1922 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
1923 RADEON_PPLL_ATOMIC_UPDATE_W,
1924 ~(RADEON_PPLL_ATOMIC_UPDATE_W));
1925 }
1926
1927 static void RADEONPLL2WaitForReadUpdateComplete(struct ati_staticdata *sd)
1928 {
1929 int i = 0;
1930
1931 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1932 the cause yet, but this workaround will mask the problem for now.
1933 Other chips usually will pass at the very first test, so the
1934 workaround shouldn't have any effect on them. */
1935 for (i = 0;
1936 (i < 10000 &&
1937 INPLL(sd, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
1938 i++);
1939 }
1940
1941 static void RADEONPLL2WriteUpdate(struct ati_staticdata *sd)
1942 {
1943 while (INPLL(sd, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
1944
1945 OUTPLLP(sd, RADEON_P2PLL_REF_DIV,
1946 RADEON_P2PLL_ATOMIC_UPDATE_W,
1947 ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
1948 }
1949
1950
1951 /* Write PLL registers */
1952 static void RADEONRestorePLLRegisters(struct ati_staticdata *sd, struct CardState *restore)
1953 {
1954 if (sd->Card.IsMobility) {
1955 /* A temporal workaround for the occational blanking on certain laptop panels.
1956 This appears to related to the PLL divider registers (fail to lock?).
1957 It occurs even when all dividers are the same with their old settings.
1958 In this case we really don't need to fiddle with PLL registers.
1959 By doing this we can avoid the blanking problem with some panels.
1960 */
1961 if ((restore->ppll_ref_div == (INPLL(sd, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
1962 (restore->ppll_div_3 == (INPLL(sd, RADEON_PPLL_DIV_3) &
1963 (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
1964 OUTREGP(RADEON_CLOCK_CNTL_INDEX,
1965 RADEON_PLL_DIV_SEL,
1966 ~(RADEON_PLL_DIV_SEL));
1967 RADEONPllErrataAfterIndex(sd);
1968 return;
1969 }
1970 }
1971
1972 OUTPLLP(sd, RADEON_VCLK_ECP_CNTL,
1973 RADEON_VCLK_SRC_SEL_CPUCLK,
1974 ~(RADEON_VCLK_SRC_SEL_MASK));
1975
1976 OUTPLLP(sd,
1977 RADEON_PPLL_CNTL,
1978 RADEON_PPLL_RESET
1979 | RADEON_PPLL_ATOMIC_UPDATE_EN
1980 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN,
1981 ~(RADEON_PPLL_RESET
1982 | RADEON_PPLL_ATOMIC_UPDATE_EN
1983 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
1984
1985 OUTREGP(RADEON_CLOCK_CNTL_INDEX,
1986 RADEON_PLL_DIV_SEL,
1987 ~(RADEON_PLL_DIV_SEL));
1988 RADEONPllErrataAfterIndex(sd);
1989
1990 if (IS_R300_VARIANT ||
1991 (sd->Card.Type == RS300)) {
1992 if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1993 /* When restoring console mode, use saved PPLL_REF_DIV
1994 * setting.
1995 */
1996 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
1997 restore->ppll_ref_div,
1998 0);
1999 } else {
2000 /* R300 uses ref_div_acc field as real ref divider */
2001 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
2002 (restore->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
2003 ~R300_PPLL_REF_DIV_ACC_MASK);
2004 }
2005 } else {
2006 OUTPLLP(sd, RADEON_PPLL_REF_DIV,
2007 restore->ppll_ref_div,
2008 ~RADEON_PPLL_REF_DIV_MASK);
2009 }
2010
2011 OUTPLLP(sd, RADEON_PPLL_DIV_3,
2012 restore->ppll_div_3,
2013 ~RADEON_PPLL_FB3_DIV_MASK);
2014
2015 OUTPLLP(sd, RADEON_PPLL_DIV_3,
2016 restore->ppll_div_3,
2017 ~RADEON_PPLL_POST3_DIV_MASK);
2018
2019 RADEONPLLWriteUpdate(sd);
2020 RADEONPLLWaitForReadUpdateComplete(sd);
2021
2022 OUTPLL(RADEON_HTOTAL_CNTL, restore->htotal_cntl);
2023
2024 OUTPLLP(sd, RADEON_PPLL_CNTL,
2025 0,
2026 ~(RADEON_PPLL_RESET
2027 | RADEON_PPLL_SLEEP
2028 | RADEON_PPLL_ATOMIC_UPDATE_EN
2029 | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
2030
2031 usleep(sd, 50000); /* Let the clock to lock */
2032
2033 OUTPLLP(sd, RADEON_VCLK_ECP_CNTL,
2034 RADEON_VCLK_SRC_SEL_PPLLCLK,
2035 ~(RADEON_VCLK_SRC_SEL_MASK));
2036 }
2037
2038 static void RADEONRestorePLL2Registers(struct ati_staticdata *sd, struct CardState *restore)
2039 {
2040 OUTPLLP(sd, RADEON_PIXCLKS_CNTL,
2041 RADEON_PIX2CLK_SRC_SEL_CPUCLK,
2042 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
2043
2044 OUTPLLP(sd,
2045 RADEON_P2PLL_CNTL,
2046 RADEON_P2PLL_RESET
2047 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2048 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN,
2049 ~(RADEON_P2PLL_RESET
2050 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2051 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
2052
2053 OUTPLLP(sd, RADEON_P2PLL_REF_DIV,
2054 restore->p2pll_ref_div,
2055 ~RADEON_P2PLL_REF_DIV_MASK);
2056
2057 OUTPLLP(sd, RADEON_P2PLL_DIV_0,
2058 restore->p2pll_div_0,
2059 ~RADEON_P2PLL_FB0_DIV_MASK);
2060
2061 OUTPLLP(sd, RADEON_P2PLL_DIV_0,
2062 restore->p2pll_div_0,
2063 ~RADEON_P2PLL_POST0_DIV_MASK);
2064
2065 RADEONPLL2WriteUpdate(sd);
2066 RADEONPLL2WaitForReadUpdateComplete(sd);
2067
2068 OUTPLL(RADEON_HTOTAL2_CNTL, restore->htotal_cntl2);
2069
2070 OUTPLLP(sd, RADEON_P2PLL_CNTL,
2071 0,
2072 ~(RADEON_P2PLL_RESET
2073 | RADEON_P2PLL_SLEEP
2074 | RADEON_P2PLL_ATOMIC_UPDATE_EN
2075 | RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN));
2076
2077 usleep(sd, 5000); /* Let the clock to lock */
2078
2079 OUTPLLP(sd, RADEON_PIXCLKS_CNTL,
2080 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
2081 ~(RADEON_PIX2CLK_SRC_SEL_MASK));
2082 }
2083
2084 void LoadState(struct ati_staticdata *sd, struct CardState *restore)
2085 {
2086 RADEONBlank(sd);
2087
2088 /* For Non-dual head card, we don't have private field in the Entity */
2089 if (!sd->Card.HasCRTC2) {
2090 RADEONRestoreCommonRegisters(sd, restore);
2091 RADEONRestoreCrtcRegisters(sd, restore);
2092 RADEONRestoreFPRegisters(sd, restore);
2093 RADEONRestorePLLRegisters(sd, restore);
2094
2095 RADEONUnblank(sd);
2096
2097 RADEONInitDispBandwidth(sd, restore);
2098
2099 SetGamma(sd, 1.0, 1.0, 1.0);
2100
2101 return;
2102 }
2103
2104 if (sd->Card.IsSecondary) {
2105 RADEONRestoreCommonRegisters(sd, restore);
2106 RADEONRestoreCrtc2Registers(sd, restore);
2107 RADEONRestorePLL2Registers(sd, restore);
2108 }
2109 else
2110 {
2111 RADEONRestoreCommonRegisters(sd, restore);
2112
2113 if (!sd->Card.HasSecondary) {
2114 RADEONRestoreCrtcRegisters(sd, restore);
2115 RADEONRestoreFPRegisters(sd, restore);
2116 RADEONRestorePLLRegisters(sd, restore);
2117 } else {
2118 RADEONRestoreCrtcRegisters(sd, restore);
2119 RADEONRestoreFPRegisters(sd, restore);
2120 RADEONRestorePLLRegisters(sd, restore);
2121 RADEONRestoreCrtc2Registers(sd, restore);
2122 RADEONRestorePLL2Registers(sd, restore);
2123 }
2124 }
2125
2126 RADEONUnblank(sd);
2127
2128 RADEONInitDispBandwidth(sd, restore);
2129
2130 SetGamma(sd, 1.0, 1.0, 1.0);
2131 }
2132
2133 void DPMS(struct ati_staticdata *sd, HIDDT_DPMSLevel level)
2134 {
2135 int mask1 = (RADEON_CRTC_DISPLAY_DIS |
2136 RADEON_CRTC_HSYNC_DIS |
2137 RADEON_CRTC_VSYNC_DIS);
2138 int mask2 = (RADEON_CRTC2_DISP_DIS |
2139 RADEON_CRTC2_VSYNC_DIS |
2140 RADEON_CRTC2_HSYNC_DIS);
2141
2142 switch (level)
2143 {
2144 case vHidd_Gfx_DPMSLevel_On:
2145 /* Screen: On; HSync: On, VSync: On */
2146 if (sd->Card.IsSecondary)
2147 OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask2);
2148 else {
2149 OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask1);
2150 }
2151 break;
2152
2153 case vHidd_Gfx_DPMSLevel_Standby:
2154 /* Screen: Off; HSync: Off, VSync: On */
2155 if (sd->Card.IsSecondary)
2156 OUTREGP(RADEON_CRTC2_GEN_CNTL,
2157 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS,
2158 ~mask2);
2159 else {
2160 OUTREGP(RADEON_CRTC_EXT_CNTL,
2161 RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS,
2162 ~mask1);
2163 }
2164 break;
2165
2166 case vHidd_Gfx_DPMSLevel_Suspend:
2167 /* Screen: Off; HSync: On, VSync: Off */
2168 if (sd->Card.IsSecondary)
2169 OUTREGP(RADEON_CRTC2_GEN_CNTL,
2170 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS,
2171 ~mask2);
2172 else {
2173 OUTREGP(RADEON_CRTC_EXT_CNTL,
2174 RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS,
2175 ~mask1);
2176 }
2177 break;
2178
2179 case vHidd_Gfx_DPMSLevel_Off:
2180 /* Screen: Off; HSync: Off, VSync: Off */
2181 if (sd->Card.IsSecondary)
2182 OUTREGP(RADEON_CRTC2_GEN_CNTL, mask2, ~mask2);
2183 else {
2184 OUTREGP(RADEON_CRTC_EXT_CNTL, mask1, ~mask1);
2185 }
2186 break;
2187 }
2188 if (level == vHidd_Gfx_DPMSLevel_On)
2189 {
2190 if (sd->Card.IsSecondary) {
2191 if (sd->Card.MonType2 == MT_DFP) {
2192 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
2193 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
2194 if (sd->Card.Type >= R200) {
2195 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_DVO_EN, ~RADEON_FP2_DVO_EN);
2196 }
2197 } else if (sd->Card.MonType2 == MT_CRT) {
2198 RADEONDacPowerSet(sd, TRUE, !sd->Card.ReversedDAC);
2199 }
2200 } else {
2201 if (sd->Card.MonType1 == MT_DFP) {
2202 OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
2203 ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
2204 } else if (sd->Card.MonType1 == MT_LCD) {
2205
2206 OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON);
2207 usleep (sd, sd->Card.PanelPwrDly * 1000);
2208 OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON);
2209 } else if (sd->Card.MonType1 == MT_CRT) {
2210 if (sd->Card.HasSecondary) {
2211 RADEONDacPowerSet(sd, TRUE, sd->Card.ReversedDAC);
2212 } else {
2213 RADEONDacPowerSet(sd, TRUE, TRUE);
2214 if (sd->Card.HasCRTC2)
2215 RADEONDacPowerSet(sd, TRUE, FALSE);
2216 }
2217 }
2218 }
2219 }
2220 else if ((level == vHidd_Gfx_DPMSLevel_Off) ||
2221 (level == vHidd_Gfx_DPMSLevel_Suspend) ||
2222 (level == vHidd_Gfx_DPMSLevel_Standby))
2223 {
2224 if (sd->Card.IsSecondary) {
2225 if (sd->Card.MonType2 == MT_DFP) {
2226 OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
2227 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
2228 if (sd->Card.Type >= R200) {
2229 OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_DVO_EN);
2230 }
2231 } else if (sd->Card.Type == MT_CRT) {
2232 RADEONDacPowerSet(sd, FALSE, !sd->Card.ReversedDAC);
2233 }
2234 } else {
2235 if (sd->Card.MonType1 == MT_DFP) {
2236 OUTREGP (RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
2237 } else if (sd->Card.MonType1 == MT_LCD) {
2238 unsigned long tmpPixclksCntl = RADEONINPLL(sd, RADEON_PIXCLKS_CNTL);
2239
2240 if (sd->Card.IsMobility || sd->Card.IsIGP) {
2241 /* Asic bug, when turning off LVDS_ON, we have to make sure
2242 RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
2243 */
2244 OUTPLLP(sd, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
2245 }
2246
2247 OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
2248 ~(RADEON_LVDS_BLON | RADEON_LVDS_ON));
2249
2250 if (sd->Card.IsMobility || sd->Card.IsIGP) {
2251 OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
2252 }
2253 } else if (sd->Card.MonType1 == MT_CRT) {
2254 if (sd->Card.HasSecondary) {
2255 RADEONDacPowerSet(sd, FALSE, sd->Card.ReversedDAC);
2256 } else {
2257 /* single CRT, turning both DACs off, we don't really know
2258 * which DAC is actually connected.
2259 */
2260 RADEONDacPowerSet(sd, FALSE, TRUE);
2261 if (sd->Card.HasCRTC2) /* don't apply this to old radeon (singel CRTC) card */
2262 RADEONDacPowerSet(sd, FALSE, FALSE);
2263 }
2264 }
2265 }
2266 }
2267 }
2268
2269 BOOL RADEONInit(struct ati_staticdata *sd)
2270 {
2271 APTR int10_save = NULL;
2272
2273 sd->Card.IsSecondary = FALSE;
2274
2275 // RADEONPreInt10Save(sd, &int10_save);
2276 // RADEONPostInt10Check(sd, int10_save);
2277
2278 D(bug("[ATI] Radeon init\n"));
2279 #if AROS_BIG_ENDIAN
2280 D(bug("[ATI] BigEndian machine\n"));
2281 #endif
2282
2283 sd->Card.HasCRTC2 = TRUE;
2284 sd->Card.IsMobility = FALSE;
2285 sd->Card.IsIGP = FALSE;
2286 sd->Card.IsDellServer = FALSE;
2287 sd->Card.HasSingleDAC = FALSE;
2288
2289 sd->Card.PanelPwrDly = 500;
2290
2291 sd->Card.ChipErrata = 0;
2292
2293 D(bug("[ATI] flags:"));
2294
2295 switch (sd->Card.ProductID)
2296 {
2297 case 0x4c59:
2298 case 0x4c5a:
2299 case 0x4c57:
2300 case 0x4c58:
2301 case 0x4c64:
2302 case 0x4c66:
2303 case 0x4c67:
2304 case 0x5c61:
2305 case 0x5c63:
2306 case 0x4e50:
2307 case 0x4e51:
2308 case 0x4e52:
2309 case 0x4e53:
2310 case 0x4e54:
2311 case 0x4e56:
2312 case 0x3150:
2313 case 0x3154:
2314 case 0x5460:
2315 case 0x5464:
2316 case 0x4a4e:
2317 sd->Card.IsMobility = TRUE;
2318 D(bug(" IsMobility\n"));
2319 break;
2320
2321 case 0x4336:
2322 case 0x4337:
2323 sd->Card.IsMobility = TRUE;
2324 D(bug(" IsMobility\n"));
2325 case 0x4136:
2326 case 0x4237:
2327 sd->Card.IsIGP = TRUE;
2328 D(bug(" IsIGP\n"));
2329 break;
2330
2331 case 0x5835:
2332 case 0x7835:
2333 sd->Card.IsMobility = TRUE;
2334 D(bug(" IsMobility\n"));
2335 case 0x5834:
2336 case 0x7834:
2337 sd->Card.IsIGP = TRUE;
2338 sd->Card.HasSingleDAC = TRUE;
2339 D(bug(" IsIGP HasSingleDAC\n"));
2340 break;
2341
2342 default:
2343 sd->Card.HasCRTC2 = FALSE;
2344 }
2345 D(bug("\n"));
2346
2347 if (sd->Card.Type == R300 &&
2348 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
2349 == RADEON_CFG_ATI_REV_A11)
2350 sd->Card.ChipErrata |= CHIP_ERRATA_R300_CG;
2351
2352 if (sd->Card.Type == RV200 ||
2353 sd->Card.Type == RS200)
2354 sd->Card.ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS;
2355
2356 if (sd->Card.Type == RV100 ||
2357 sd->Card.Type == RS100 ||
2358 sd->Card.Type == RS200)
2359 sd->Card.ChipErrata |= CHIP_ERRATA_PLL_DELAY;
2360
2361 if ((sd->Card.Type == RS100) ||
2362 (sd->Card.Type == RS200) ||
2363 (sd->Card.Type == RS300)) {
2364 ULONG tom = INREG(RADEON_NB_TOM);
2365
2366 sd->Card.FbUsableSize = (((tom >> 16) -
2367 (tom & 0xffff) + 1) << 6) * 1024;
2368
2369 OUTREG(RADEON_CONFIG_MEMSIZE, sd->Card.FbUsableSize);
2370 } else {
2371 /* There are different HDP mapping schemes depending on single/multi funciton setting,
2372 * chip family, HDP mode, and the generation of HDP mapping scheme.
2373 * To make things simple, we only allow maximum 128M addressable FB. Anything more than
2374 * 128M is configured as invisible FB to CPU that can only be accessed from chip side.
2375 */
2376 sd->Card.FbUsableSize = INREG(RADEON_CONFIG_MEMSIZE);
2377 if (sd->Card.FbUsableSize > 128*1024*1024) sd->Card.FbUsableSize = 128*1024*1024;
2378 if ((sd->Card.Type == RV350) ||
2379 (sd->Card.Type == RV380) ||
2380 (sd->Card.Type == R420)) {
2381 OUTREGP (RADEON_HOST_PATH_CNTL, (1<<23), ~(1<<23));
2382 }
2383 }
2384
2385 /* Some production boards of m6 will return 0 if it's 8 MB */
2386 if (sd->Card.FbUsableSize == 0) sd->Card.FbUsableSize = 8192*1024;
2387
2388 #if 0
2389 if (sd->Card.IsSecondary) {
2390 /* FIXME: For now, split FB into two equal sections. This should
2391 * be able to be adjusted by user with a config option. */
2392 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
2393 RADEONInfoPtr info1;
2394
2395 pScrn->videoRam /= 2;
2396 pRADEONEnt->pPrimaryScrn->videoRam = pScrn->videoRam;
2397
2398 info1 = RADEONPTR(pRADEONEnt->pPrimaryScrn);
2399 info1->FbMapSize = pScrn->videoRam * 1024;
2400 info->LinearAddr += pScrn->videoRam * 1024;
2401 info1->MergedFB = FALSE;
2402 }
2403 #endif
2404
2405 sd->Card.R300CGWorkaround = (sd->Card.Type == R300 &&
2406 (INREG(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK)
2407 == RADEON_CFG_ATI_REV_A11);
2408
2409 D(bug("[ATI] R300CGWorkaroung = %s\n", sd->Card.R300CGWorkaround? "Yes":"No"));
2410
2411 sd->Card.MemCntl = INREG(RADEON_SDRAM_MODE_REG);
2412 sd->Card.BusCntl = INREG(RADEON_BUS_CNTL);
2413
2414 sd->Card.DDCReg = RADEON_GPIO_DVI_DDC;
2415
2416 RADEONGetVRamType(sd);
2417
2418 D(bug("[ATI] Video memory = %dMiB (%d bit %s SDRAM)\n", sd->Card.FbUsableSize >> 20,
2419 sd->Card.RamWidth, sd->Card.IsDDR ? "DDR":"SDR"));
2420
2421 BitmapInit(sd);
2422
2423 /* RADEONPreInitDDC */
2424 sd->Card.DDC1 = FALSE;
2425 sd->Card.DDC2 = FALSE;
2426 sd->Card.DDCBios = FALSE;
2427
2428 RADEONGetBIOSInfo(sd);
2429 RADEONQueryConnectedMonitors(sd);
2430 RADEONGetClockInfo(sd);
2431 RADEONGetPanelInfo(sd);
2432
2433 if (sd->Card.MonType1 == MT_UNKNOWN)
2434 sd->Card.MonType1 = MT_CRT;
2435
2436 return TRUE;
2437 }
2438
2439 /*
2440 Allocates some memory area on GFX card, which may be sufficient for bitmap
2441 with given size and depth. The must_have bit may be defined but doesn't
2442 have to. If it is TRUE, the allocator will do everything to get the memory -
2443 eg. it will throw other bitmaps away from it or it will shift them within
2444 GFX memory
2445 */
2446
2447 IPTR AllocBitmapArea(struct ati_staticdata *sd, ULONG width, ULONG height,
2448 ULONG bpp, BOOL must_have)
2449 {
2450 IPTR result;
2451 ULONG size = (((width * bpp + 63) & ~63) * height + 1023) & ~1023;
2452
2453 LOCK_HW
2454
2455 // Forbid();
2456 // result = (IPTR)Allocate(&sd->CardMem, size);
2457 // Permit();
2458 //
2459 // /*
2460 // If Allocate failed, make the 0xffffffff as return. If it succeeded, make
2461 // the memory pointer relative to the begin of GFX memory
2462 // */
2463 // if (result == 0) --result;
2464 // else result -= (IPTR)sd->Card.FrameBuffer;
2465
2466 Forbid();
2467 result = BitmapAlloc(sd, size);
2468 Permit();
2469
2470 D(bug("[ATI] AllocBitmapArea(%dx%d@%d) = %p\n", width, height, bpp, result));
2471
2472 UNLOCK_HW
2473
2474 /* Generic thing. Will be extended later */
2475 return result;
2476 }
2477
2478 VOID FreeBitmapArea(struct ati_staticdata *sd, IPTR bmp, ULONG width, ULONG height, ULONG bpp)
2479 {
2480 APTR ptr = (APTR)(bmp + sd->Card.FrameBuffer);
2481 ULONG size = (((width * bpp + 63) & ~63) * height + 1023) & ~1023;
2482
2483 LOCK_HW
2484
2485 D(bug("[ATI] FreeBitmapArea(%p,%dx%d@%d)\n",
2486 bmp, width, height, bpp));
2487
2488 Forbid();
2489 // Deallocate(&sd->CardMem, ptr, size);
2490 BitmapFree(sd, bmp, size);
2491 Permit();
2492
2493 UNLOCK_HW
2494 }
2495
2496 VOID SetGamma(struct ati_staticdata *sd, float r, float g, float b)
2497 {
2498 int i;
2499
2500 if (sd->Card.IsSecondary)
2501 PAL_SELECT(1);
2502 else
2503 PAL_SELECT(0);
2504
2505 for (i=0; i < 256; i++)
2506 {
2507 int ri = 256.0*pow((double)i / 256.0, 1/r);
2508 int gi = 256.0*pow((double)i / 256.0, 1/g);
2509 int bi = 256.0*pow((double)i / 256.0, 1/b);
2510
2511 RADEONWaitForFifo(sd, 32);
2512 OUTPAL(i, ri, gi, bi);
2513 }
2514 }
A totally sweet operating system