2 * ARM entry point, and initialization code.
9 #error ARM versions below ARMv6 not supported yet.
12 #define STACK_SIZE 0x1000
18 * Entry point for the kernel.
21 * r1 -> machine type number.
22 * r2 -> start address of ATAGS.
27 # Since these can only branch to 32MiB from instruction, put the address
28 # of the handlers nearby, and copy them too.
30 # Execution starts here too, so we set this to "Start."
34 ldr pc, prefetch_abort
41 ud: .word exception_ud
42 swi: .word exception_swi
43 prefetch_abort: .word exception_prefetch_abort
44 data_abort: .word exception_data_abort
45 unused: .word exception_unused
46 irq: .word exception_irq
47 fiq: .word exception_fiq
50 // Move vectors to 0x00000000.
63 // Switch to FIQ mode.
65 ldr sp, =fiq_stack + (STACK_SIZE)
68 ldr sp, =abort_stack + (STACK_SIZE)
71 ldr sp, =abort_stack + (STACK_SIZE)
74 ldr sp, =abort_stack + (STACK_SIZE)
77 ldr sp, =abort_stack + (STACK_SIZE)
80 ldr sp, =abort_stack + (STACK_SIZE)
88 // If lower than end, continue.
96 // DO NOT RETURN HERE.
99 // The stacks in the BSS section.