Fixed issue with return address in cpu_sim.py. Fixed bugs in compiler generation...

[trinary.git] / circuits / clock_gen_test.asc

Version 4\r
SHEET 1 880 680\r
WIRE 304 160 208 160\r
FLAG 304 160 CLK\r
FLAG -64 112 $G_Vdd\r
FLAG -64 176 $G_Vss\r
SYMBOL tpower -64 144 R0\r
SYMATTR InstName X1\r
SYMBOL clock_gen 128 80 R0\r
SYMATTR InstName X2\r
TEXT 168 304 Left 0 !.tran 200u\r